Page 1
E2E0055-19-41
¡ Semiconductor MSM63182A
This version: Apr. 1999
¡ Semiconductor
MSM63182A
4-Bit Microcontroller with Built-in 512-Dot Matrix LCD Drivers, Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The MSM63182A is an enhanced version of the MSM63182 in which supply currents have been
improved.
The MSM63182A is a CMOS 4-bit microcontroller with built-in 512-dot matrix LCD drivers and
operates at 0.9 V (min.). The MSM63182A is suitable for applications such as games, toys,
watches, etc. which are provided with an LCD display.
The MSM63182A is an M6318x series mask ROM-version product of OLMS-63K family, which
employs Oki's original CPU core nX-4/250.
The MSM63P180 is the one-time-programmable ROM version of MSM63188/A, having one-time
PROM (OTP) as internal program memory.
The MSM63P180 is used to evaluate the software development.
FEATURES
• Rich instruction set
439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock : 32.768 kHz crystal oscillator
High-speed clock : 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
4K words
Basic instruction length is 16 bits/1 word
• Data memory space
384 nibbles
• External data memory space
1/27
Page 2
¡ Semiconductor MSM63182A
64 Kbytes (expandable by using an I/O port)
• Stack level
Call stack level : 8 levels
Register stack level : 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output/high-impedance output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
Input port : 2 ports ¥ 4 bits
Output port : 4 ports ¥ 4 bits
Input-output port : 3 ports ¥ 4 bits
• Buzzer function
Buzzer output : 0.946 to 5.461 kHz (adjustable in 15 steps)
Buzzer output modes : Intermittent sound 1, 2; simple sound; continu-
ous sound
• LCD driver
Number of segments : 512 Max. (32 SEG ¥ 16 COM)
1/1 to 1/16 duty
1/4 or 1/5 bias (regulator built-in)
Selectable as all-on mode/all-off mode/power down mode/normal display mode
Adjustable contrast
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage : Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V,
2.20 ±0.20 V or 2.80 ±0.30 V
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
2/27
Page 3
¡ Semiconductor MSM63182A
• Timers and counter
Watchdog timer ¥ 1
Overflows in 2 sec.
100 Hz timer ¥ 1
Measurable in steps of 1/100 sec.
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Interrupt sources
External interrupt : 2
Internal interrupt : 6 (watchdog timer interrupt is a nonmask-
able interrupt)
• Operating voltage
When backup used : 0.9 to 2.7 V
(Low-speed clock operating)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
When backup not used : 1.8 to 5.5 V
(Operating frequency: 300 to 500 kHz)
2.2 to 5.5 V
(Operating frequency: 300 kHz to 1 MHz)
2.7 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
• Package:
128-pin plastic QFP (QFP128-P-1420-0.50-K) : (Product name: MSM63182A-xxxGS-K)
Chip : (Product name: MSM63182A-xxx)
xxx indicates a code number.
Differences Between the MSM63182 and the MSM63182A
The MSM63182A has the following improved characteristics.
• Supply currents (I
• The V
voltage during a halt of high-speed clock oscillation
DDL
DD1
, I
DD2
, I
) in DC characteristics
DD3
3/27
Page 4
¡ Semiconductor MSM63182A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. indicates that the power is supplied
to the circuits corresponding to the signal names inside from V
interface).
nX-4/250
L
TIMING
CONTROL
CBR
EBR
H
YX
RA
PC
A
ROM
4KW
(power supply for
DDI
SP
RSP
STACK
CAL: 8-level
REG: 16-level
RESET
TST1
TST2
XT0
XT1
OSC0
OSC1
V
DDH
V
DD
CB1
CB2
V
DD1
V
DD2
V
DD3
V
DD4
V
DD5
C1
C2
V
DDL
RST
TST
OSC
BACK
UP
BIAS
ALU
INSTRUCTION
DECODER
INT
4
INT
1
INT
1
CG
MIE
IR
RAM
384N
INT182
TBC
BLD
100HzTC
WDT
Z
BUS
CONTROL
DATA BUS
EXTMEM
BUZZER
INT
1
INPUT
PORT
OUTPUT
PORT
I/O
PORT
INT
1
LCD
&
DSPR
D0-7*
A0-15*
RD*
WR*
BD
BDB
P0.0-P0.3
P1.0-P1.3
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
P7.0-P7.3
P8.0-P8.3
P9.0-P9.3
PA.0-PA.3
COM1-16
SEG0-31
V
DDI
V
SS
4/27
Page 5
¡ Semiconductor MSM63182A
PIN CONFIGURATION (TOP VIEW)
DDI
BDBBDP7.0
P7.1
P7.2
(NC)
(NC)
(NC)
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
V
(NC)
(NC)
(NC)
(NC)
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
(NC)
(NC)
(NC)
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
1
1
110
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39404142434445464748495051525354555657585960616263
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
(NC)
(NC)
(NC)
P7.3
P6.0
P6.1
P6.2
P6.3
P1.0
P1.1
P1.2
P1.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P8.0
P8.1
P8.2
P8.3
P0.0
P0.1
P0.2
P0.3
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
(NC)
(NC)
(NC)
(NC)
(NC)
SS
DD1VDD2VDD3VDD4VDD5
V
V
C1
C2
DDH
V
CB1
V
CB2
DD
DDL
V
OSC1
OSC0
XT1
XT0
RESET
TST2
TST1
P5.3
(NC)
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
(NC)
(NC)
5/27
Page 6
¡ Semiconductor MSM63182A
PAD CONFIGURATION
Pad Layout
DD
75 P5.3
73 TST2
74 TST1
70 RESET
71 XT1
72 XT0
DDL
67 V
68 OSC1
69 OSC0
66 V
65 CB2
63 V
64 CB1
DDH
61 C1
62 C2
DD5
60 V
59 V
DD4
DD2
DD3
57 V
58 V
DD1
SS
56 V
55 V
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P0.3
P0.2
P0.1
P0.0
P8.3
P8.2
P8.1
P8.0
P9.3
P9.2
P9.1
P9.0
PA.3
PA.2
PA.1
PA.0
P1.3
P1.2
P1.1
P1.0
P6.3
P6.2
P6.1
P6.0
P7.3
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
54 SEG0
53 SEG1
52 SEG2
51 SEG3
50 SEG4
49 SEG5
48 SEG6
47 SEG7
46 SEG8
45 SEG9
44 SEG10
43 SEG11
42 SEG12
41 SEG13
40 SEG14
39 SEG15
38 SEG16
37 SEG17
36 SEG18
35 SEG19
34 SEG20
33 SEG21
32 SEG22
31 SEG23
30 SEG24
29 SEG25
28 SEG26
27 SEG27
26 SEG28
25 SEG29
24 SEG30
23 SEG31
Y
123456789
DDI
BD
V
P7.0
P7.1
BDB
COM1
P7.2
COM3
COM2
11
10
COM5
COM4
13
12
COM7
COM6
15
14
COM9
COM8
17
16
18
COM10
COM12
COM11
192120
COM15
COM14
COM13
22
COM16
Chip Size : 4.44 mm ¥ 4.92 mm
Chip Thickness : 350 mm (typ.)
Coordinate Origin : Chip center
Pad Hole Size : 100 mm ¥ 100 mm
Pad Size : 110 mm ¥ 110 mm
Minimum Pad Pitch : 140 mm
Note: The chip substrate voltage is VSS.
X
6/27
Page 7
¡ Semiconductor MSM63182A
Pad Coordinates
Pad No.
Pad
Name
X (µm) Y (µm)
1 P7.2 –1547 –2265
2 P7.1 –1407 –2265
3 P7.0 –1267 –2265
4 BD –1090 –2265
5 BDB –950 –2265
6V
DDI
–810 –2265
7 COM1 –630 –2265
8 COM2 –490 –2265
9 COM3 –350 –2265
10 COM4 –210 –2265
11 COM5 –70 –2265
12 COM6 70 –2265
13 COM7 210 –2265
14 COM8 350 –2265
15 COM9 490 –2265
16 COM10 630 –2265
17 COM11 770 –2265
18 COM12 910 –2265
19 COM13 1050 –2265
20 COM14 1190 –2265
21 COM15 1330 –2265
22 COM16 1470 –2265
23 SEG31 2075 –2170
24 SEG30 2075 –2030
25 SEG29 2075 –1890
26 SEG28 2075 –1750
27 SEG27 2075 –1610
28 SEG26 2075 –1470
29 SEG25 2075 –1330
30 SEG24 2075 –1190
31 SEG23 2075 –1050
32 SEG22 2075 –910
33 SEG21 2075 –770
34 SEG20 2075 –630
35 SEG19 2075 –490
36 SEG18 2075 –350
Pad No.
Pad
Name
X (µm) Y (µm) Pad No.
37 SEG17 2075 –210
38 SEG16 –70
39 SEG15 70
40 SEG14 210
41 SEG13 350
42 SEG12 490
43 SEG11 630
44 SEG10 770
45 SEG9 910
46 SEG8 1050
47 SEG7 1190
48 SEG6 1330
49 SEG5 1470
50 SEG4 1610
51 SEG3 1750
52 SEG2 1890
53 SEG1 2030
54 SEG0 2170
55 V
56 V
57 V
58 V
59 V
60 V
SS
DD1
DD2
DD3
DD4
DD5
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
2075
1575 2265
1425 2265
1275 2265
1125 2265
975 2265
825 2265
61 C1 675 2265
62 C2 525 2265
63 V
DDH
375 2265
64 CB1 225 2265
65 CB2 75 2265
66 V
67 V
DD
DDL
–75 2265
–225 2265
68 OSC1 –375 2265
69 OSC0 –525 2265
70 RESET –675 2265
71 XT1 –825 2265
72 XT0 –975 2265
Pad
Name
X (µm) Y (µm)
73 TST2 –1247 2265
74 TST1 –1387 2265
75 P5.3 –1548 2265
76 P5.2 2170
77 P5.1 2030
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105 –1890
P5.0
P4.3
P4.2
P4.1
P4.0
P0.3
P0.2
P0.1
P0.0
P8.3
P8.2
P8.1
P8.0
P9.3
P9.2
P9.1
P9.0
PA.3
PA.2
PA.1
PA.0
P1.3
P1.2
P1.1
P1.0
P6.3
P6.2
P6.1
106 P6.0 –2030
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
–2075
1890
1750
1610
1470
1330
1190
1050
910
770
630
490
350
210
70
–70
–210
–350
–490
–630
–770
–910
–1050
–1190
–1330
–1470
–1610
–1750
107 P7.3 –2075 –2170
7/27
Page 8
¡ Semiconductor MSM63182A
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63182A are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol Pin Type
V
V
V
V
V
V
V
DD
SS
DD1
DD2
DD3
DD4
DD5
52 —
41 —
42
43
44 —
45
46
C1 47 —
Power
Supply
C2 48 —
V
V
V
DDI
DDL
DDH
110 —
53 —
49 —
CB1 50 —
CB2 51 —
XT0 58 I
XT1 57 O
Oscillation
OSC0 55 I
OSC1 54 O
TST1 60 I
Test
TST2 59 I
Reset RESET 56 I
Description
Positive power supply
Negative power supply
Power supply pins for LCD bias (internally generated).
Capacitors (0.1 mF) should be connected between these pins and
.
V
SS
Capacitor connection pins for LCD bias generation.
A capacitor (0.1 mF) should be connected between C1 and C2.
Positive power supply pin for external interface
(power supply for input, output, and input-output ports)
Positive power supply pin for internal logic (internally generated).
A capacitor (0.1 mF) should be connected between this pin and V
SS
.
Voltage multiplier pin for power supply backup (internally generated).
A capacitor (1.0 mF) should be connected between this pin and VSS.
Pins to connect a capacitor for voltage multiplier.
A capacitor (1.0 mF) should be connected between CB1 and CB2.
Low-speed clock oscillation pins.
A 32.768 kHz crystal should be connected between XT0 and XT1,
and C
(5 to 25 pF) should be connected between XT0 and VSS.
G
High-speed clock oscillation pins.
A ceramic resonator and capacitors (C
oscillation resistor (R
) should be connected to these pins.
OS
, CL1) or external
L0
Input pins for testing.
A pull-down resistor is internally connected to these pins.
The user cannot use these pins.
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
Then, setting this pin to "L" level starts executing an instruction
from address 0000H.
A pull-down resistor is internally connected to this pin.
Buzzer
BD 108 O
BDB 109 O
Buzzer output pin (non-inverted output)
Buzzer output pin (inverted output)
8/27
Page 9
¡ Semiconductor MSM63182A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol
P0.0/INT5
P0.1/INT5
P0.2/INT5
P0.3/INT5
P1.0/INT5
P1.1/INT5
P1.2/INT5
P1.3/INT5
P4.0/A0
P4.1/A1
P4.2/A2
P4.3/A3
P5.0/A4
P5.1/A5
P5.2/A6
P5.3/A7
P6.0/A8
P6.1/A9
Port
P6.2/A10
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15
P8.0/RD
P8.1/WR
P8.2
P8.3/INT4
P9.0/D0
P9.1/D1
P9.2/D2
P9.3/D3
PA.0/D4
PA.1/D5
PA.2/D6
Pin
78
77
76
75
94
93
92
91
74
73
72
71
70
69
68
61
98
97
96
95
107
106
105
99
82
81
80
79
86
85
84
83
90
89
88
Type Description
4-bit input ports.
Pull-up resistor input, pull-down resistor input, or
I
high-impedance input is selectable for each bit.
I
4-bit output ports.
P-channel open drain output, N-channel open drain output,
O
CMOS output, or high-impedance output is selectable for each
bit.
O
O
O
4-bit input-output ports.
In input mode, pull-up resistor input, pull-down resistor input,
I/O
or high-impedance input is selectable for each bit.
In output mode, P-channel open drain output, N-channel open
drain output, CMOS output, or high-impedance output is
selectable for each bit.
I/O
I/O
PA.3/D7
87
9/27
Page 10
¡ Semiconductor MSM63182A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG0
SEG1
SEG2
SEG3
LCD
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
Pin Type
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
O
O
Description
LCD common signal output pins
LCD segment signal output pins
10/27
Page 11
¡ Semiconductor MSM63182A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol
SEG25
SEG26
SEG27
LCD
SEG28
SEG29
SEG30
SEG31
Pin Type
10
9
8
7
6
5
4
O
Description
LCD segment signal output pins
11/27
Page 12
¡ Semiconductor MSM63182A
Table 2 shows the secondary functions of each pin of the MSM63182A.
Table 2 Pin Descriptions (Secondary Functions)
Function Symbol
P8.3/INT4
P0.0/INT5
P0.1/INT5
External
Interrupt
P0.2/INT5
P0.3/INT5
P1.0/INT5
P1.1/INT5
P1.2/INT5
P1.3/INT5
Pin
79
78
77
76
75
94
93
92
91
Type Description
External 4 interrupt input pin.
I
The change of input signal level causes an interrupt to occur.
External 5 interrupt input pins.
The change of input signal level causes an interrupt to occur.
The Port 0 Interrupt Enable register (P0IE) and Port 1 Interrupt
Enable register (P1IE) enable or disable an interrupt for each bit.
I
12/27
Page 13
¡ Semiconductor MSM63182A
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function Symbol
P4.0/A0
P4.1/A1
P4.2/A2
P4.3/A3
P5.0/A4
P5.1/A5
P5.2/A6
P5.3/A7
P6.0/A8
P6.1/A9
P6.2/A10
External
Memory
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15
P9.0/D0
P9.1/D1
P9.2/D2
P9.3/D3
PA.0/D4
PA.1/D5
PA.2/D6
PA.3/D7
P8.0/RD
P8.1/WR
Pin
74
73
72
71
70
69
68
61
98
97
96
95
107
106
105
99
86
85
84
83
90
89
88
87
82
81
Type
Address output bus for external memory
O
Data bus for external memory
I/O
O Read signal output pin for external memory (negative logic)
O Write signal output pin for external memory (negative logic)
Description
13/27
Page 14
¡ Semiconductor MSM63182A
ABSOLUTE MAXIMUM RATINGS
= 0 V)
(V
SS
Parameter Symbol Condition Rating Unit
Power Supply Voltage 6
DD1
V
DD2
V
DD3
V
DD4
V
DD5
V
V
DDH
DDL
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
T
STG
DD
DDI
IN1
IN2
DDI
DD1
DD2
DD3
DD4
DD5
DDI
DDH
–0.3 to +1.6Power Supply Voltage 1 Ta = 25°CV
–0.3 to +2.9Power Supply Voltage 2 Ta = 25°C
–0.3 to +4.2Power Supply Voltage 3 Ta = 25°C
–0.3 to +5.5Power Supply Voltage 4 Ta = 25°C
–0.3 to +6.8Power Supply Voltage 5 Ta = 25°C
V
V
V
V
V
–0.3 to +6.0Ta = 25°C V
–0.3 to +6.0Power Supply Voltage 7 Ta = 25°CV
–0.3 to +6.0Power Supply Voltage 8 Ta = 25°C
–0.3 to +6.0Power Supply Voltage 9 Ta = 25°CV
–0.3 to V
Input, Ta = 25°CV
Output, Ta = 25°CV
Output, Ta = 25°CV
Output, Ta = 25°CV
Output, Ta = 25°CV
Output, Ta = 25°CV
–0.3 to V
–0.3 to V
–0.3 to V
–0.3 to V
–0.3 to V
–0.3 to V
–0.3 to V
Output, Ta = 25°CV
Output, Ta = 25°CV
–0.3 to V
–0.3 to V
DD
DDI
DD1
DD2
DD3
DD4
DD5
DD
DDI
DDH
+ 0.3Input Voltage 1 VDD Input, Ta = 25°CV
+ 0.3Input Voltage 2 V
+ 0.3Output Voltage 1 V
+ 0.3Output Voltage 2 V
+ 0.3Output Voltage 3 V
+ 0.3Output Voltage 4 V
+ 0.3Output Voltage 5 V
+ 0.3Output Voltage 6 VDD Output, Ta = 25°CV
+ 0.3Output Voltage 7 V
+ 0.3Output Voltage 8 V
–55 to +150Storage Temperature —
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
14/27
Page 15
¡ Semiconductor MSM63182A
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(V
= 0 V)
SS
Parameter Symbol Condition Range Unit
Operating Temperature T
Operating Voltage
Crystal Oscillation Frequency f
Ceramic Oscillation Frequency
External RC Oscillator Resistance
• When backup is not used
op
V
DD
V
DDI
XT
—
— 0.9 to 2.7 V
—
—
VDD = 1.2 to 2.7 V
f
CM
VDD = 1.2 to 2.7 V
R
OS
–20 to +70 °C
0.9 to 5.5 V
30 to 35 kHz
300k to 500k
Hz
200k to 1MVDD = 1.5 to 2.7 V
100 to 300
kW
50 to 300VDD = 1.5 to 2.7 V
Parameter Symbol Condition Range Unit
Operating Temperature T
Operating Voltage
Crystal Oscillation Frequency f
Ceramic Oscillation Frequency
External RC Oscillator Resistance
(V
= 0 V)
SS
op
V
DD
V
DDI
XT
—
— 1.8 to 5.5 V
—
—
–20 to +70 °C
1.8 to 5.5 V
30 to 35 kHz
300k to 500kVDD = 1.8 to 5.5 V
f
CM
VDD = 2.2 to 5.5 V
300k to 1M
Hz
200k to 2MVDD = 2.7 to 5.5 V
100 to 300VDD = 1.8 to 5.5 V
R
OS
VDD = 2.2 to 5.5 V
50 to 300
kW
30 to 300VDD = 2.7 to 5.5 V
15/27
Page 16
¡ Semiconductor MSM63182A
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter Symbol Condition
Voltage
DD2
Voltage Temperature Deviation DV
DD2
V
Voltage V
DD1
V
Voltage V
DD3
V
Voltage V
DD4
V
Voltage V
DD5
Voltage
V
DDH
(Backup used)
V
Voltage V
DDL
Crystal Oscillation Hold Voltage
External Crystal Oscillator Capacitance
Internal Crystal Oscillator Capacitance
External Ceramic Oscillator
Capacitance
POR Voltage V
Non-POR Voltage V
(V
V
V
V
T
C
= V
DD
= 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
DDI
1/5 bias, 1/4 bias
DD2
DD2
DD1
(Ta = 25°C)
1/5 bias, 1/4 bias V
1/5 bias
DD3
1/4 bias (connect
V
DD3
1/5 bias
DD4
1/4 bias
1/5 bias
DD5
1/4 bias
High-speed clock oscillation
stopped
V
DDH
High-speed clock oscillation
DD
(Ceramic oscillation, 1 MHz)
V
DD
High-speed clock
oscillation stopped
DDL
High-speed clock oscillation
(V
= 1.2 to 5.5 V)
DD
STA
Oscillation start time:
within 5 seconds
Backup V
HOLD
STOP
C
G
C
D
CSA2.00MG (Murata
L0, 1
OS
POR1
POR2
MFG.-make) used
V
DD
V
DD
DD
V
DD
DD
Mea-
Max.Typ.Min.
Unit
suring
Circuit
V
mV/°C
V
V
V
—
and V
DD2
1.91.81.7V
—–4—V
DD2
DD2
DD2
DD2
DD2
DD2
DD2
Typ.+ 0.2
Typ.+ 0.3
Typ.+ 0.2
Typ.+ 0.4
Typ.+ 0.3
Typ.+ 0.5
Typ.+ 0.4
Typ.– 0.2
Typ.– 0.3
)
Typ.– 0.2
Typ.– 0.4
Typ.– 0.3
Typ.– 0.5
Typ.– 0.4
1/2 ¥ V
3/2 ¥ V
V
2 ¥ V
3/2 ¥ V
5/2 ¥ V
2 ¥ V
3.0—2.8 V
= 1.5 V
2.7—2.0
= 1.5 V
1.81.30.8
5.5—1.2
——1.0Crystal Oscillation Start Voltage V
V
1
V
V
V
——0.9
——1.7Backup not used V
—ms
—pF
—pF
5.0—0.1Crystal Oscillation Stop Detect Time
25—5
302520
—30—
pF
= 3.0 V
—pF
= 1.5 V V
= 3.0 V V
= 1.5 V V
= 3.0 V V
16128Internal RC Oscillator Capacitance C
0.4—0.0
0.7—0.0V
1.5—1.2
3.0—2.0V
Notes: 1. "T
reset occurs.
2. "POR" denotes Power On Reset.
3. "V
up to VDD.
4. "V
again rises up to VDD.
" indicates that if the crystal oscillator stops over the value of T
STOP
" indicates that POR occurs when VDD falls from VDD to V
POR1
" indicates that POR does not occur when VDD falls from VDD to V
POR2
, the system
STOP
and again rises
POR1
POR2
and
16/27
Page 17
¡ Semiconductor MSM63182A
DC Characteristics (continued)
• When backup is used
(VDD = V
= 1.5 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
DDI
Parameter Symbol Condition
CPU is in HALT state.
Supply Current 1
(High-speed clock oscillation
I
DD1
stopped)
CPU is in HALT state.
Supply Current 2
LCD is in Power Down mode.
I
DD2
(High-speed clock oscillation
stopped)
Supply Current 3 I
DD3
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
CPU is in operation at high-speed oscillation
DD4
(RC oscillation, f = approx. 720 kHz, R
CPU is in operation at high-speed oscillation
DD5
(Ceramic oscillation, 1 MHz)
• When backup is not used
Ta = –20 to +50°C
Ta = –20 to +70°C
Ta = –20 to +50°C
Ta = –20 to +70°C
= 51 kW)
OS
Mea-
Max.Typ.Min.
Unit
suring
Circuit
6.55.1—
mA
7.05.1—
5.03.9—
mA
7.03.9—
1
1713—
mA
800600—Supply Current 4 I
900700—Supply Current 5 I
mA
mA
(VDD = V
= 3.0 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
DDI
Parameter Symbol Condition
CPU is in HALT state.
(High-speed clock oscillation
Supply Current 1
I
DD1
stopped)
CPU is in HALT state.
LCD is in Power Down mode.
Supply Current 2
I
DD2
(High-speed clock oscillation
stopped)
Supply Current 3 I
DD3
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
CPU is in operation at
Supply Current 4 I
DD4
high-speed oscillation
(RC oscillation)
CPU is in operation at high-speed oscillation
DD5
(Ceramic oscillation, 2 MHz)
Ta = –20 to +50°C
Ta = –20 to +70°C
Ta = –20 to +50°C
Ta = –20 to +70°C
f = approx. 800 kHz,
= 51 kW
R
OS
f = approx. 500 kHz,
= 100 kW
R
OS
—
—
Mea-
Max.Typ.Min.
Unit
suring
Circuit
2.82.4—
mA
3.02.4—
2.21.7—
mA
2.51.7—
8.06.3—
mA
1
600450
mA
450350
1000850—Supply Current 5 I
mA
17/27
Page 18
¡ Semiconductor MSM63182A
DC Characteristics (continued)
(VDD = V
DDI
V
DD4
= V
= 4.4 V, V
Parameter Symbol Condition
Output Current 1
(P4.0 to P4.3)
(P5.0 to P5.3)
I
OH1
V
= V
OH1
– 0.5 V –1.0 mA
DDI
(P6.0 to P6.3)
(PA.0 to PA.3)
I
OL1
V
= 0.5 V 5.0 mA
OL1
Output Current 2
(BD, BDB)
Output Current 3
(SEG0 to SEG31)
(COM1 to COM16)
Output Current 4
(OSC1)
I
OH2
I
OL2
I
OH3
I
OHM3
I
OHM3S
I
OMH3
I
OMH3S
I
OML3
OML3S
OLM3
I
OLM3S
OL3
I
OH4R
I
OL4R
I
OH4C
I
OL4C
V
= VDD – 0.7 V –2.0 mA
OH2
V
= 0.7 V 6.0 mA
OL2
V
= V
OH3
V
OHM3
V
OHM3S
V
OMH3
V
OMH3S
V
OML3
V
OML3S
V
OLM3
V
OLM3S
V
= VSS + 0.2 V (VSS level)
OL3
V
OH4R
= V
= V
= V
= V
= V
= V
= V
= V
= V
– 0.2 V (V
DD5
+ 0.2 V (V
DD4
DD4
+ 0.2 V (V
DD3
DD3
+ 0.2 V (V
DD2
DD2
+ 0.2 V (V
DD1
DD1
– 0.5 V
DDH
– 0.2 V (V
– 0.2 V (V
– 0.2 V (V
– 0.2 V (V
(RC oscillation)
V
= 0.5 V
OL4R
(RC oscillation)
V
= V
OH4C
DDH
– 0.5 V
(ceramic oscillation)
V
= 0.5 V
OL4C
(ceramic oscillation)
Output Leakage
(P4.0 to P4.3)
I
OOH
VOH = V
DDI
(P5.0 to P5.3)
(P6.0 to P6.3)
(PA.0 to PA.3)
I
OOL
VOL = V
SS
= 3.0 V, VSS = 0 V, V
DDH
= 5.5 V, Ta = –20 to +70°C unless otherwise specified)
DD5
= 1.5 V
V
DDI
= 3.0 V
V
DDI
= 5.0 V
V
DDI
= 1.5 V
V
DDI
V
= 3.0 V
DDI
= 5.0 V
V
DDI
V
= 1.5 V
DD
= 3.0 V
V
DD
= V
V
DD
DDH
= 1.5 V
V
DD
V
= 3.0 V
DD
= V
V
DD
DDH
level)
DD5
level)
DD4
level)
DD4
level)
DD3
level)
DD3
level)
DD2
level)
DD2
level)
DD1
level)
DD1
= V
V
DD
DDH
= V
V
DD
DDH
DDH
= V
V
DD
DDH
DDH
= V
V
DD
DDH
DDH
= V
V
DD
DDH
= 1.1 V, V
DD1
Min.
–2.0
–5.0
–8.0
0.2
1.0
1.5
–2.5
–6.0
= 5.0 V
–9.0
0.4
2.0
= 5.0 V
3.0
—
4
—
4
—
4
—
4
—
4
= 3.0 V
–2.5
= 5.0 V –1.0 mA–2.0–3.5
= 3.0 V
= 5.0 V 3.5 mA2.01.0
= 3.0 V
= 5.0 V –100 mA–280–450
= 3.0 V
= 5.0 V 450 mA200100
—
–0.3
Typ.
–1.2
–3.0
–4.0
1.2
3.0
4.0
–1.3
–4.0
–5.5
1.3
4.0
5.5
—
—
—
—
—
—
—
—
—
—
–1.5
—
—
= 2.2 V, V
DD2
Max.
–0.2 mA
–1.5 mA
–0.4 mA
–3.0 mA
–0.75 mA
–60 mA–180–300VDD = V
300 mA12060VDD = V
Unit
2.0 mA
8.0 mA
2.5 mA
9.0 mA
–4 mA
— mA
–4
mA
—
mA
–4
mA
—
mA
–4
mAI
—
mAI
–4
mA
mAI
—
2.5 mA1.50.75VDD = V
0.3 mA
— mA
= 3.3 V,
DD3
Circuit
Mea-
suring
2
18/27
Page 19
¡ Semiconductor MSM63182A
DC Characteristics (continued)
(VDD = V
DDI
V
DD4
= V
= 4.4 V, V
Parameter Symbol Condition
Input Current 1
V
= V
IH1
(P0.0 to P0.3)
(P1.0 to P1.3)
I
IH1
(when pulled down)
DDI
(P8.0 to P8.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
Input Current 2
(OSC0)
I
I
IH1Z
I
IL1Z
I
I
IH2R
I
IL2R
I
IH2C
I
IL2C
V
IL1
IL2
IL1
(when pulled up)
V
IH1
V
IL1
V
IL2
(when pulled up)
V
IH2R
V
IL2R
V
IH2C
(ceramic oscillation)
V
IL2C
(ceramic oscillation)
= V
SS
= V
(in a high impedance state) 1.0 mA—0.0
DDI
= V
(in a high impedance state) 0.0 mA—–1.0
SS
= V
SS
= V
(RC oscillation) 1.0 mA—0.0
DDH
= VSS (RC oscillation) 0.0 mA—–1.0
= V
DDH
= V
SS
Input Current 3
(RESET)
I
I
IH3
IL3
V
= V
IH3
DD
V
= V
IL3
SS
Input Current 4
(TST1, TST2)
I
I
IH4
IL4
V
= V
IH4
DD
V
= V
IL4
SS
= 3.0 V, VSS = 0 V, V
DDH
= 5.5 V, Ta = –20 to +70°C unless otherwise specified)
DD5
= 1.5 V
V
DDI
= 3.0 V
V
DDI
= 5.0 V
V
DDI
V
= 1.5 V
DDI
= 3.0 V
V
DDI
= 5.0 V
V
DDI
V
= V
DD
DDH
= V
V
DD
DDH
= V
V
DD
DDH
= V
V
DD
DDH
= V
V
DD
DDH
= V
V
DD
DDH
= 1.5 V
V
DD
= 3.0 V 600 mA350150
V
DD
= V
V
DD
DDH
= 3.0 V 1.5 mA1.00.5
V
DD
= V
V
DD
DDH
= 1.1 V, V
DD1
Min.
2
30
70
–30
–180
–600
= 3.0 V
= 5.0 V
= 3.0 V
= 5.0 V
= 3.0 V
= 5.0 V
–200
–600
0.1
0.75
–1.0
–3.0
10
= 5.0 V 2.0 mA1.00.5
= 5.0 V 4.0 mA2.51.25
Typ.
10
90
250
–10
–90
–250
–110
–350
0.5
1.5
–0.5
–1.5
50
= 2.2 V, V
DD2
Max.
–150 mA
–0.1 mA
–0.75 mA
Unit
30 mA
180 mA
600 mA
–2 mA
–30 mA
–70 mA
–30 mA
1.0 mA
3.0 mA
80 mA
0.0 mA—–1.0
300 mA15050VDD = 1.5 V
0.0 mA—–1.0
= 3.3 V,
DD3
Mea-
suring
Circuit
3
19/27
Page 20
¡ Semiconductor MSM63182A
DC Characteristics (continued)
Parameter Symbol Condition
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
Input Voltage 2
(OSC0)
Input Voltage 3
(RESET, TST1, TST2)
Hysteresis Width 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(PA.0 to PA.3)
(VDD = V
V
IH1
V
IL1
V
IH2
V
IL2
V
IH3
V
IL3
DV
T1
V
DDI
DD4
= V
= 4.4 V, V
= 3.0 V, VSS = 0 V, V
DDH
= 5.5 V, Ta = –20 to +70°C unless otherwise specified)
DD5
V
= 1.5 V 1.2 — 1.5 V
DDI
V
= 3.0 V 2.4 — 3.0 V
DDI
V
= 5.0 V 4.0 — 5.0 V
DDI
V
= 1.5 V 0.0 — 0.3 V
DDI
V
= 3.0 V 0.0 — 0.6 V
DDI
= 5.0 V 0.0 — 1.0 V
V
DDI
VDD = V
VDD = V
VDD = V
VDD = V
V
= 3.0 V 2.4 — 3.0 V
DDH
= 5.0 V 4.0 — 5.0 V
DDH
= 3.0 V 0.0 — 0.6 V
DDH
= 5.0 V 0.0 — 1.0 V
DDH
= 1.5 V 1.35 — 1.5 V
DD
= 1.1 V, V
DD1
VDD = 3.0 V 2.4 — 3.0 V
= V
V
DD
= 5.0 V 4.0 — 5.0 V
DDH
VDD = 1.5 V 0.0 — 0.15 V
VDD = 3.0 V 0.0 — 0.6 V
V
DD
= V
V
V
V
= 5.0 V 0.0 — 1.0 V
DDH
= 1.5 V 0.05 0.1 0.3 V
DDI
= 3.0 V 0.2 0.5 1.0 V
DDI
= 5.0 V 0.25 1.0 1.5 V
DDI
= 2.2 V, V
DD2
Max.Typ.Min.
DD3
Unit
= 3.3 V,
Measuring
Circuit
4
Hysteresis Width 2
(RESET, TST1, TST2)
Input Pin Capacitance
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
DV
C
VDD = 1.5 V 0.05 0.1 0.3 V
= 3.0 V 0.2 0.5 1.0 V
T2
IN
V
DD
V
DD
= V
= 5.0 V 0.25 1.0 1.5 V
DDH
———5pF
1
20/27
Page 21
¡ Semiconductor MSM63182A
p
Measuring circuit 1
CB1
C
b12
CB2
C1
C
12
C2
q
OSC0
*1
w
OSC1
Ca, Cb, Cc, Cd, Ce, Cl, C
C
, C
b12
h
C
G
C
L0
C
L1
Ceramic Resonator
C
G
XT0
XT1
V
SS
VDDV
A
12
DDIVDD1
C
: 0.1 mF
V
C
a
b
V
DD2
V
C
V
DD3
c
V
C
V
DD4
d
V
C
V
DD5
e
V
V
DDH
DDL
C
V
C
h
l
V
V
*1 RC Oscillator
32.768 kHz
Crystal
: 1 mF
: 15 pF
: 30 pF
: 30 pF
: CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
R
OS
Ceramic Oscillator
C
q
w
L0
Ceramic Resonator
q
Measuring circuit 2
V
IH
*2
V
IL
C
L1
INPUT OUTPUT
w
V
SS
VDDV
DDIVDD1VDD2VDD3VDD4VDD5VDDH
V
DDL
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the s
ecified output pins.
*3
A
21/27
Page 22
¡ Semiconductor MSM63182A
Measuring circuit 3
*4
A
Measuring circuit 4
V
IH
*4
INPUT OUTPUT
VSSVDDV
DDIVDD1VDD2VDD3VDD4VDD5VDDH
INPUT OUTPUT
V
DDL
Waveform
Monitoring
V
IL
V
V
SS
DDVDDIVDD1VDD2VDD3VDD4VDD5VDDH
V
DDL
*4 Measured at the specified input pins.
22/27
Page 23
¡ Semiconductor MSM63182A
AC Characteristics (External Memory Interface)
(VDD = 0.9 to 5.5 V, V
= 1.8 to 5.5 V, VSS = 0 V, V
DDH
specified)
(1) Reading from External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Read Cycle Time
RD Output Delay Time
Output Valid Time
External Memory Output Delay Time
(b) When CPU operates at 2 MHz (V
Parameter
Read Cycle Time
RD Output Delay Time
Output Valid Time
External Memory Output Delay Time
Symbol Condition Min. Typ. Max. Unit
t
RC
t
OE
t
OHA
t
DO
= 2.7 to 5.5 V)
DDH
Symbol Condition Min. Typ. Max. Unit
t
RC
t
OE
t
OHA
t
DO
= 5.0 V, Ta = –20 to +70°C unless otherwise
DDI
—
—
—
—
—
—
—
—
—
—
—
—
1.0 ms
—
—
—
61.0 ms
—
—
—
—
—
—
—
—
5.0
5.0
5.0
—
100
100
150
ms
ms
ms
ns
ns
ns
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
System clock
P7 - P4
(A15 - A0)
P8.0
(RD)
PA, P9
(D7 - D0)
Port setup value
Port setup value
MOVXB obj, xadr16
MOVXB obj, [RA]
Address output Port setup value
t
OE
S2S1S2S1S2S1
t
RC
5 V (V
0 V (V
5 V (V
0 V (V
t
OHA
5 V (V
Port setup valueInput data
t
DO
0 V (V
DDI
SS
DDI
SS
DDI
SS
)
)
)
)
)
)
23/27
Page 24
¡ Semiconductor MSM63182A
(2) Writing to External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Write Cycle Time
Address Setup Time
Write Time
Write Recovery Time
Data Setup Time
Data Hold Time
Symbol Condition Min. Typ. Max. Unit
t
t
t
t
WR
t
t
WC
AS
W
DS
DH
—
—
—
—
—
—
—
—
—
—
—
—
61.0 ms
30.5
15.3
15.3
45.8
15.3
—
—
—
—
—
—
ms
ms
ms
ms
ms
(b) When CPU operates at 2 MHz (V
Parameter
Write Cycle Time
Address Setup Time
Write Time
Write Recovery Time
Data Setup Time
Data Hold Time
= 2.7 to 5.5 V)
DDH
Symbol Condition Min. Typ. Max. Unit
t
WC
t
AS
t
W
t
WR
t
DS
t
DH
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB [RA], obj or MOVXB xadr16, obj
System clock
—
—
—
—
—
—
1.0 ms
0.4
0.2
0.2
0.7
0.2
—
—
—
—
—
—
—
—
—
—
—
—
ms
ms
ms
ms
ms
S2S1S2S1S2S1
t
WC
(A15 - A0)
PA, P9
(D7 - D0)
P8.1
(WR)
Address output Port setup valuePort setup valueP7 - P4
5 V (V
0 V (V
5 V (V
Output data Port setup valuePort setup value
t
t
DS
DH
0 V (V
5 V (V
0 V (V
t
tWt
AS
WR
DDI
SS
DDI
SS
DDI
SS
)
)
)
)
)
)
24/27
Page 25
¡ Semiconductor MSM63182A
APPLICATION CIRCUITS
•RC oscillation is selected as high-speed
LCD
oscillation.
•Ports are powered from external memory
power source.
•C
is an IC power supply bypass capacitor.
v
•Values of C
C
, and CG, are for reference only.
h
, Cb, Cc, Cd, Ce, Cl, C
a
b12
, C12,
Crystal
32.768 kHz
COM1-16
XT0
C
G
5 to
25 pF
C
1.5 V
v
C
l
C
e
C
d
C
c
C
b
C
a
C
0.1 mF
C
b12
h
1.0 mF
1.0 mF
0.1 mF
0.1 mF
0.1 mF
0.1 mF
0.1 mF
0.1 mF
XT1
V
DDH
V
DD
CB1
CB2
V
DDL
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
MSM63182A
C1
C
12
Push SW
0.1 mF
C2
SEG0-31
OSC0
OSC1
P8.3
P8.2
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
R
OS
RESET
Buzzer
Open
TST1
TST2
V
DDI
BD
Note: V
Be sure to connect the V
device or to the positive power supply pin of the external memory.
V
BDB
P4-7
A15-0
External
V
SS
P9, PA
P8.0
P8.1
is the power supply pin for the input, output, and input-output ports.
DDI
pin either to the positive power supply pin (VDD) of this
DDI
Memory
D7-0
(64K ¥ 8 bits)
RD
WR
V
Application Circuit Example with Power Supply Backup
DD
5.0 V
SS
25/27
Page 26
¡ Semiconductor MSM63182A
APPLICATION CIRCUITS (continued)
•Ceramic oscillation is selected as high-speed
LCD
oscillation.
•Ports, external memory, and IC share their
power supply.
•C
is an IC power supply bypass capacitor.
v
•Values of C
C
, and CL1 are for reference only.
L0
, Cb, Cc, Cd, Ce, Cl, C12, CG,
a
C
V
DD
G
5 to 25 pF
5.0 V
C
v
C
l
C
e
C
d
C
c
C
b
C
a
Buzzer
Crystal
32.768 kHz
Open
0.1 mF
0.1 mF
0.1 mF
0.1 mF
0.1 mF
0.1 mF
0.1 mF
C
12
0.1 mF
Push SW
Open
XT0
XT1
V
DDH
V
DD
CB1
CB2
V
DDL
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
C1
C2
RESET
TST1
TST2
BD
COM1-16
SEG0-31
MSM63182A
OSC0
OSC1
P8.3
P8.2
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
V
DDI
CL0 30 pF
C
L1
30 pF
Ceramic
Resonator
(Example: 1 MHz)
V
DD
Note: V
Be sure to connect the V
device or to the positive power supply pin of the external memory.
V
DD
BDB
P4-7
A15-0
External
V
SS
P9, PA
P8.0
P8.1
is the power supply pin for the input, output, and input-output ports.
DDI
pin either to the positive power supply pin (VDD) of this
DDI
D7-0
Memory
(64K ¥ 8 bits)
RD
WR
V
SS
Application Circuit Example with No Power Supply Backup
26/27
Page 27
¡ Semiconductor MSM63182A
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-1420-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.19 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
27/27
Page 28
E2Y0002-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
Loading...