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E2B0021-27-Y2
¡ Semiconductor
¡ Semiconductor
This version: Nov. 1997
Previous version: Mar. 1996
MSM5839C
MSM5839C
40-DOT SEGMENT DRIVER
GENERAL DESCRIPTION
The MSM5839C is a dot matrix LCD segment driver LSI which is fabricated using low power
CMOS metal gate technology. This LSI consists of two 20-bit shift registers, two 20-bit latches,
a 40-bit level shifter and a 40-bit 4-level driver.
It converts serial data, which is received from LCD controller LSI, into parallel data and outputs
LCD driving waveform to the LCD panel.
Expansion of display can easily be made by increasing the number of characters and character
patterns.
This LSI can drive a variety of LCD panels because the bias voltage, which determines an LCD
driving voltage, can be optionally supplied from the external source.
FEATURES
• Supply voltage : 4.5 to 5.5V
• LCD driving voltage : 4 to 11V
• Applicable LCD duty : 1/3 to 1/64
• Bias voltage can be supplied externally.
• Applicable commomn driver: MSM5238 (32 outputs)
• Package options:
56-pin plastic QFP (QFP56-P-910-0.65-K) (Product name: MSM5839C GS-K)
56-pin plastic QFP (QFP56-P-910-0.65-L2) (Product name: MSM5839C GS-L2)
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¡ Semiconductor
BLOCK DIAGRAM
MSM5839C
VDD(V1)
V
V
V
EE(V4
DF
LOAD
DI
CP
O1O
2
2
3
O19O20O21O
22
40-Bit 4-Level Driver
O39O
40
V
DD
)
V
EE
40-Bit Level Shifter
V
DD
20-Bit Latch 20-Bit Latch
1
20-Bit Shift
Register
20-Bit Shift
Register
V
SS
V
SS
DO
40
DO20DI
21
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PIN CONFIGURATION (TOP VIEW)
(Top view)
NC
NC
NC
56555453525150494847464544
1
O
1
O
2
2
O
3
3
4
O
4
5
O
5
6
O
6
7
O
7
8
O
8
9
O
9
10
O
10
11
O
11
12
O
12
13
O
13
14
O
14
15161718192021222324252627
15
MSM5839C
)
4
(V
1
LOAD
DI
DF
O18O17O16O
CP
)
20
19
DD
O
O
DD
V
21
O
2
VSSV
V
23
22
O
*(V
20
EE
3
O24O
DI 21DO
V
43
42
DO
40
O
41
40
O
40
39
39
O
38
38
O
37
37
O
36
36
O
35
35
O
34
34
O
33
33
O
32
32
O
31
31
O
30
30
O
29
29
O
28
28
27O26
25
O
O
NC: No connection
56-Pin Plastic QFP (Type K)
12
5
1
123456789
56
NC
NC
55
NC
54
53
DF
52
LOAD
51
DI
1
50
CP
49
V
DD
48
V
SS
47
V
2
46
V
3
DO
45
44
20
43
DI
21
42414039383736353433323130
40
40
VEE(V4)O
DO
6
7
O
O
O4O3O2O
O38O39O
O
36
37
O
8
O
O34O35O
O9O
33
O
10
11
O
1011121314
32
29
30
O31O
O
O14O13O
15
O
15
O
16
16
O
17
17
18
O
18
19
O
19
20
O
20
21
*(VDD)
22
O
21
23
O
22
24
O
23
25
O
24
26
25
27
O
26
28
O
27
29
O28O
NC: No connection
56-Pin Plastic QFP (Type L)
* This pin is internally connected to VDD, so connect it to the power supply or leave it open.
Note : The figure for Type L shows the configuration viewed from the reverse side of the package.
Pay attention to the difference in pin arrangement.
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ABSOLUTE MAXIMUM RATINGS
MSM5839C
Parameter
Supply Voltage (1)
Supply Voltage (2) V
Input Voltage V
Storage Temperature T
*1: VDD>V2>V3>V
Symbol Condition Rating Unit
Ta = 25°C –0.3 to +6 V
Ta = 25°C 0 to 12 V
Ta = 25°C –0.3 to V
— –55 to +150 °C
EE
DD
V
DD
–
1
STG
1
*
V
EE
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (1)
Supply Voltage (2) V
Operating Temperature T
*1: VDD>V2>V3>V
EE
Symbol Condition Range Unit
— 4.5 to 5.5 V
— 4 to 11 V
— –20 to +85 °C
DD
V
DD
1
*
V
–
EE
op
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
"H" Input Voltage V
"L" Input Voltage V
"H" Input Current I
"L" Input Current I
"H" output Voltage V
"L" output Voltage V
ON Resistance R
Supply Current I
Symbol Condition Min. Typ. Max. Unit
IH
IH
IL
OH
OL
*1
*1
IL
VI = V
*1
*1
*2
*2
DD
VI = 0V — — –1 mA
IO = –0.4 mA
IO = 0.4 mA — — 0.4 V
— 0.8V
—V
VDD – VEE = 8V
*4
ON
– VO| = 0.25V
|V
N
Connect all inputs to VDD or V
DD
VDD – VEE = 11V, No load
+0.3 V
DD
(V
= 5V ±10%, Ta = –20 to +85°C)
DD
DD
SS
—VDDV
— 0.2V
DD
—— 1 mA
V
DD
– 0.4
—— V
—510kW
*3
SS
— — 100 mA
V
*1: Applicable to LOAD, CP, DI1, DI21, DF
*2: Applicable to DO20, DO
*3: VN = VDD to V
EE, V2
*4: Applicable to O1 - O
40
7
= (VDD – VEE), V3 = (VDD – VEE)
9
40
2
9
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Switching Characteristics
Parameter
"H", "L" Propagation Delay Time
Clock Frequency f
Clock Pulse Width t
LOAD Pulse Width t
Data Setup Time DI to CP t
CP to LOAD Time t
LOAD to CP Time t
DATA Hold Time DI to CP t
CP Rise/Fall Time
LOAD Rise/Fall Time
MSM5839C
(V
= 5V ±10%, Ta = –20° to +85°C, CL = 15pF)
DD
Symbol Condition Min. Typ. Max. Unit
t
PLH
t
PHL
CP
W(CP)
W(L)
SETUP
CL
LC
HOLD
t
r(CP)
t
f(CP)
t
r(L)
t
f(L)
— — — 250 ns
DUTY = 50%
—
—
—
— — 2 MHz
150 — — ns
150 — — ns
100 — — ns
250 — — ns—
0——ns—
50——ns—
—
—
——50ns
—— 1 ms
CP
, DI
DI
1
21
DO20, DO
LOAD
t
f(CP)
t
w(CP)
0.8V
DD
40
t
SETUP
0.8V
DD
0.8V
0.2V
DD
DD
0.8V
0.2V
0.2V
t
t
DD
DD
PLH
PHL
DD
0.2V
t
w(CP)
t
HOLD
DD
t
r(L)
0.8V
0.2V
DD
DD
t
CL
0.2V
t
w(L)
t
r(CP)
0.8V
DD
DD
t
SETUP
t
0.8
V
0.2
V
f(L)
t
DD
DD
LC
0.2V
0.8V
DD
DD
0.2V
0.8
V
0.2
V
DD
t
HOLD
DD
DD
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¡ Semiconductor
MSM5839C
FUNCTIONAL DESCRIPTION
Pin Functional Description
•DI
1
The data input pin for the 20-bit shift register (from 1st to 20th bit). The display data is input
to the data input pin in synchronization with a clock pulse.
•CP
Clock pulse input pin for the two 20-bit shift registers. The data is shifted in the two 20-bit shift
registers at the falling edge of the clock pulse. Data setup time (t
(t
•DO
) are required between DI1, DI21 and CP.
HOLD
20
The 20th output bit of the shift register.
The data which is input from DI1 is clocked out with a delay of the number of bits of the shift
register (20). A 40-bit shift register can be configured by connecting the output of this pin to DI
pin.
) and data hold time
SETUP
21
•DI
21
The data input pin for the 20-bit shift register (from 21st to 40th bit).
Connecting the DO20 pin and this pin allows the device to be used as a 40-bit shift register.
•DO
40
The 40th output bit of the shift register.
The data which is input from DI1 is clocked out with a delay of the number of the bits of the
shift register.
When increasing the number of characters, this pin is used to cascade connect the next
MSM5839C.
•DF
Alternate signal input pin for LCD driving waveform.
•VDD(V1), V
SS
Supply voltage pins. VDD should be 4.5 to 5.5V.
VSS is a ground pin (VSS = 0V).
•V2, V3, VEE(V4)
Bias supply voltage pins to drive the LCD. Bias voltage is supplied from an external source.
• LOAD
The signal for latching the shift register contents is input from this pin.
When LOAD pin is set at "H", the shift register contents are transferred to the 40-bit 4-level
driver. When LOAD pin is set at "L", the last display output data (O1 to O40), which was
transferred when LOAD pin was at "H", is held.
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MSM5839C
•O1 to O
40
Display data output pins which correspond to each data bit in the latch.
One of VDD, V2, V3 or VEE (V4) is selected as a display driving voltage source based on the
combination of latched data level and DF signal. Refer to the Truth Table below.
These pins should be connected to the SEGMENT side of the LCD panel.
Truth Table
Latched data DF LCD driver output
H
HV
LV
HV
L
LV
(V4)
EE
(V1)
DD
3
2
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PACKAGE DIMENSIONS
QFP56-P-910-0.65-K
Mirror finish
MSM5839C
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.36 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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QFP56-P-910-0.65-L2
Spherical surface
MSM5839C
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.36 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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