Page 1
Cascadable Silicon Bipolar
MMIC␣ Amplifier
Technical Data
MSA-0900
Features
• Broadband, Minimum Ripple
Cascadable 50 Ω Gain Block
• 8.0 ± 0.2 dB Typical Gain
Flatness from 0.1 to 4.0 GHz
• 3 dB Bandwidth:
0.1 to 6.0␣ GHz
• Low VSWR:
≤ 1.5:1 from 0.1 to 4.0␣ GHz
• 11.5 dBm Typical P
1dB
at
1.0␣ GHz
Description
The MSA-0900 is a high performance silicon bipolar Monolithic
Microwave Integrated Circuit
(MMIC) chip. This MMIC is
designed for very wide bandwidth
industrial and military applications that require flat gain and low
VSWR.
The MSA-series is fabricated using
HP’s 10 GHz fT, 25␣ GHz f
MAX
,
silicon bipolar MMIC process
which uses nitride self-alignment,
ion implantation, and gold metallization to achieve excellent
performance, uniformity and
reliability. The use of an external
bias resistor for temperature and
current stability also allows bias
flexibility.
The recommended assembly
procedure is gold-eutectic die
attach at 400°C and either wedge
or ball bonding using 0.7 mil gold
wire.
This chip is intended to be used
with an external blocking capacitor completing the shunt feedback
path (closed loop). Data sheet
characterization is given for a
45␣ pF capacitor. Low frequency
performance can be extended by
using a larger valued capacitor.
[1]
Chip Outline
Note:
1. Refer to the APPLICATIONS section
“Silicon MMIC Chip Use” for additional
information.
[1]
AK
Typical Biasing Configuration
R
(Required)
RFC (Optional)
= 7.8 V
d
C
bias
block
C
Fbl
C
block
IN OUT
4
3
MSA
1
V
2
5965-9548E
V
CC
> 12 V
6-430
Page 2
MSA-0900 Absolute Maximum Ratings
Parameter Absolute Maximum
Device Current 80 mA
(TMS)
[2,3]
= 25°C.
Mounting␣ Surface
> 148° C.
than do alternate methods.
jc
750 mW
Power Dissipation
RF Input Power +13 dBm
Junction Temperature 200°C
Storage Temperature –65 to 200° C
Notes:
1. Permanent damage may occur if any of these limits are exceeded.
2. T
Mounting Surface
3. Derate at 14 mW/° C for T
4. The small spot size of this technique results in a higher, though more
accurate determination of θ
[1]
Thermal Resistance
θjc = 70°C/W
[2,4]
:
Electrical Specifications
Symbol Parameters and Test Conditions
G
∆G
f
3 dB
P
Power Gain (|S21|2) f = 0.1 GHz dB 8.0
P
Gain Flatness
3 dB Bandwidth
[3]
[3,4]
[1]
, T
A
= 25° C
[2]
: Id = 35 mA, Z
= 50 Ω Units Min. Typ. Max.
O
f = 0.1 to 4.0 GHz dB ±0.2
GHz 6.0
Input VSWR f = 1.0 to 4.0 GHz 1.4:1
VSWR
Output VSWR f = 1.0 to 4.0 GHz 1.5:1
NF 50 Ω Noise Figure f = 1.0 GHz dB 6.0
f = 4.0 GHz 6.5
P
1 dB
Output Power at 1 dB Gain Compression f = 1.0 GHz dBm 11.5
f = 4.0 GHz 6.5
IP
t
V
3
D
d
Third Order Intercept Point f = 1.0 GHz dBm 23.0
Group Delay f = 1.0 GHz psec 60
Device Voltage V 7.0 7.8 8.6
dV/dT Device Voltage Temperature Coefficient mV/°C –16.0
Notes:
1. The recommended operating current range for this device is 25 to 45 mA. Typical performance as a function of current
is on the following page.
RF performance of the chip is determined by packaging and testing 10 devices per wafer.
2.
3. The value is the expected achievable performance for the MSA-0900 used with an external 45 pF capacitor mounted in a
100 mil stripline package.
4. Referenced from 0.1 GHz gain (GP).
Part Number Ordering Information
Part Number Devices Per Tray
MSA-0900-GP4 100
6-431
Page 3
MSA-0900 Typical Scattering Parameters
S
Freq.
GHz Mag Ang dB Mag Ang dB Mag Ang Mag Ang k
11
S
21
[1,2]
(Z
= 50 Ω, TA = 25° C, I
O
S
12
d
S
= 35 mA)
22
0.02 .32 –107 10.8 3.48 151 –13.9 .203 17 .32 –106 0.83
0.05 .22 –143 8.6 2.70 164 –13.6 .209 6 .22 –142 1.09
0.1 .11 –144 8.2 2.57 171 –13.3 .215 3 .11 –142 1.16
0.2 .10 –160 8.1 2.54 172 –13.5 .211 1 .10 –158 1.19
0.4 .10 –171 8.1 2.54 175 –13.4 .215 2 .10 –166 1.18
0.6 .09 –170 8.1 2.55 166 –13.3 .216 1 .10 –166 1.18
0.8 .08 –171 8.2 2.57 162 –13.3 .216 1 .11 –166 1.17
1.0 .08 –170 8.3 2.59 158 –13.1 .220 1 .11 –167 1.15
1.5 .07 –166 8.6 2.68 147 –13.1 .221 1 .14 –172 1.12
2.0 .07 –138 8.9 2.80 136 –12.6 .234 1 .15 –172 1.07
2.5 .08 –131 9.3 2.92 126 –12.6 .236 1 .18 179 1.04
3.0 .12 –119 9.6 3.01 112 –12.0 .250 1 .21 171 0.99
3.5 .17 –125 9.6 3.02 95 –11.8 .256 –1 .22 157 0.97
4.0 .22 –132 9.1 2.86 78 –11.5 .265 –3 .19 144 0.96
4.5 .27 –140 8.4 2.64 63 –11.5 .265 –5 .16 138 0.97
5.0 .32 –149 7.5 2.36 50 –11.4 .268 –6 .12 138 1.00
5.5 .34 –154 6.4 2.09 38 –11.3 .272 –6 .10 162 1.02
6.0 .36 –158 5.3 1.84 29 –11.3 .272 –6 .10 –166 1.07
6.5 .38 –158 4.2 1.62 22 –11.4 .271 –6 .16 –151 1.12
7.0 .39 –157 3.2 1.45 15 –11.5 .267 –6 .23 –147 1.17
Notes:
1. S-parameters are de-embedded from 100 mil BeO package measured data using the package model found in the
DEVICE MODELS section.
2. S-parameter data assumes an external 45 pF capacitor. Low fequency performance can be extended using a larger
valued capacitor.
6-432
Page 4
Typical Performance, T
(unless otherwise noted)
18
15
12
(dB)
9
p
G
6
3
0
Figure 1. Typical Power Gain vs.
Frequency, Id = 35 mA.
15
12
(dBm)
9
1 dB
P
6
0.1 0.2 0.3 0.5 2.01.0 4.0
Figure 4. Output Power at 1 dB Gain
Compression and Noise Figure vs.
Frequency.
Open Loop
Closed Loop
0.1.02 0.3 0.5 1.0 3.0 6.0
FREQUENCY (GHz)
= 45 mA
I
d
Id = 35 mA
Id = 25 mA
FREQUENCY (GHz)
= 25° C
A
7.0
6.5
6.0
NF (dB)
5.5
9
d
(mA)
0.1 GHz
1.0 GHz,
1.0 GHz,
4.0 GHz
4.0 GHz
6.0 GHz
(dB)
p
G
8
7
6
5
4
2010 30 40 50
I
Figure 2. Power Gain vs. Current.
13
12
(dBm)NF (dB)
1 dB
11
P
7
6
5
4
–25–55 +25 +85 +125
TEMPERATURE (°C)
P
1 dB
8
G
P
7
NF
Figure 3. Output Power at 1 dB Gain
Compression, Noise Figure and Power
Gain vs. Case Temperature,
f = 1.0 GHz, I
= 35 mA.
d
Gp (dB)
MSA-0900 Bonding Diagram
Capacitor
(45 pF typ)
4
MSA
Die
Input Trace
Numbers refer to pin contacts listed on the Chip Outline.
A09
2
2
1
5
MSA-0900 Chip Dimensions
Ground
Output
Trace
(backside
contact)
3
(4) BONDPAD
FOR FEEDBACK
CAPACITOR
Ground
6-433
(3) OUTPUT
(BACKSIDE CONTACT)
(1) INPUT
Unless otherwise specified, tolerances are
±13 µm/±0.5 mils. Chip thickness is 114 µm/4.5 mil.
Bond Pads are 41 µm/1.6 mil typical on each side.
Note 1: Output contact is made by die attaching the
backside of the die.
450 µm
17.7 mil
(2)
GROUND
AK
335 µm
13.2 mil
OPTIONAL
TOPSIDE
(5)
OUTPUT
[1]
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