Datasheet MP7528 Datasheet (EXAR)

MP7528

CMOS

Dual Buffered Multiplying 8-Bit

Digital-to-Analog Converter

FEATURES

• On-Chip Latches for Both DACs

• +5 V to +15 V Operation

• DACs Matched to 1%

• Four Quadrant Multiplication

• 15 V CMOS Compatible

• See MP7529A or MP7529B for Improved Performance

GENERAL DESCRIPTION

The MP7528 is a dual 8-bit digital/analog converter designed
using EXAR’s proven decoded DAC architecture. It features ex­cellent DAC-to-DAC matching and guaranteed monotonicity .

Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.

Data is transferred into either of the two DAC data latches via
a common 8-bit TTL/CMOS compatible input port. Control input

APPLICATIONS

• Microprocessor Controlled Gain Circuits

• Microprocessor Controlled Attenuator Circuits

• Microprocessor Controlled Function Generation

• Precision AGC Circuits

• Bus Structured Instruments

/DACB determines which DAC is to be loaded. The

DACA
MP7528’s load cycle is similar to the write cycle of a random ac­cess memory and the device is bus compatible with most 8-bit
microprocessors.

The device operates from a +5V to +15V power supply with

only 2 mA of current (maximum).

Both DACs offer excellent four quadrant multiplication char­acteristics with a separate reference input and feedback resistor
for each DAC.

SIMPLIFIED BLOCK AND TIMING DIAGRAM

DB7-DB0

DACA/DACB

CS

WR

V

DD

DGND

D

LATCH A

E

D

LATCH B

E

V

REFA

Q

DAC A

Q

DAC B

V

REFB

R

FBA

I

OUTA

R

FBB

I

OUTB

AGND

DB7-DB0

DACA/DACB

CS

WR

OUT

Rev. 2.00

1

MP7528

ORDERING INFORMATION

Package

Type

Plastic Dip MP7528JN
Plastic Dip MP7528KN

Plastic Dip MP7528LN

SOIC MP7528JS
SOIC MP7528KS

SOIC MP7528LS
PLCC MP7528JP
PLCC MP7528KP
PLCC MP7528LP

Ceramic Dip MP7528AD
Ceramic Dip MP7528BD
Ceramic Dip MP7528CD
Ceramic Dip MP7528SD*
Ceramic Dip MP7528TD*

*Contact factory for non-compliant military processing

PIN CONFIGURATIONS

Temperature

Range

–40 to +85
–40 to +85

–40 to +85
–40 to +85°C

–40 to +85
–40 to +85°C
–40 to +85
–40 to +85°C
–40 to +85°C
–40 to +85
–40 to +85
–40 to +85°C

–55 to +125
–55 to +125°C

°C
°C

°C

°C

°C

°C
°C

°C

Part No.

INL

(LSB)

1

+

1/2

+
+

1/4

1

+

1/2

+
+

1/4

+

1
+1/2
+1/4

+

1

1/2

+
+1/4

+

1
+

1/2

See Packaging Section for Package Dimensions

DNL

(LSB)

+

1
1

+

1

+

1

+

1

+
+

1
1

+
+

1
+1
+1

1

+

1

+
+

1
+

1

Gain Error

(LSB)

+

6
4

+
+

3

+

6
4

+
+

3
+6
+4

3

+
+6

4

+

3

+

6

+
+

4

Rev. 2.00

AGND

I

V

DGND

DACA/DACB

(MSB) DB7

OUTA

R

FBA

REFA

DB6
DB5
DB4

1
2
3
4
5
6
7
8
9

10

20 Pin CDIP, PDIP (0.300”)

D20, N20

20
19
18
17
16
15
14
13
12
11

I

OUTB

R

FBB

V

REFB

V

DD

WR
CS

DB0 (LSB)
DB1
DB2
DB3

201
2
3
4
5
6
7
8
9

Pin Out

See

at Left

19

18

17

16

15

14

13

12

1110

20 Pin SOIC (Jedec, 0.300”)

S20

2

PIN CONFIGURATIONS (CONT’D)

MP7528

PIN OUT DEFINITIONS

AGND

DB3

I

OUTB

DB2

R

FBB

DB1

V

REFA

DGND

DACA/DACB

(MSB) DB7

DB6

I

OUTA

R

FBA

3 2 1 20 19

4

5

6

7

8

9 10111213

DB5

DB4

20 Pin PLCC

P20

PIN NO. NAME DESCRIPTION

1 AGND Analog Ground
2I
3R
4V

OUTA

FBA

REFA

5 DGND Digital Ground
6 DAC A

/ DAC Select

DAC B
7 DB7 (MSB) Data Input Bit 7
8 DB6 Data Input Bit 6
9 DB5 Data Input Bit 5
10 DB4 Data Input Bit 4
11 DB3 Data Input Bit 3
12 DB2 Data Input Bit 2
13 DB1 Data Input Bit 1
14 DB0 (LSB) Data Input Bit 0
15 CS
16 WR
17 V
18 V
19 R
20 I

DD
REFB
FBB

OUTB

Current Out DAC A
Feedback Resistor for DAC A
Reference Input for DAC A

Chip Select
Write
Power Supply
Reference Input for DAC B
Feedback Resistor for DAC B
Current Out DAC B

V

18

REFB

17

V

DD

16

WR
CS

15

14

DB0
(LSB)

Rev. 2.00

3

MP7528

ELECTRICAL CHARACTERISTICS

DD = + 5 V, VREF = +10 V unless otherwise noted)

(V

25°C

Tmin to Tmax

Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments

STATIC PERFORMANCE

1

Resolution (All Grades) N 8 8 Bits
Integral Non-Linearity INL LSB End Point Linearity Spec.

(Relative Accuracy)

J, A, S +

1+1
K, B, T +1/2 +1/2
L, C +

1/4 +1/4
Monotonicity Guaranteed over temp
Differential Non-Linearity DNL +

1+1 LSB All grades monotonic over full
J, A, S temperature range.
K, B, T
L, C

Gain Error GE LSB Using Internal R

J, A, S +4+6 Digital Inputs = V

FB

INH

K, B, T +2+4
L, C +

Gain Temperature Coefficient

2

TC

GE

Power Supply Rejection Ratio PSRR +

Output Leakage Current (Pin 2) I
Output Leakage Current (Pin 20) I
Input Resistance V

V

OUT1

OUT2

REFA
REFB

8 15 8 15 kΩ TC = –300 ppm/°C max.
8 15 8 15 kΩ 11 kΩ typical

1+3

+70 ppm/°C ∆Gain/∆Temperature

200 +400 ppm/% |∆Gain/∆VDD| ∆VDD = + 5%

Digital Inputs = V
+50nA +400nA nA Digital Inputs = V
+50nA +400nA nA Digital Inputs = V

INH

INL

INH

Input Resistance Matching +1+1%

DYNAMIC PERFORMANCE

2

RL=100Ω, CL=13pF

Harmonic Distortion THD –85 dB V

IN

= 6V

RMS

@ 1 KHz

Digital Crosstalk Q 30 nVs Measured for code transition

to F

Z

S

SS

Channel-to-Channel Isolation CCI –77 dB
AC Feedthrough at I

OUT1

F

T

Glitch Energy Egl 160 nVs Z
Propagation Delay t

PD

–70 –65 dB V

= 10kHz, 20 Vp-p, sinewave

REF

to FS Input Change

S

220 270 ns From digital input to 90%

of final analog output current

Rev. 2.00

4

ELECTRICAL CHARACTERISTICS (CONT’D)

MP7528

25°C

Tmin to Tmax

Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments

DIGITAL INPUTS

Logical “1” Voltage V
Logical “0” Voltage V
Input Leakage Current I
Input Capacitance

Data C
Control C

ANALOG OUTPUTS

3

2.4 2.4 V

IH

IL

2

2

LKG

IN
IN

0.8 0.8 V
+1+10 µA

10 10 pF
15 15 pF

Output Capacitance

C

OUTA

C

OUTA

C

OUTB

C

OUTB

POWER SUPPLY

Functional Voltage Range

5

2

Supply Current I

V

DD
DD

4.5 15.75 4.5 15.75 V

120 120 pF DAC Inputs all 1’s

50 50 pF DAC Inputs all 0’s

120 120 pF DAC Inputs all 1’s

50 50 pF DAC Inputs all 0’s

2 2 mA All digital inputs = 0 V or all = 5 V
2 2 mA All digital inputs = V

or all = V

IL

SWITCHING
CHARACTERISTICS

Chip Select to Write Set-Up Time t
Chip Select to Write Hold Time t
DAC Select to Write Set-Up Time t
DAC Select to Write Hold Time t
Data Valid to W rite Set-Up Time t
Data Valid to W rite Hold Time t
Write Pulse Width t

4

200 230 ns

CS
CH

AS
AH
DS
DH

WR

20 30 ns

200 230 ns

20 30

110 130 ns

00ns

180 200 ns

IH

NOTES:

1

Full Scale Range (FSR) is 10V for unipolar mode.

2

Guaranteed but not production tested.

3

Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.

4

See timing diagram.

5

Specified values guarantee functionality. Refer to other parameters for accuracy.

Specifications are subject to change without notice

Rev. 2.00

5

MP7528

ELECTRICAL CHARACTERISTICS

(VDD = + 15 V, V

= +10 V unless otherwise noted)

REF

25°C

Tmin to Tmax

Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments

STATIC PERFORMANCE

1

Resolution (All Grades) N 8 8 Bits
Integral Non-Linearity INL LSB End Point Linearity Spec.

(Relative Accuracy)

J, A, S +

1+1
K, B, T +1/2 +1/2
L, C +

1/4 +1/4
Monotonicity Guaranteed over temp
Differential Non-Linearity DNL LSB All grades monotonic over full

J, A, S +
K, B, T +
L, C +

Gain Error GE LSB Using Internal R

J, A, S +4+5 Digital Inputs = V

1+1 temperature range.
1+1
1+1

FB

INH

K, B, T +2+3
L, C +

Gain Temperature Coefficient

2

TC

GE

Power Supply Rejection Ratio PSRR +

Output Leakage Current (Pin 2) I
Output Leakage Current (Pin 20) I
Input Resistance V

V

OUT1

OUT2

REFA
REFB

8 15 8 15 kΩ TC = –300 ppm/°C max.
8 15 8 15 kΩ 11 kΩ typical

1+1

+35 ppm/°C ∆Gain/∆Temperature

100 +200 ppm/% |∆Gain/∆VDD| ∆VDD = + 5%

Digital Inputs = V
+50nA +200nA nA Digital Inputs = V
+50nA +200nA nA Digital Inputs = V

INH

INL

INH

Input Resistance Matching +1+1%

DYNAMIC PERFORMANCE

2

RL=100Ω, CL=13pF

Harmonic Distortion THD –85 dB V

IN

= 6V

RMS

@ 1 KHz

Digital Crosstalk Q 60 nVs Measured for code transition

ZS to F

S

Channel-to-Channel Isolation CCI –77 dB
AC Feedthrough at I

OUT1

F

T

Glitch Energy Egl 440 nVs ZS to F
Propagation Delay t

PD

–70 –65 dB V

80 100 ns From 50% of digital input to 90%

= 10kHz, 20 Vp-p, sinewave

REF

Input Change

S

of final analog output current

DIGITAL INPUTS

Logical “1” Voltage V
Logical “0” Voltage V
Input Leakage Current I
Input Capacitance

Data C
Control C

3

13.5 13.5 V

IH

IL

2

ILKG

IN
IN

1.5 1.5 V
+1+10 µA

10 10 pF
15 15 pF

Rev. 2.00

6

ELECTRICAL CHARACTERISTICS (CONT’D)

MP7528

25°C

Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments

ANALOG OUTPUTS

Output Capacitance

POWER SUPPLY

Functional Voltage Range
Supply Current I

SWITCHING
CHARACTERISTICS

Chip Select to Write Set-Up Time t
Chip Select to Write Hold Time t
DAC Select to Write Set-Up Time t
DAC Select to Write Hold Time t
Data Valid to W rite Set-Up Time t
Data Valid to W rite Hold Time t
Write Pulse Width t

NOTES:

1

Full Scale Range (FSR) is 10V for unipolar mode.

2

Guaranteed but not production tested.

3

Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.

4

See timing diagram.

5

Specified values guarantee functionality. Refer to other parameters for accuracy.

2

C

OUTA

C

OUTA

C

OUTB

C

OUTB

5

2

V

DD
DD

CS
CH

AH
DS
DH

WR

4.5 15.75 4.5 15.75 V

60 80 ns
10 15 ns

AS

60 80 ns
10 15 ns
30 40 ns

00ns

60 80 ns

120 120 pF DAC Inputs all 1’s

120 120 pF DAC Inputs all 1’s

Tmin to Tmax

50 50 pF DAC Inputs all 0’s

50 50 pF DAC Inputs all 0’s

2 2 mA All digital inputs = 0 V or all = 5 V
2 2 mA All digital inputs = V

or all = V

IL

IH

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)

VDD to GND +17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND +
(Functionality Guaranteed +

0.5 V)

1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital Input Voltage to DGND –0.5 V, +17 V. . . . . . . . . . . . .

, V

V

PIN2

V

REFA

NOTES:

1

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

to GND –0.5 V, +17 V. . . . . . . . . . . . . . . . . . . .

PIN20

, V

to GND +25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REFB

, V

V

RFBA

RFBB

Storage Temperature –65
Lead Temperature (Soldering, 10 secs.) +300
Package Power Dissipation Rating to 75

CDIP, PDIP, SOIC, PLCC 900mW. . . . . . . . . . . . . . . . . .

Derates above 75

1, 2, 3

to GND +25 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

°C to +150°C. . . . . . . . . . . . . . . . .

°C

°C 12mW/°C. . . . . . . . . . . . . . . . . . . . .

stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

2

Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.

3

GND refers to AGND and DGND.

Rev. 2.00

7

°C. . . . . . . . .

MP7528

INTERFACE LOGIC INFORMATION

DAC Selection: Both DAC latches share a common 8-bit in­put port. The control input DACA
accept data from the input port.

Mode Selection: Inputs CS
mode of the selected DAC. See Mode Selection Table below:

/DACB selects which DAC can

and WR control the operating

DAC A/DAC B DAC B

L
H
X
X

CS WR DAC A

L
L
H
X

L = LOW state, H = HIGH state, X = Don’t care state

Table 1. Mode Selection Table

Write Mode: When CS

and WR are both low the selected
DAC is in the write mode. The input data latches of the selected
DAC are transparent and its analog output responds to activity
on DB0-DB7.

Hold Mode: The selected DAC latch retains the data which

was present on DB0-DB7 just prior to CS

and WR assuming a
high state. Both analog outputs remain at the values corre­sponding to the data in their respective latches.

L
L
X
H

Write
Hold
Hold
Hold

Hold
Write
Hold
Hold

CS

DAC A/DAC B

WR

DATA IN

(DB0-DB7)

t

t

CS

t

AS

t

WR

t

DS

V

IH

V

IL

NOTES:

1. All input signal rise and fall times measured from 10% to 90% of V
V

= +5 V, tr = tf = 20 ns

DD

V

= +15 V, tr = tf = 40 ns

DD

2. Timing measurement reference level is V

V

IH

DATA IN

V

STABLE

IL

+ VIL / 2

IH

CH

t

AH

t

DH

Figure 1. Write Cycle Timing Diagram

DD

V

DD

0

V

DD

0

V

DD

0

V

DD

0

.

Rev. 2.00

8

MICROPROCESSOR INTERFACE

MP7528

A0-A15

Address

V

MA

Decode

Logic

CPU
6800

φ2

D0–D7

Analog circuitry has been omitted for clarity
*A = Decoded 7528 DAC A Address
**A + 1 = Decoded 7528 DAC B Address

Address Bus

A*

A+1**

Data Bus

Figure 2. MP7528 Dual DAC to 6800

CPU Interface

DACA

CS

WR

DB0
DB7

/DACB

DAC A

MP7528

DAC B

A8-A15

CPU

Address

Decode

Logic

Address Bus

A*

8085

A+1**

WR

ALE

AD0–AD7

NOTE:

8085 instruction SHLD (store H & L direct) can update
both DACS with data from H and L registers

Latch

8212

ADDR/Data Bus

Analog circuitry has been omitted for clarity
*A = Decoded 7528 DAC A Address
**A + 1 = Decoded 7528 DAC B Address

Figure 3. MP7528 Dual DAC to 8085

CPU Interface

DACA/DACB

DAC A

CS

MP7528

WR

DAC B

DB0
DB7

PERFORMANCE CHARACTERISTICS

Graph 1. Relative Accuracy vs. Digital Code

5 V

Graph 2. Relative Accuracy vs. Digital Code

15 V

Rev. 2.00

9

MP7528

This page left blank

Rev. 2.00

10

20 LEAD CERAMIC DUAL-IN-LINE

(300 MIL CDIP)

D20

MP7528

S

1

See
Note 1

Base

Plane

Seating

Plane

SYMBOL MIN MAX MIN MAX NOTES

A –– 0.200 –– 5.08 ––
b 0.014 0.023 0.356 0.584 ––
b

1

c 0.008 0.015 0.203 0.381 ––
D –– 1.060 –– 26.92 4
E 0.220 0.310 5.59 7.87 4
E

1

e 0.100 BSC 2.54 BSC 5
L 0.125 0.200 3.18 5.08 ––
L

1

Q 0.015 0.070 0.381 1.78 3
S –– 0.080 –– 2.03 6
S

1

0.038 0.065 0.965 1.65 2

0.290 0.320 7.37 8.13 7

0.150 –– 3.81 –– ––

0.005 –– 0.13 –– 6

L

INCHES MILLIMETERS

20

110

D

Q

be

S

11

b

1

α 0° 15° 0° 15° ––

E

1

E

A

L

1

NOTES

1. Index area; a notch or a lead one identification mark
is located adjacent to lead one and is within the
shaded area shown.

2. The minimum limit for dimension b
(0.58 mm) for all four corner leads only.

3. Dimension Q shall be measured from the seating
plane to the base plane.

4. This dimension allows for off-center lid, meniscus and
glass overrun.

5. The basic lead spacing is 0.100 inch (2.54 mm) be­tween centerlines.

6. Applies to all four corners.

7. This is measured to outside of lead, not center.

α

c

may be 0.023

1

Rev. 2.00

11

MP7528

20 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP)

N20

S

Seating

Plane

20

1

Q

1

A
L

B

SYMBOL MIN MAX MIN MAX

A –– 0.200 –– 5.08
A

1

B 0.014 0.023 0.356 0.584
B

(1) 0.038 0.065 0.965 1.65

1

C 0.008 0.015 0.203 0.381
D 0.945 1.060 24.0 26.92
E 0.295 0.325 7.49 8.26
E

1

e 0.100 BSC 2.54 BSC
L 0.115 0.150 2.92 3.81

0.015 –– 0.38 ––

0.220 0.310 5.59 7.87

D

eB

INCHES

α 0° 15° 0° 15°

Q

1

S 0.040 0.080 1.02 2.03

0.055 0.070 1.40 1.78

11

E

10

MILLIMETERS

1

A

1

1

E

C

α

Rev. 2.00

Note: (1) The minimum limit for dimensions B1 may be 0.023”

(0.58 mm) for all four corner leads only.

12

20 LEAD SMALL OUTLINE

(300 MIL JEDEC SOIC)

D

20 11

MP7528

S20

E H

10

h x 45°

Seating
Plane

C

A

α

e

SYMBOL MIN MAX MIN MAX

A 0.097 0.104 2.464 2.642
A
B 0.014 0.019 0.356 0.483
C 0.0091 0.0125 0.231 0.318
D 0.500 0.510 12.70 12.95
E 0.292 0.299 7.42 7.59
e 0.050 BSC 1.27 BSC
H 0.400 0.410 10.16 10.41
h 0.010 0.016 0.254 0.406
L 0.016 0.035 0.406 0.889

B

A

1

L

INCHES MILLIMETERS

1

0.0050 0.0115 0.127 0.292

α 0° 8° 0° 8°

Rev. 2.00

13

MP7528

Notes

Rev. 2.00

14

Notes

MP7528

Rev. 2.00

15

MP7528

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im­prove design, performance or reliability . EXAR Corporation assumes no responsibility for the use of any circuits de­scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum­stances.

Copyright EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Rev. 2.00

16