Datasheet MMBT6427LT1 Datasheet (Motorola)

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1
Motorola Small–Signal Transistors, FETs and Diodes Device Data
 
NPN Silicon
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector–Emitter Voltage V
40 Vdc
Collector–Base Voltage V
40 Vdc
Emitter–Base Voltage V
EBO
12 Vdc
Collector Current — Continuous I
C
500 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board
(1)
TA = 25°C Derate above 25°C
P
D
225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient
R
q
JA
556 °C/W
Total Device Dissipation
Alumina Substrate,
(2)
TA = 25°C
Derate above 25°C
P
D
300
2.4
mW
mW/°C
Thermal Resistance, Junction to Ambient
R
q
JA
417 °C/W
Junction and Storage Temperature TJ, T
stg
–55 to +150 °C
DEVICE MARKING
MMBT6427LT1 = 1V
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise noted)
Characteristic
Symbol Min Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
(IC = 10 mAdc, VBE = 0)
V
(BR)CEO
40
Vdc
Collector–Base Breakdown Voltage
(IC = 100 mAdc, IE = 0)
V
(BR)CBO
40
Vdc
Emitter–Base Breakdown Voltage
(IC = 10 mAdc, IC = 0)
V
(BR)EBO
12
Vdc
Collector Cutoff Current
(VCE = 25 Vdc, IB = 0)
I
CES
1.0
µAdc
Collector Cutoff Current
(VCB = 30 Vdc, IE = 0)
I
50
nAdc
Emitter Cutoff Current
(VEB = 10 Vdc, IC = 0)
I
EBO
50
nAdc
1. FR–5 = 1.0 0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MMBT6427LT1/D

SEMICONDUCTOR TECHNICAL DATA

Motorola Preferred Device
1
2
3
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
Motorola, Inc. 1996
COLLECTOR 3
BASE
1
EMITTER 2
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MMBT6427LT1
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Motorola Small–Signal Transistors, FETs and Diodes Device Data
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise noted) (Continued)
Characteristic
Symbol Min Max Unit
ON CHARACTERISTICS
DC Current Gain
(IC = 10 mAdc, VCE = 5.0 Vdc) (IC = 100 mAdc, VCE = 5.0 Vdc) (IC = 500 mAdc, VCE = 5.0 Vdc)
h
FE
10,000 20,000 14,000
100,000 200,000 140,000
Collector–Emitter Saturation Voltage
(IC = 50 mAdc, IB = 0.5 mAdc) (IC = 500 mAdc, IB = 0.5 mAdc)
V
CE(sat)
(3)
— —
1.2
1.5
Vdc
Base–Emitter Saturation Voltage
(IC = 500 mAdc, IB = 0.5 mAdc)
V
BE(sat)
2.0
Vdc
Base–Emitter On Voltage
(IC = 50 mAdc, VCE = 5.0 Vdc)
V
BE(on)
1.75
Vdc
SMALL–SIGNAL CHARACTERISTICS
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz)
C
obo
7.0
pF
Input Capacitance
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz)
C
ibo
15
pF
CurrentGain — High Frequency
(IC = 10 mAdc, VCE = 5.0 Vdc, f = 100 MHz)
|hfe|
1.3
Vdc
Noise Figure
(IC = 1.0 mAdc, VCE = 5.0 Vdc, RS = 100 k, f = 1.0 kHz)
NF
10
dB
3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2.0%.
R
S
i
n
e
n
IDEAL
TRANSISTOR
Figure 1. Transistor Noise Model
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Motorola Small–Signal Transistors, FETs and Diodes Device Data
NOISE CHARACTERISTICS
(VCE = 5.0 Vdc, TA = 25°C)
Figure 2. Noise Voltage
f, FREQUENCY (Hz)
50
100
200
500
20
Figure 3. Noise Current
f, FREQUENCY (Hz)
Figure 4. Total Wideband Noise Voltage
RS, SOURCE RESISTANCE (kΩ)
Figure 5. Wideband Noise Figure
RS, SOURCE RESISTANCE (kΩ)
5.0
50
70
100
200
30
10
20
1.0
101020 50 100 200 500 1 k 2 k 5 k 10 k 20 k 50 k 100 k
2.0
1.0
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
BANDWIDTH = 1.0 Hz RS
0
IC = 1.0 mA
100 µA
10 µA
BANDWIDTH = 1.0 Hz
IC = 1.0 mA
100 µA
10 µA
e
n
, NOISE VOLTAGE (nV)
i
n
, NOISE CURRENT (pA)
2.0 5.0 10 20 50 100 200 500 100 0
BANDWIDTH = 10 Hz TO 15.7 kHz
IC = 10 µA
100 µA
1.0 mA
8.0
10
12
14
6.0
0
4.0
1.0 2.0 5.0 10 20 50 100 200 500 100 0
2.0
BANDWIDTH = 10 Hz TO 15.7 kHz
10 µA
100 µA
IC = 1.0 mA
V
T
, TOTAL WIDEBAND NOISE VOLTAGE (nV)
NF, NOISE FIGURE (dB)
10 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 50 k 100 k
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Motorola Small–Signal Transistors, FETs and Diodes Device Data
SMALL–SIGNAL CHARACTERISTICS
Figure 6. Capacitance
VR, REVERSE VOLTAGE (VOLTS)
5.0
7.0
10
20
3.0
Figure 7. High Frequency Current Gain
IC, COLLECTOR CURRENT (mA)
Figure 8. DC Current Gain
IC, COLLECTOR CURRENT (mA)
Figure 9. Collector Saturation Region
IB, BASE CURRENT (µA)
2.0
200 k
5.0
0.04
4.0
2.0
1.0
0.8
0.6
0.4
0.2
TJ = 25°C
C, CAPACITANCE (pF)
1.5
2.0
2.5
3.0
1.0
0.5
|h
fe
|, SMALL–SIGNAL CURRENT GAIN
h
FE
, DC CURRENT GAIN
V
CE
, COLLECTOR–EMITTER VOLTAGE (VOLTS)
0.1 0.2 0.4 1.0 2.0 4.0 10 20 40
C
ibo
C
obo
0.5 1.0 2.0 0.5 10 20 50 100 200 500
VCE = 5.0 V f = 100 MHz TJ = 25
°
C
100 k
70 k 50 k
30 k 20 k
10 k
7.0 k
5.0 k
3.0 k
2.0 k
7.0 10 20 30 50 70 100 200 300
500
TJ = 125°C
25°C
–55°C
VCE = 5.0 V
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000
TJ = 25°C
IC =
10 mA
50 mA 250 mA 500 mA
Figure 10. “On” Voltages
IC, COLLECTOR CURRENT (mA)
Figure 11. Temperature Coefficients
IC, COLLECTOR CURRENT (mA)
1.6
5.0
–1.0
V, VOLTAGE (VOLTS)
1.4
1.2
1.0
0.8
0.6
7.0 10 20 30 50 70 100 200 300 500
V
BE(sat)
@ IC/IB = 1000
R
V
, TEMPERATURE COEFFICIENTS (mV/ C)
°
θ
TJ = 25°C
V
BE(on)
@ VCE = 5.0 V
V
CE(sat)
@ IC/IB = 1000
–2.0
–3.0
–4.0
–5.0
–6.0
5.0 7.0 10 20 30 50 70 100 200 300 500
25°C TO 125°C
–55°C TO 25°C
*R
q
VC
FOR V
CE(sat)
q
VB
FOR V
BE
25°C TO 125°C
–55°C TO 25°C
*APPLIES FOR IC/IB ≤ hFE/3.0
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MMBT6427LT1
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Motorola Small–Signal Transistors, FETs and Diodes Device Data
Figure 12. Thermal Response
t, TIME (ms)
1.0
r(t), TRANSIENT THERMAL
2.0 5.01.00.50.20.1
RESISTANCE (NORMALIZED)
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01 20 5010 200 500100 1.0 k 2.0 k 5.0 k 10 k
D = 0.5
0.2
0.1
0.05
SINGLE PULSE
SINGLE PULSE
Z
θ
JC(t)
= r(t)
R
θ
JCTJ(pk)
– TC = P
(pk) Zθ
JC(t)
Z
θ
JA(t)
= r(t)
R
θ
JATJ(pk)
– TA = P
(pk) Zθ
JA(t)
Design Note: Use of Transient Thermal Resistance Data
FIGURE A
t
P
P
P
P
P
t
1
1/f
DUTY CYCLE
+
t1f
+
t
1
t
P
PEAK PULSE POWER = P
P
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Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to i nsure proper solder connection
interface between the board and the p ackage. With the correct p ad geometry, the packages will s elf align when subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the pad size. T his can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T
J(max)
, the maximum rated junction temperature of the
die, R
θJA
, the thermal resistance from the device junction to ambient, a nd the operating temperature, TA. Using t he values provided on the data sheet for the SOT–23 package, PD can be calculated as follows:
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts.
The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short t ime could r esult in device failure. T herefore, the following items should always be o bserved in o rder t o minimize t he thermal s tress t o which the devices a re subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
PD =
T
PD =
150°C – 25°C
556°C/W
J(max)
R
θJA
– T
A
= 225 milliwatts
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Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE DIMENSIONS
D
J
K
L
A
C
B
S
H
GV
3
1
2
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
DIMAMIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B 0.0472 0.0551 1.20 1.40 C 0.0350 0.0440 0.89 1.11 D 0.0150 0.0200 0.37 0.50 G 0.0701 0.0807 1.78 2.04 H 0.0005 0.0040 0.013 0.100 J 0.0034 0.0070 0.085 0.177 K 0.0180 0.0236 0.45 0.60 L 0.0350 0.0401 0.89 1.02 S 0.0830 0.0984 2.10 2.50 V 0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
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MMBT6427LT1
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Motorola Small–Signal Transistors, FETs and Diodes Device Data
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MMBT6427LT1/D
*MMBT6427LT1/D*
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