Datasheet ML6554CU Datasheet (Micro Linear Corporation)

November 1999

FEATURING

POWER SOP

High-Performance

Thermal Dissipation Package

PRELIMINARY

ML6554

3A Bus Termination Regulator

GENERAL DESCRIPTION

The ML6554 switching regulator is designed to convert
voltage supplies ranging from 2.3V to 4V into a desired
output voltage or termination voltage for various
applications. The ML6554 can be implemented to
produce regulated output voltages in two different modes.
In the default mode, when the V
ML6554 output voltage is 50% of the voltage applied to
V

. The ML6554 can also be used to produce various

CCQ

user-defined voltages by forcing a voltage on the VREF
pin. In this case, the output voltage follows the input
VREFIN voltage. The switching regulator is capable of
sourcing or sinking up to 3A of current while regulating an
output VTT voltage to within 3% or less.

The ML6554, used in conjunction with series termination
resistors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator
can be used as a termination voltage for other bus
interface standards such as SSTL, CMOS, Rambus™,
GTL+, VME, LV-CMOS, LV-TTL, and PECL.

pin is open, the

REF

IN

FEATURES

■ Power SOP package

■ Can source and sink up to 3A, no heat sink required

■ Integrated Power MOSFETs

■ Generates termination voltages for SSTL-2 SDRAM,

SGRAM, or equivalent memories

■ Generates termination voltages for active termination

schemes for GTL+, Rambus, VME, LV-TTL, PECL and
other high speed logic

■ V

■ Separate voltages for V

■ Buffered V

■ V

■ Minimum external components

■ Shutdown for standby or suspend mode operation

input available for external voltage divider

REF

and PV

output

REF

of ±3% or less at 3A

OUT

CCQ

DD

BLOCK DIAGRAM

15

V

CCQ

+
–

10

11

13

200kΩ

VREF

200kΩ

AGND

IN

■ Thermal Shutdown » 130ºC

GND

9

SRQ

12

V

DD

Q

SHDN

2

4 58

PV

P

GND1

DD1

7

PV

DD2

V

L1

(V

)

OUT

3

6

V

L2

(V

)

OUT

P

GND2

AV

REF

14

CC

BUFFER

+
–

VREF

OUT

OSCILLATOR/

GENERATOR

ERROR AMP

RAMP

16

V

V

FB

1

V

DD

–
+

RAMP
COMPARATOR

D

1

ML6554

PIN CONFIGURATION

PIN DESCRIPTION

ML6554

16-Pin PSOP (U16)

PV

P

GND1

P

GND2

PV

D

GND

V

DD

DD1

V

V

DD2

L1

L2

1

2

3

4

5

6

7

8

TOP VIEW

AV

16

15

14

13

12

11

10

9

CC

V

CCQ

VREF

AGND

SHDN

VREF

V

FB

V

DD

OUT

IN

PIN NAME FUNCTION

1V
2PV

DD

DD1

Digital supply voltage
Voltage supply for internal po wer

transistors
3V
4P

5P

6V
7PV

L1

GND1

GND2

L2

DD2

Output voltage/ inductor connection

Ground for output power transistors

Ground for output power transistors

Output voltage/inductor connection

Voltage supply for internal po wer

transistors
8D

GND

Digital ground

PIN NAME FUNCTION

9V

10 V

DD

FB

Digital supply voltage
Input for external compensation

feedback

11 VREF

IN

Input for external reference voltage

12 SHDN Shutdown active low. CMOS input

level

13 AGND Ground for internal reference voltage

divider
14 VREF
15 V

CCQ

OUT

Reference voltage output

Voltage reference for internal voltage

divider
16 AV

CC

Analog voltage supply

2

NOVEMBER, 1999

ABSOLUTE MAXIMUM RATINGS

ML6554

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional

Lead Temperature (Soldering, 10 sec) ..............................

Thermal Resistance (qJC)(Note 3) ........................... 2°C/W

Output Current, Source or Sink.................................3.0A

device operation is not implied.

OPERATING CONDITIONS

Temperature Range ....................................... 0°C to 70°C

PVDD Operating Range................................ 2.0V to 4.0V

+ 0.3V

IN

5.0V

PV

..........................................................................................

DD

Voltage on Any Other Pin ......GND – 0.3V to V

Average Switch Current (I

)..................................3.0A

AVG

Junction T emperature.......................................................

Storage Temperature Range .............................................

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, PVDD = 3.3V±10%, TA = Operating Temperature Range (Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SWITCHING REGULATOR

V

VREF

Z

Output Voltage, SSTL_2 I

TT

(See Figure 1) V

Internal Resistor Divider I

OUT

V

IN

Reference Pin Input Impedance Note 2 V

REF

= 0, V

OUT

= open V

REF

Note 2 V
I

= ±3A, V

OUT

V

= open V

REF

Note 2 V

= 0 V

OUT

Note 2 V

= 2.3V 1.12 1.15 1.18 V

CCQ

= 2.5V 1.22 1.25 1.28 V

CCQ

= 2.7V 1.32 1.35 1.38 V

CCQ

= 2.3V 1.09 1.15 1.21 V

CCQ

= 2.5V 1.19 1.25 1.31 V

CCQ

= 2.7V 1.28 1.35 1.42 V

CCQ

= 2.3V 1.139 1.15 1.162 V

CCQ

= 2.5V 1.238 1.25 1.263 V

CCQ

V

= 2.7V 1.337 1.35 1.364 V

CCQ

= 0 100 kW

CCQ

Switching Frequency 650 kHz

DV

OFFSET

Offset Voltage V

TT

– VREF

OUT

V

= 2.5V No Load V

CCA

SUPPLY

I

Quiescent Current I

Q

= 0, no load I

OUT

BUFFER

I

REF

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: AV
Note 3: Infinite heat sink

Output Load Current 3 mA

, PVDD = 3.3V ±10%

CC

NOVEMBER, 1999

= 2.5 –12.5 12.5 mV

CCQ

VCCQ

I

AVCC

I

DVCC

10 µA

500 µA

7mA

3

ML6554

FUNCTIONAL DESCRIPTION

This switching regulator is capable of sinking and sourcing
3A of current without an external heatsink. The ML6554
uses a power surface mount package (PSOP) that includes
an integrated heat slug. The heat can be piped through the
bottom of the device and onto the PCB (Figure 2).

The ML6554 integrates two power MOSFETs that can be
used to source and sink 3A of current while maintaining a
tight voltage regulation. Using the external feedback, the
output can be regulated well within 3% or less,
depending on the external components chosen. Separate
voltage supply inputs have been added to accommodate
applications with various power supplies for the databus
and power buses.

OUTPUTS

, V

The output voltage pins (V

L1

are tied to the databus,

L2)

address, or clock lines via an external inductor. See the
Applications section for recommendations. Output
voltage is determined by the V

or VREFIN inputs.

CCQ

INPUTS

The input voltage pins (V
output voltages (VL1 or V
the VREF
the V

pin is floating, the output voltage is 50% of

IN

CCQ

input. V

can be the reference voltage for the

CCQ

or VREFIN) determine the

CCQ

. In the default mode, where

L2)

databus.

Output voltage can also be selected by forcing a voltage
at the VREF
the voltage at the VREF

pin. In this case, the output voltage follows

IN

input. Simple voltage dividers

IN

can be used this case to produce a wide variety of output
voltages between 2.3V to 4V.

VREF INPUT AND OUTPUT

The VREF
outputs (Inputs section, above). The VREF

input can be used to force a voltage at the

IN

OUT

pin is an
output pin that is driven by a small output buffer to
provide the V

signal to other devices in the system.

REF

The output buffer is capable of driving several output
loads. The output buffer can handle 3mA.

OTHER SUPPLY VOLTAGES

Several inputs are provide for the supply voltages: PV
PV

, AVCC, and VDD.

DD2

The PV

DD1

and PV

and provide the power supply to

DD2

DD1

the power MOSFETs. VDD provides the voltage supply to
the digital sections, while AV

supplies the voltage for

CC

the analog sections. Again, see the Applications section
for recommendations.

FEEDBACK INPUT

The VFB pin is an input that can be used for closed loop
compensation. This input is derived from the voltage
output. See application section for recommendation.

,

TPI

V

TT

TO SDRAMS

C1
820µF
F2V
OS-CON

L1 3.3µH

C2

0.1µF

R1 100Ω

C3 0.1µF

C4 0.1µF

R2 100Ω

1

V

DD

2

PV

3

V

L1

4

P

GND1

5

P

GND2

6

V

L2

7

PV

8

D

GND

R4 100kΩ

R5 1kΩ

Figure 1.

C9 0.1µF

U1

ML6554

DD1

DD2

C7 1nF

VREF

AV

V

CCQ

OUT

AGND

SHDN

VREF

V

V

CC

DD

220µF

2.5V TO 4V

220µF

GNDGND

C8 0.1µF

R3

100kΩ

16

15

14

13

12

11

IN

10

FB

9

V

CCQ

VREF

SHDN

VREF

OUT

IN

4

NOVEMBER, 1999

APPLICATIONS

ML6554

USING THE ML6554 FOR SSTL BUS TERMINATION

The circuit schematic in Figure 1 shows a recommended
approach for an constructing a bus terminating solution for
an SSTL-2 bus. This circuit can be used in PC memory and
Graphics memory applications as shown in Figures 3 and

4. Note that the ML6554 can provide the voltage
reference (V
the layout as shown in Figures 5, 6, and 7, and measuring
the VTT performance using the test setup as described in
Figure 8, the ML6554 delivered a VTT ± 20mV for 1A to
3A loads (see Figure 9). Table 1 provides a recommended
parts list. For more recent Applications Notes or
Evaluation Boards contact Micro Linear.

POWER HANDLING CAPABILITY OF THE PSOP PACKAGE

Using the board layout shown in Figures 5,6, and 7;
soldering the ML6554 to the board at zero LFPM the
temperature around the package measured 55ºC for 3A
loads. Note that a 1ounce copper plane was used in the
board construction.

) and terminating voltages (VTT). Using

REF

Airflow is not likely to be needed in the operation of this
device (assuming a board layout similar to that described
above). T he power handling performance of the PSOP
package is shown by a study of the package manufacturer
for various airflow vs. qJA conditions in Figure 10.

BUS TERMINATION SOLUTIONS FOR OTHER BUSES

Table 2 provides a summary of various bus termination
V

& V

REF

those applications.

requirements. The ML6554 can be used for

TT

Figure 2. Cutaway view of PSOP Package

NOVEMBER, 1999

HEAT SLUG

5

ML6554

168/184/208-PIN DIMM CONNECTORS

AND SDRAM/SGRAM MODULES

TERMINATION

RESISTORS

PC CHIP SET

NORTHBRIDGE

DATA LINE, CLOCK LINES,

ADDRESS LINES, CONTROL LINES

TERMINATION

RESISTORS

VREF

Figure 3. Complete Termination Solution PC Main Memory (PC Motherboard)

VTT

ML6554

6

NOVEMBER, 1999

ML6554

3D

GRAPHIC CHIP

DATA LINE, CLOCK LINES,

ADDRESS LINES, CONTROL LINES

TERMINATION

RESISTORS

VOLTAGE

REGULATOR

5V OR 3.3V

2.5V

SO DIMM

AND MODULES

TERMINATION

RESISTORS

SGRAM

VREF

ML6554

VTT

AGP/PCI BUS

Figure 4. Complete Termination Solution Graphics Memory Bus – AGP Graphics Cards

NOVEMBER, 1999

7

ML6554

Figure 5. Top Silk

Figure 6. Top Layer Figure 7. Bottom Layer

8

NOVEMBER, 1999

3.3V POWER
SUPPLY

ML6554

VA

V

CCQ

SUPPLY

VA

ACTIVE
CLAMP

V

CCQ

Figure 8. Test Circuit Setup

V

DD

ML6554

EVAL

GND

V

TT

CURRENT SOURCE/SINK

POWER SUPPLY

I

TT

VTT VARIANCE WITH VDD@ITT (V

1.29

1.28

(V)

TT

V

1.27

1.26

2.0 2.5 3.0 4.03.5

TESTED WITH EVAL PCB

VDD (V)

Figure 9. VTT Performance for SSTL-2 Bus

CCQ

2.5V)

I

TT

3A SINKING

2A SINKING

1A SINKING

0A SINKING

3A SOURCING

2A SOURCING

1A SOURCING

NOVEMBER, 1999

9

ML6554

ITEM QTY DESCRIPTION MANUFACTURER / PART NUMBER DESIGNATOR

RESISTORS

1 2 100W1210 SMD P anasonic/ERJ-8ENF1000V R1, R2
211kW 1210 SMD P anasonic/ERJ-8ENF1001V R5
3 2 100kW1210 SMD P anasonic/ERJ-8ENF1003V R3, R4

CAPACITORS

4 3 0.1µF 1210 Film SMD Panasonic/ECV3VB1E104K C2, C8, C9

Panasonic/ECU-V1H104KBW
5 1 820µF 2V Solid Elect. SMD Sanyo/ 2SV820M Os Con C1
6 2 330µF Tant 6.3V 100mW AVX/ TPSE337M006R0100 C5, C6
7 1 1nF 1210 Film SMD Panasonic/ECU-V1H102KBM C7
8 2 0.1µF 0805 Film Panasonic/ECJ-2VF1C104Z C3, C4

ICS

9 1 ML6554 Bus Terminator ML6554CU U1

Power SOP Package

MAGNETICS

1 0 1 3.3µH 5A inductor SMD Coilcraft/D03316P-332HC L1

Pulse Eng./ P0751.332T

Gowanda/SMP3316-331M

XFMRS inc./XF0046-S4

OTHER

11 1 Scope probe socket Tektronics/131-4353-00 TP1
1 2 1 12 Pin breakaway strip Sullins/PTC36SAAN (36 PINS) I/O, standoffs

VENDOR LIST

1. AVX [phone]

2. Sanyo [phone]

3. Tektronix [phone]

4. Coilcraft [phone]

5. Pulse [phone]

6. Gowanda [phone]

7. Xfmrs Inc. [phone]

8. Panasonic [phone]

9. Digikey [phone]

Table 1. Recommend Parts List for SSTL-2 Termination Circuit

10

NOVEMBER, 1999

ML6554

(ºC/W)

JA

θ

60

40

20

0

0.2 1.0 1.4 1.80.6

0.0

0.4 1.2 1.6 2.00.8

POWER (W)

NATURAL CONVECTION ΘJA TEST RESULTS

1.27mm PITCH PowerSOP™ 2
SLUG SOLDERED

Figure 10. Graphical Results Summary – 1S2P Test Board

16Ld PSOP2

2.3x3.1mm PAD

1.9mm DIE

60

40

(ºC/W)

JA

Θ

20

16Ld PSOP2

2.3x3.1mm PAD

0

0 200 300 500

AIR VELOCITY (LFPM)

FORCED CONVECTION ΘJA TEST RESULTS

1.27mm PITCH PowerSOP™ 2

1.9mm DIE @ 0.8 WATTS

SLUG SOLDERED

400100

DRAWING NUMBER ENG-CB-1007 REV A

Applicable Jedec Spec JC 51-X (Note 1)

(Sroposed Spec)

Substrate Material FR-4
Dimensions (LxW) (Overall) 114.3 x 76.2mm
Dimensions (LxW) (Metallization) 55 x 65mm
Dimensions (LxW) (Inner Planes) 73 x 73mm
Thickness 1.6 mm
Pitch 1.27mm
Stackup (# Signal Layers, # Cu Planes) 1S2P
Cu Trace Coverage (Signal Layer) 12%
Cu Coverage (Internal Layer) 100%
T r ace W idth (Spec/Measured) 235.5±25.5/288µm
Trace Cu Thickness (Spec/Measured) 70±14/67µm
Inner Cu Thickness (Spec/Measured) 35±3.5/31µm
Build # C1797

Note 1: Proposed Spec "Thermal Test Board with Two Internal Solid Copper Planes for leaded Surface Mount Packages".

Figure 11. Test Board Layout for QJA vs. Airflow

NOVEMBER, 1999

11

ML6554

BUS DESCRIPTION DRIVING VDDQ VTT VREF MICRO INDUSTRY

METHOD LINEAR SYSTEM

SOUTIONS COMPONENTS

GTL+ Gunning Open Drain 5v or 3.3V 1.5V±10% 1.0V±2% ML6554CU; 300 to 500MHz

Tr ansceiver Note 10 Note12 Note 11 Mode: V

REF

Bus Plus Input = 1.5V, PC Chipsets;

VCC = 5V GTLP 16xxx

SSTL_2 Series Stub Symmetric 2.5V±10% 0.5x(V

) 2.5V ML6554CU SSTL SDRAM;

DDQ

Terminated Drive, Series ±3% or ML6553CS; Hitachi,
Logic for 2V Resistance Mode: V

REF

Input = Floating NEC, Micro,
or Forced, Mitsubishi
VCC = 3.3V

RAMBUS RAMBUS Open Drain None 2.5V 2.0V ML6553CS; nDRAM,

Signaling Specified Mode: V

REF

Logic Input = Open, Intel, Toshiba

V

= V

CC

DDQ

L V-TTL Low Voltage Symmetric 3.3±10% V

TTL Logic or Drive Mode: V

/2 3.3V ML6553CS; Processors o r

DDQ

REF

PECL or Input = Open, LV-TTL

3.3V VME VCC = VDDQ SDRAM,

Processor;

Buffers;
Fairchild,
Texas Instr.

Fujitsu,

RAMBUS,

backplanes;

EDO RAM

12

Table 2. Termination Solutions Summary By Buss Type

NOVEMBER, 1999

PHYSICAL DIMENSIONS inches (millimeters)

Package: U16

16-Pin PSOP

0.386 - 0.393

PIN 1 ID

9.80 - 9.98

HEAT SLUG

0.150 - 0.157

3.81 - 3.99

16

ML6554

HEAT SLUG

DIMENSIONS:

0.079 × 0.279
(2.01 × 7.09)

0.230 - 0.244
(5.84 - 6.20)

0.017 - 0.027

0.43 - 0.69
(4 PLACES)

0.055 - 0.061
(1.40 - 1.55)

1

0.014 - 0.019
(0.35 - 0.49)

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML6554CU 0°C to 70°C 16-Pin PSOP (U16)

0.050 BSC
(1.27 BSC)

0.061 - 0.068
(1.55 - 1.73)

SEATING PLANE

Micro Linear Corporation

2092 Concourse Drive

San Jose, CA 95131
T el: [phone]

Fax: [phone]

www .microlinear.com

0.00 - 0.004

(0.127 - 0.25)

0º - 8º

0.016 - 0.035
(0.41 - 0.89)

0.0075 - 0.0098
(0.19 - 0.25)

© Micro Linear 1999. is a registered trademark of Micro Linear Corporation. All other trademarks are the
property of their respective owners.

Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116;
5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376;
5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174;
5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223;
5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.

Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents
of this publication and reserves the right to make changes to specifications and product descriptions at any time without
notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted
by this document. The circuits contained in this document are offered as possible applications only. Particular uses or
applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged
to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including
liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property
right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications.

DS6554-01

NOVEMBER, 1999

13

To receive a price quote or to request a
product sample, call or send e-mail to your
local representative.

When sending e-mail, be sure to include the
Micro Linear part number and whether you
want a price quote or a sample in the subject
line.

(i.e. subject: Sample request - ML part#xxxx)

Click here to find your local representative