Datasheet ML2280BCS, ML2283CCP, ML2283CIP, ML2280CIS, ML2280CCS Datasheet (Micro Linear Corporation)

May 1997

ML2280*, ML2283**

Serial I/O 8-Bit A/D Converters

GENERAL DESCRIPTION

The ML2280 and ML2283 are 8-bit successive
approximation A/D converters with serial I/O and
configurable input multiplexers with up to 4 input
channels.

All errors of the sample-and-hold incorporated on the
ML2280 and ML2283 are accounted for in the analog-to­digital converters accuracy specification.

The voltage reference can be externally set to any value
between GND and VCC, thus allowing a full conversion
over a relatively small voltage span if desired.

The ML2283 is an enhanced double polysilicon, CMOS,
pin-compatible second source for the ADC0833 A/D
converter. All parameters are guaranteed over temperature
with a power supply voltage of 5V ±10%.

FEATURES

■ Conversion time: 6µs

■ ML2280 capable of digitizing a 5V, 40kHz sine wave

■ Total unadjusted error with external

reference: ±1/2LSB or ±1LSB

■ Sample-and-hold: 375ns acquisition

■ 0 to 5V analog input range with single 5V

power supply

■ 2.5V reference provides 0 to 5V analog input range

■ No zero- or full-scale adjust required

■ Low power: 12.5mW MAX

■ Analog input protection: 25mA (min) per input

■ Differential analog voltage inputs (ML2280)

■ Programmable multiplexer with differential or single

ended analog inputs (ML2283)

■ 0.3" width 8- or 14-pin DIP, or 8-Pin SOIC (ML2280)

■ Superior pin-compatible replacement for ADC0833

* This Part Is Obsolete
** This Part Is End Of Life As Of August 1, 2000

BLOCK DIAGRAM

ML2281

A/D WITH SAMPLE & HOLD FUNCTION

V

IN+

V

IN–

8pF

8pF

+

+

Σ

COMP

–

–

CONTROL

AND

TIMING

OUTPUT

SHIFT-REGISTER

SUCCESSIVE

APPROXIMATION

REGISTER

D/A

CONVERTER

V

CC

GND

V

CS

CLK

DO

REF/2

CH0

CH1

CH2

CH3

4-BIT

4-CHANNEL

S.E.
OR

2-CHANNEL

DIFF

MULTIPLEXER

ML2283

SHIFT-REGISTER

CONTROL

AND

TIMING

SHIFT-REGISTER

CONVERTER

SAMPLE & HOLD

V

AGND

INPUT

OUTPUT

A/D

WITH

FUNCTION

REF/2

V

CC

DI

SARS

CLK

CS

DO

SE

DGND

SHUNT

REGULATOR

V+

1

ML2280, ML2283

PIN CONFIGURATION

ML2280

Single Differential Input

8-Pin PDIP

CS

V

IN

V

IN

GND

1

2

+

3

–

4

TOP VIEW

8

7

6

5

PIN DESCRIPTION

V

CLK

DO

V

CC

REF/2

ML2280

Single Differential Input

8-Pin SOIC

CS

V

IN

V

IN

GND

1

2

+

3

–

4

TOP VIEW

8

7

6

5

V

CLK

DO

V

CC

REF/2

4-Channel MUX

14-Pin PDIP

1

V+

2

CS

3

CH0

4

CH1

5

CH2

6

CH3

DGND

7

ML2283

TOP VIEW

8

V

CC

9

DI

10

CLK

11

SARS

12

DO

13

V

REF/2

14

AGND

NAME FUNCTION

V

CC

Positive supply. 5V ± 10%

DGND Digital ground. 0 volts. All digital inputs and

outputs are referenced to this point.

AGND Analog ground. The negative reference voltage

for A/D converter.
GND Combined analog and digital ground.
CH0, Analog inputs. Digitally selected to be single

VIN+, VIN– ended (VIN) or; VIN+ or VIN– of a differential

input. Analog range = GND - VIN - VCC.
V

REF/2

Reference. The analog input range is twice the

positive reference voltage value applied to this

pin.
V+ Input to the Shunt Regulator.
DO Data out. Digital output which contains result

of A/D conversion. The serial data is clocked

out on falling edges of CLK.

NAME FUNCTION

SARS Successive approximation register status.

Digital output which indicates that a
conversion is in progress. When SARS goes
to 1, the sampling window is closed and
conversion begins. When SARS goes to 0,
conversion is completed. When CS = 1, SARS
is in high impedance state.

CLK Clock. Digital input which clocks data in on

DI on rising edges and out on DO on falling
edges. Also used to generate clocks for A/D
conversion.

DI Data input. Digital input which contains serial

data to program the MUX and channel
assignments.

CS Chip select. Selects the chip for multiplexer

and channel assignment and A/D conversion.
When CS = 1, all digital outputs are in high
impedance state. When CS = 0, normal A/D
conversion takes place.

2

ML2280, ML2283

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Current into V+ ...................................................... 15mA

Supply Voltage, VCC................................................. 6.5V

Voltage

Logic Inputs ........................................... –7 to VCC +7V

Analog Inputs ................................ –0.3V to VCC +0.3V

Input Current per Pin (Note 1) .............................. ±25mA

Storage Temperature ................................ –65°C to 150°C

Package Dissipation

at TA = 25°C (Board Mount) .............................800mW

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, TA = T

SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX MIN NOTE 3 MAX UNITS

MIN

to T

, VCC = 5V ±10%, f

MAX

Lead Temperature (Soldering 10 sec.)

Dual-In-Line Package (Molded) .......................... 260°C

Dual-In-Line Package (Ceramic) ......................... 300°C

OPERATING CONDITIONS

Supply Voltage, VCC............................ 4.5VDC to 6.3V

Temperature Range (Note 2) ................. T

ML2280 BIP, ML2283 BIP ...................... –40°C to 85°C

ML2280 CIP, ML2283 CIP

ML2280 BCP, ML2283 BCP ......................0°C to 70°C

ML2280 CCP, ML2283 CCP

= 1.333MHz, and V

CLK

ML228XB ML228XC

TYP TYP

REF/2

= 2.5V.

MIN

- TA - T

DC

MAX

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Total Unadjusted V
Error V

Reference Input (Note 4) 10 15 20 10 15 20 kW
Resistance

Common-Mode (Notes 4, 7) GND V
Input Range –0.05 +0.05 –0.05 +0.05

DC Common-Mode Common mode voltage ±1/16 ±1/4 ±1/16 ±1/4 LSB
Error voltage GND to V

AC Common-Mode Common mode voltage ±1/4 ±1/4 LSB
Error GND to V

DC Power Supply V
Sensitivity V

AC Power Supply 100mV
Sensitivity on V

Change in Zero 15mA into V+ ±1/2 ±1/2 LSB
Error from V
to Internal Zener V
Operation

=5V VCC = N.C.

CC

= 2.5V ±1/2 ±1 LSB

REF/2

not connected ±2 ±2 LSB

REF/2

(Notes 4, 6)

(Note 5)

0 to 50kHz (Note 5)

= 5V ±10% ±1/32 ±1/4 ±1/32 ±1/4 LSB

CC

- VCC +0.1V

REF

(Note 5)

P-P

(Note 5)

CC

= 2.5V (Note 5)

REF/2

CC/2

,

CC

, 25kHz sine ±1/4 ±1/4 LSB

CC

GND V

CC

V

V

V+ Input Resistance (Note 4) 20 35 20 35 kW

Internal Diode 15mA into V+ 6.9 6.9 V

Z

Regulated Break­down (at V+)

3

ML2280, ML2283

ELECTRICAL CHARACTERISTICS (Continued)

ML228XB ML228XC

TYP TYP

SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX MIN NOTE 3 MAX UNITS

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)

I

OFF

Off Channel On channel = V

CC

–1 –1 µA

Leakage Current Off channel = 0V

(Notes 4, 8)

On channel = 0V +1 +1 µA
Off channel = V

CC

(Notes 4, 8)

I

ON

On Channel On channel = 0V –1 –1 µA
Leakage Current Off channel = V

CC

(Notes 4, 8)

On channel = V

CC

+1 +1 µA
Off channel = 0V
(Notes 4, 8)

TYP

SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX UNITS

DIGITAL AND DC CHARACTERISTICS

V

IN(1)

V

IN(0)

I

IN(1)

I

IN(0)

V

OUT(1

V

OUT(0)

I

OUT

I

SOURCE

I

SINK

I

CC

Logical “1” Input Voltage (Note 4) 2.0 V

Logical “0” Input Voltage (Note 4) 0.8 V

Logical “1” Input Current VIN = V

(Note 4) 1 µA

CC

Logical “0” Input Current VIN = 0V (Note 4) –1 µA

Logical “1” Output Voltage I

Logical “0” Output Voltage I

HI-Z Output Current V

Output Source Current V

Output Sink Current V

= –2mA (Note 4) 4.0 V

OUT

= 2mA (Note 4) 0.4 V

OUT

= 0V (Note 4) –1 µA

OUT

V

= V

OUT

OUT

OUT

CC

= 0V (Note 4) –6.5 mA

= V

(Note 4) 8.0 mA

CC

1µA

Supply Current (Note 4) 1.3 2.5 mA

4

ML2280, ML2283

ELECTRICAL CHARACTERISTICS (Continued)

TYP

SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX UNITS

AC ELECTRICAL CHARACTERISTICS

f

CLK

t

ACQ

t

C

Clock Frequency (Note 4) 10 1333 kHz

Sample-and-Hold Acquisition 1/2 1/f

Conversion Time Not including MUX adddressing time 8 1/f

SNR Signal to Noise Ratio VIN = 40kHz, 5V sine. f

ML2280 (f

SAMPLING

@ 120kHz). Noise is sum of all

nonfundamental components up to 1/2
of f

SAMPLING

(Note 11)

THD Total Harmonic Distortion VIN = 40kHz, 5V sine. f

ML2280 (f

SAMPLING

@ 120kHz). THD is sum of 2,

3, 4, 5 harmonics relative to fundamental
(Note 11)

IMD Intermodulation Distortion V

ML2280 f

= fA + fB. fA = 40kHz, 2.5V sine. –60 dB

IN

= 39.8kHz, 2.5V Sine, f

B

(f

SAMPLING

(f

A

@ 120kHz). IMD is (fA + fB),

– fB), (2fA + fB), (2fA – fB), (fA + 2fB),

(fA – 2fB) relative to fundamental (Note 11)

Clock Duty Cycle (Notes 4, 9) 40 60 %

t

SET-UP

CS Falling Edge or Data Input (Note 4) 130 ns
Valid to CLK Rising Edge

t

HOLD

Data Input Valid after (Note 4) 80 ns
CLK Rising Edge

t

, CLK Falling Edge to Output CL = 100pF (Note 4 & 10)

PD1

t

PD0

Data Valid Data MSB first 90 200 ns

Data LSB first 50 110 ns

= 1.333MHz 47 dB

CLK

= 1.333MHz –60 dB

CLK

= 1.333MHz

CLK

CLK

CLK

t

, Rising Edge of CS to Data CL = 10pF, RL = 10kW (see high impedance 40 90 ns

1H

t

0H

Output and SARS Hi-Z test circuits) (Note 5)

CL = 100pF, RL = 2kW (Note 5) 80 160 ns

C

IN

C

OUT

Note 1: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND < or VIN > VCC) the absolute value of current at that pin should be limited to

Note 2: 0°C to 70°C and –40°C to 85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by

Note 3: Typicals are parametric norm at 25°C.
Note 4: Parameter guaranteed and 100% tested.
Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 6: Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
Note 7: For VIN– • VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for

Note 8: Leakage current is measured with the clock not switching.
Note 9: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,

Note 10: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for

Note 11: Because of multiplexer addressing, test conditions for the ML2283 is V

Capacitance of Logic Input 5 pF

Capacitance of Logic Outputs 5 pF

25mA or less.

correlation with worst-case test conditions.

analog input voltages one diode drop below ground or one diode drop greater than the V
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog V
be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V
tolerance and loading.

the minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.

comparator response time..

or V

IN

= 30kHz, 5V sine (f

IN

supply. Be careful, during testing at low VCC levels (4.5V), as high level

CC

does not exceed the supply voltage by more than 50mV, the output code will

REF

SAMPLING

ª 89kHz)

over temperature variations, initial

DC

5

ML2280, ML2283

DATA

OUTPUT

DATA

OUTPUT

t

1H

V

CC

CS

R

C

L

L

DO AND

SARS OUTPUTS

t

0H

V

CC

R

L

C

L

DO AND

SARS OUTPUTS

CS

GND

V

OH

GND

V

GND

V

V

t

1H

t

r

90%

50%

10%

t

1H

90%

t

0H

t

50%

10%

90%

t

0H

r

10%

CC

CC

OL

Figure 1. High Impedance Test Circuits and Waveforms

CLK

CS

DATA

IN (DI)

Data Input Timing

t

SET-UP

t

HOLD

CLK

CS

t

SET-UP

t

HOLD

ML2281 Start Conversion Timing

t

SET-UP

START CONVERSION

CLK

DATA

OUT (DO)

Data Output Timing

t

PD0, tPD1

SE

t

SET-UP

t

PD0, tPD1

DO

BIT 7

(MSB)

BIT 6

Figure 2. Timing Diagrams

6

CLOCK (CLK)

CHIP SELECT (CS)

DATA OUT (DO)

SAMPLE & HOLD

ACQUISITION (t

ACQ

ML2280, ML2283

ML2280 Timing

1

234567891011

t

SET-UP

t

C

HI-Z

)

76 5432 10

(MSB) (LSB)

*LSB FIRST OUTPUT NOT AVAILABLE ON ML2280

*

HI-Z

CLOCK (CLK)

CHIP SELECT (CS)

DATA IN (DI)

SAR STATUS (SARS)

DATA OUT (DO)

ML2283 Timing

123456789101112131415161718192021

t

SET-UP

ADDRESS MUX

START

HI-Z HI-Z

ACQUISITION (t

ODD/SIGN

BIT

SGL/DIF SELECT

HI-Z HI-Z

SAMPLE & HOLD

ACQ

BIT 1

)

SELECT

BIT 0

A/D CONVERSION IN PROCESS

765 432 0 12345

(MSB)

OUTPUT DATA

DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION

LSB FIRST DATAMSB FIRST DATA

671

Figure 2. Timing Diagrams (Continued)

7

ML2280, ML2283

1.0

0.75

VCC = 5V
V

= 5V

REF

0.5

–55 C

LINEARITY ERROR (LSB)

0.25
25 C

0

0 0.01 0.1 1

CLOCK FREQUENCY (MHz)

Figure 3. Linearity Error vs f

1

V

= 5V

CC

f

= 1.333MHz

CLK

0.75

0.5

–55 C

LINEARITY ERROR (LSB)

0.25

0

0235

125 C

25 C

41

V

(VDC)

REF

125 C

CLK

LS193

LOAD

B0
COUNT
DOWN

A5VBCD

ML2280

CLK

V

+

IN

V

–

CS

IN

CLK

1

234567891011121314

START

CS

FSR

HI-Z HI-Z

DO

CLK

D7 D6 D5 D4 D3 D2 D1 D0

START

SRQ

DQ

DQ

DQ

TMS320

SERIES

Q

DSP

Q

Q

FSR
CLK

DRDO

Figure 4. Linearity Error vs V

Voltage

REF

Figure 5. Unadjusted Offset Error vs V

Voltage

REF

8

DI*

CS

ML2280, ML2283

13

2

CLK

CH0*

CH1

CH2*

CH3*

V

REF/2

V

CC

V+*

DGND*

AGND*

RRRR R

16

V

CC

3

4

5

6

9

14

1

8

INPUT PROTECTION—ALL LOGIC INPUTS

5-BIT SHIFT-REGISTER

SGL/DIF

V

CC

7V SHUNT
REGULATOR

ODD/

SIGN

MUX

ADDRESS

TO INTERNAL
CIRCUITRY

INPUT
13
16
17
18

ANALOG

(EQUIVALENT)

V

CC

TO

INTERNAL

CIRCUITS

+

MUX

SELECT 0SELECT 1START

Σ

–

R

C

C

LADDER

AND

DECODER

D

C

+
–

COMP

COMP

SAR

LOGIC

AND

LATCH

T

x

TIME

DELAY

DSTART 2

CS

B7
B6
B5
B4
B3
B2
B1
B0

CS

LSB FIRST

RRC

9-BIT

SHIFT

REGISTER

EOC

EOC

START

CS

CQR

DCQ

DCQ

C

R

D

D

R

R

Q

CS

DEOC

SARS*

11

CS

CS

CS

DSTART 1

CS

10

DO

* SOME OF THESE FUNCTIONS/PINS ARE NOT AVAILABLE WITH ML2280.

Figure 6. ML2288 Functional Block Diagram

MSB FIRST

PARALLEL XFR
TO SHIFT REGISTER

9

ML2280, ML2283

FUNCTIONAL DESCRIPTION

MULTIPLEXER ADDRESSING

The design of these converters utilizes a sample data
comparator structure which provides for a differential analog
input to be converted by a successive approximation routine.

The actual voltage converted is always the difference
between an assigned “+” input terminal and a “–” input
terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned “+” input is less than the “–”
input, the converter responds with an all zeros output code.

A unique input multiplexing scheme has been utilized
to provide multiple analog channels with software
configurable single ended, differential, or pseudo
differential options.

A particular input configuration is assigned during the
MUX addressing sequence, prior to the start of a
conversion. The MUX address selects which of the analog
inputs are to be enabled and whether this input is single
ended or differential. In the differential case, it also assigns
the polarity of the analog channels. Differential inputs are
restricted to adjacent channel pairs. For example, channel
0 and channel 1 may be selected as a different pair but
channel 0 or channel 1 cannot act differentially with any
other channel. In addition to selecting the differential
mode, the sign may also be selected. Channel 0 may be
selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is
illustrated by the MUX addressing codes shown in Table 1.

The MUX address is shifted into the converter via the DI
input. Since the ML2280 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.

Since the input configuration is under software control, it
can be modified, as required, at each conversion. A
channel can be treated as a single-ended, ground
referenced input for one conversion; then it can be
reconfigured as part of a differential channel for another
conversion. Figure 7 illustrates these different input modes.

SINGLE-ENDED MUX MODE

MUX ADDRESS CHANNEL#

SGL/ ODD/

DIF SIGN 1 0123

10 0 +
10 1 +
11 0 +
11 1 +

SELECT

COM is internally tied to AGND

DIFFERENTIAL MUX MODE

MUX ADDRESS CHANNEL#

SGL/ ODD/

DIF SIGN 1 0123

00 0 + –
00 1 + –
01 0 – +
01 1 – +

SELECT

Table 1. ML2283 MUX Addressing 4 Single-Ended

or 2 Differential Channel

4 Single-Ended

+

0

+

1

+

2

+

3

AGND

2 Differential

+ (–)

0, 1

– (+)

+ (–)

2, 3

– (+)

Mixed Mode

DIGITAL INTERFACE

The block diagram and timing diagrams in Figures 2-5
illustrate how a conversion sequence is performed.

A conversion is initiated when CS is pulsed low. This line
must me held low for the entire conversion. The converter is
now waiting for a start bit and its MUX assignment word.

A clock is applied to the CLK input. On each rising edge
of the clock, the data on DI is clocked into the MUX
address shift register. The start bit is the first logic “1” that
appears on the DI input (all leading edge zeros are
ignored). After the start bit, the device clocks in the next 2
to 4 bits for the MUX assignment word.

10

+

0, 1

-

+

2

+

3

AGND

Figure 7. Analog Input Multiplexer Functional Options

for ML2288

ML2280, ML2283

When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1/2
clock period is used for sample & hold settling through the
selected MUX channels. The SAR status output goes high
at this time to signal that a conversion is now in progress
and the DI input is ignored.

The DO output comes out of High impedance and
provides a leading zero for this one clock period.

When the conversion begins, the output of the
comparator, which indicates whether the analog input is
greater than or less than each successive voltage from the
internal DAC, appears at the DO output on each falling
edge of the clock. This data is the result of the conversion
being shifted out (with MSB coming first) and can be read
by external logic or µP immediately.

After 8 clock periods, the conversion is completed. The SAR
status line returns low to indicate this 1/2 clock cycle later.

The serial data is always shifted out MSB first during the
conversion. After the conversion has been completed, the
data can be shifted out a second time with LSB first. The
2280 data is shifted out only once, MSB first.

All internal registers are cleared when the CS input is
high. If another conversion is desired, CS must make a
high to low transition followed by address information.

The DI input and DO output can be tied together and
controlled through a bidirectional µP I/O bit with one
connection. This is possible because the DI input is only
latched in during the MUX addressing interval while the
DO output is still in the high impedance state.

REFERENCE

The ML2280 and ML2283 are intended primarily for use in
circuits requiring absolute accuracy. In this type of system,
the analog inputs vary between very specific voltage limits
and the reference voltage for the A/D converter must remain
stable with time and temperature. For ratiometric
applications, see the ML2281 and ML2284 which have a
V

input that can be tied to VCC.

REF

The voltage applied to the V

pin defines the voltage

REF/2

span of the analog input (the difference between VIN+ and
VIN–) over which the 256 possible output codes apply. A
full-scale conversion (an all 1s output code) will result when
the voltage difference between a selected “+”input and “–”
input is approximately twice the voltage at the V

REF/2

pin.
This internal gain of 2 from the applied reference to the full­scale input voltage allows biasing a low voltage reference
diode from the 5VDC converter supply. To accommodate a
5V input span, only a 2.5V reference is required. The output
code changes in accordance with the following equation:

2

/






Output Code



() ()

VV

+− −

IN IN

256

=



2

()

V



REF

where the output code is the decimal equivalent of the 8-bit
binary output (ranging from 0 to 255) and the term V

REF/2

is

the voltage to ground.

The V

pin is the center point of a two resistor divider

REF/2

(each resistor is 10kW) connected from VCC to ground. Total
ladder input resistance is the parallel combination of these
two equal resist. As show in Figure 8, a reference diode
requiring an external biasing resistor if its current
requirements meet the indicated level.

The minimum value of V

can be quite small (See

REF/2

Typical Performance Curves) to allow direct conversions of
transducer outputs providing less than a 5V output span.
Particular care must be taken with regard to noise pickup,
circuit layout and system error voltage sources when
operating with a reduced span due to the increased
sensitivity of the converter (1LSB equals V

REF/256

).

V

CC

5V

10kΩ

V

ML2280
ML2283

10kΩ

GND

V

FULL-SCALE

NOTE: NO EXTERNAL BIASING RESISTOR NEENED IF: V

≅ 2.4V

REF/2

1.2V

I

Z

+

V

Z

–

Figure 8. Reference Biasing

V

CC

10kΩ

ML2280
ML2283

10kΩ

GND

V

FULL-SCALE

V

CC

< AND IZ min. <

Z

2

≅ 5.0V

V

CC/2

5kΩ

– V

V

5V

REF/2

2.5V

Z

11

ML2280, ML2283

ANALOG INPUTS AND SAMPLE/HOLD

An important feature of the ML2280 and ML2283 is that
they can be located at the source of the analog signal and
then communicate with a controlling µP with just a few
wires. This avoids bussing the analog inputs long distances
and thus reduces noise pickup on these analog lines.
However, in some cases, the analog inputs have a large
common mode voltage or even some noise present along
with the valid analog signal.

The differential input of these converters reduces the effects
of common mode input noise. Thus, if a common mode
voltage is present on both “+” and “–” inputs, such as 60Hz,
the converter will reject this common mode voltage since it
only converts the difference between “+” and “–” inputs.

The ML2280 and ML2283 have a true sample and hold
circuit which samples both “+” and “–” inputs
simultaneously. This simultaneous sampling with a true S/H
will give common mode rejection and AC linearity
performance that is superior to devices where the two input
terminals are not sampled at the same instant and where
true sample and hold capability does not exist. Thus, these
A/D converters can reject AC common mode signals from
DC-50kHz as well as maintain linearity for signals from DC­50kHz.

The signal at the analog input is sampled during the interval
when the sampling switch is closed prior to conversion start.
The sampling window (S/H acquisition time) is 1/2 CLK
period wide and occurs 1/2 CLK period before DO goes
from high impedance to active low state. When the
sampling switch closes at the start of the S/H acquisition
time, 8pF of capacitance is thrown onto the analog input. 1/
2 CLK period later, the sampling switch is opened and the
signal present at the analog input is stored. Any error on the
analog input at the end of the S/H acquisition time will
cause additional conversion error. Care should be taken to
allow adequate charging or settling time from the source.
If more charging or settling time is needed to reduce these
analog input errors, a longer CLK period can be used.

For latchup immunity each analog input has dual diodes to
the supply rails, and a minimum of ±25mA (±100mA
typically) can be injected into each analog input without
causing latchup.

ZERO ERROR ADJUSTMENT

The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V

is not ground,

IN MIN

a zero offset can be done. The converter can be made to
output 00000000 digital code for this minimum input
voltage by biasing any VIN– input at this V

IN MIN

value.

This utilizes the differential mode operation of the A/D.

The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be
measured by grounding the VIN– input and applying a
small magnitude positive voltage to the VIN+ input. Zero
error is the difference between the actual DC input
voltage which is necessary to just cause an output digital
code transition from 00000000 to 00000001 and the ideal
1/2 LSB value (1/2 LSB = 9.8mV for V

= 5.000VDC).

REF

FULL-SCALE ADJUSTMENT

The full-scale adjustment can be made by applying a
differential input voltage which is 1-1/2 LSB down from
the desired analog full-scale voltage range and then
adjusting the magnitude of the V

input or VCC for a

REF

digital output code which is just changing from 11111110
to 11111111.

ADJUSTMENT FOR AN ARBITRARY ANALOG
INPUT VOLTAGE RANGE

If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input
signal which does not go to ground), this new zero
reference should be properly adjusted first. A VIN+ voltage
which equals this desired zero reference plus 1/2 LSB
(where the LSB is calculated for the desired analog span,
1 LSB = analog span/256) is applied to selected “+” input
and the zero reference voltage at the corresponding “–”
input should then be adjusted to just obtain the 00000000
to 00000001 code transition.

The full-scale adjustment should be made by forcing a
voltage to the VIN+ input which is given be:

V fs adjust V

+=−×

IN MAX

15

.



VV

−

()

MAX MIN



256








12

where V

The V

REF

= high end of the analog input range

MAX

V

= low end (offset zero) of the analog range

MIN

or VCC voltage is then adjusted to provide a

code change from 11111110 to 11111111.

SHUNT REGULATOR

A unique feature of the ML2283 is the inclusion of a shunt
regulator connected from V+ terminal to ground which
also connects to the VCC terminal (which is the actual
converter supply) through a silicon diode as shown in
Figure 8. When the regulator is turned on, the V+ voltage
is clamped at 11VBE set by the internal resistor ratio. The
typical I-V of the shunt regulator is shown in Figure 9.

ML2280, ML2283

It should be noted that before V+ voltage is high enough
to turn on the shunt regulator (which occurs at about

5.5V), 35kW resistance is observed between V+ and GND.
When the shunt regulator is not used, V+ pin should be
either left floating or tied to GND. The temperature
coefficient of the regulator is –22mV/°C.

12V

I + →

CURRENT LIMITING

RESISTOR, I+ ≤15mA

Figure 9. Shunt Regulator

V+

GND

28.8kΩ

3.2kΩ

3.2kΩ

15mA

I+

SLOPE =

1

35kΩ

5.5V

V+

6.9V

V

CC

Figure 10. I-V Characteristic of the Shunt Regulator

13

ML2280, ML2283

APPLICATIONS

CH0

ML2283 8051

CS

CLK

DI

DOCH3

P1

3

P1

2

P1

1

P1

0

8051 Interface and Controlling Software

MNEMONIC INSTRUCTION

START: ANL P1, #0F7H ;SELECT A/D (CS = 0)

MOV B, #5 ;BIT COUNTER ¨ 5
MOV A, #ADDR ;A ¨ MUX BIT

LOOP 1: RRC A ;CY ¨ ADDRESS BIT

JC ONE ;TEST BIT

;BIT = 0

ZERO: ANL P1, #0FEH ;DI ¨ 0

SJMP CONT ;CONTINUE

;BIT = 1

ONE: ORL P1, #1 ;D1 ¨ 1
CONT: ACALL PULSE ;PULSE SK 0 Æ 1 Æ 0

DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE
ACALL PULSE ;EXTRA CLOCK FOR SYNC
MOV B, #8 ;BIT COUNTER ¨ 8

LOOP 2: ACALL PULSE ;PULSE SK 0 Æ 1 Æ 0

MOV A, P1 ;CY ¨ DO
RRC A
RRC A
MOV A, C ;A ¨ RESULT
RLC A ;A(0) BIT ¨ AND SHIFT
MOV C, A ;C ¨ RESULT
DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE

RETI ;PULSE SUBROUTINE

PULSE: ORL P1, #04 ;SK ¨ 1

NOP ;DELAY
ANL P1, #0FBH ;SK ¨ 0
RET

14

APPLICATIONS (Continued)

51kΩ (4)

MUX ADDRESS

ML2280, ML2283

5V

DC

START BIT

SGL/DIF

0.01µF

CLOSE TO

START THE

A/D CONVERSION

5 V

DC

10kΩ

10kΩ

0.001µF

CLOCK

GENERATOR

CLK

+

START

START

CLK

CLK

NC

CLK

CLK

QD

CLK

1.3kΩ(8)

5V

15

2

1

DC

2

12

11

7

8

11

CLK INT

CLK

SHIFT/

LOAD

(OR VIN)

CS

CLK

SARS

GND

CLK
Q

H

86543141312

PARALLEL INPUTS

INPUT SHIFT REGISTER

74HC165

SIN

10

NC

1kΩ1kΩ 1kΩ 1kΩ

23

ANALOG INPUTS

ML2283

V

REF/2

2.5V

914

CLR

OUTPUT SHIFT REGISTER

74HC164

V+DGNDAGND

GND

7

NC

DO

9

CC

141789

Q

DO

14

DC

3456

01

A

345610111213

13

D1

DO

SI A

SI B

5V

DC

14

1

2

51kΩ

+10µF

V

5V

V

CC

V

CC

1/2 74HC74

MSB DATA DISPLAY LSB

ML2283 “Stand-Alone” or Evaluation Circuit

5V

DC

15

ML2280, ML2283

APPLICATIONS (Continued)

(+) V

DC

V

IN

R

L

ML2283

V

(–)

V

IN

T

10kΩ

MIN

A

ADJ.

R

SET

5V

CC

REF/2

+

10µF

V

CC

(5 VDC)

7.5kΩ

5kΩ
T

MAX

A

ADJ.

15V

+
–

–15V

DC

OP

AMP

DC

600Ω

DIODE CLAMPING IS NOT NEEDED

VIN (+)

(–)

V

IN

IF CURRENT IS LIMITED TO 25mA

ML2280

V

CC

V

CC

(5VDC)

+

10µF

Low-Cost Remote Temperature Sensor

V

CC

(5VDC)

100Ω
ZERO

ADJ.

0.1Ω

120kΩ

XDR

V

XDR

1kΩ

ZERO

ADJ.

100Ω

240kΩ

20kΩ

3kΩ

I

→

VIN (–)

LOAD

V

(2A FULL-SCALE)

CC

ML2280

V

IN

REF/2

3kΩ

+

1µF

V

(+)

Digitizing a Current Flow

V

CC

(5VDC)

VIN (+)

VIN (–)*

ML2280

V

CC

+

10µF

V

CC

(5VDC)

+

10µF

Protecting the Input

2kΩ

9.1kΩ

–

1kΩ

+

FS
ADJ.

2.5V

16kΩ

LOAD

16

0.35 V

CC

+

*V

(–) = 0.15V

IN

15% OF VCC ≤ V

CC

≤ 85% OF V

XDR

V

REF/2

CC

Operating with Ratiometric Transducers

1µF

–

1kΩ

+

FS
ADJ.

8.2kΩ

APPLICATIONS (Continued)

V

CC

(5VDC)

+

V

IN

VIN (+)

VIN (–)

ML2280

V

V

REF/2

CC

+

10µF

1kΩ

+

1µF

300Ω

10kΩ

FS

ADJ.

–
+

SET FOR 1.5V

2kΩ

1.2V

+

V

IN

SETS ZERO

CODE VOLTAGE

2.7kΩ

VIN (+)

VIN (–)

1kΩ
2V

DC

ZERO ADJ.

ML2280

330Ω

ML2280, ML2283

V

CC

(5VDC)

V

V

CC

REF/2

+

1kΩ

1.5
+

1µF

10µF

330Ω

10kΩ

FS

ADJ.

SETS

VOLTAGE SPAN

1.2V

1.2kΩ

Span Adjust: 0V - VIN - 3V

STRAIN GUAGE

LOAD CELL

300Ω/30mV FS

• USES ONE MORE WIRE THAN LOAD CELL ITSELF

• TWO MINI-DIPs COULD BE MOUNTED INSIDE
LOAD CELL FOR DIGITAL OUTPUT TRANSDUCER

• ELECTRONIC OFFSET AND GAIN TRIMS RELAX
MECHANICAL SPECS FOR GUAGE FACTOR AND OFFSET

• LOW LEVEL CELL OUTPUT IS CONVERTED IMMEDIATELY
FOR HIGH NOISE IMMUNITY

10V

Zero-Shift and Span Adjust: 2V - VIN - 5V

330Ω

6.8kΩ

1kΩ

GAIN

1.3kΩ
10kΩ 1MΩ

1MΩ

+
–

DUAL

+
–

DUAL

20kΩ

10kΩ
OFFSET

20kΩ

5.1V

10V

V

–IN

+IN

REF/2

V

CC

ML2280

GND

CLK

CS

DO

Digital Load Cell

17

ML2280, ML2283

APPLICATIONS (Continued)

START

ML2280

+

V

IN

V

–

IN

CLK

CS

LS193

LOAD

A5VBCD

CLK

COUNT

DOWN

B0

SRQ

DQ

Q

DQ

Q

DQ

Q

Sampling Rate 111kHz, Data Rate 1.33MHz

TMS320

SERIES

DSP

FSR
CLK

DRDO

CLK

START

CS

FSR

DO

1

234567891011121314

HI-Z HI-Z

D7 D6 D5 D4 D3 D2 D1 D0

Interfacing ML2280 to TMS320 Series

18

PHYSICAL DIMMENSIONS inches (millimeters)

Package: P08

8-Pin PDIP

0.365 - 0.385
(9.27 - 9.77)

0.055 - 0.065
(1.39 - 1.65)

8

ML2280, ML2283

0.020 MIN
(0.51 MIN)
(4 PLACES)

0.170 MAX
(4.32 MAX)

0.125 MIN
(3.18 MIN)

8

PIN 1 ID

1

0.016 - 0.020
(0.40 - 0.51)

0.189 - 0.199
(4.80 - 5.06)

0.100 BSC

(2.54 BSC)

SEATING PLANE

0.240 - 0.260
(6.09 - 6.60)

0.015 MIN
(0.38 MIN)

Package: S08

8-Pin SOIC

0.299 - 0.335
(7.59 - 8.50)

0º - 15º

0.008 - 0.012
(0.20 - 0.31)

0.017 - 0.027
(0.43 - 0.69)

(4 PLACES)

0.055 - 0.061

(1.40 - 1.55)

PIN 1 ID

1

0.050 BSC

(1.27 BSC)

0.012 - 0.020
(0.30 - 0.51)

SEATING PLANE

0.148 - 0.158
(3.76 - 4.01)

0.059 - 0.069
(1.49 - 1.75)

0.228 - 0.244
(5.79 - 6.20)

0.004 - 0.010
(0.10 - 0.26)

0º - 8º

0.015 - 0.035
(0.38 - 0.89)

0.006 - 0.010
(0.15 - 0.26)

19

ML2280, ML2283

PHYSICAL DIMMENSIONS inches (millimeters)

Package: P14

14-Pin PDIP

0.740 - 0.760

(18.79 - 19.31)

14

0.070 MIN
(1.77 MIN)
(4 PLACES)

0.170 MAX
(4.32 MAX)

0.125 MIN

(3.18 MIN)

PIN 1 ID

1

0.050 - 0.065
(1.27 - 1.65)

0.016 - 0.022
(0.40 - 0.56)

0.240 - 0.260
(6.09 - 6.61)

0.100 BSC
(2.54 BSC)

0.015 MIN
(0.38 MIN)

SEATING PLANE

0.295 - 0.325
(7.49 - 8.25)

0º - 15º

0.008 - 0.012
(0.20 - 0.31)

ORDERING INFORMATION

ALTERNATE TOTAL TEMPERATURE

PART NUMBER PART NUMBER UNADJUSTED ERROR RANGE PACKAGE

SINGLE ANALOG INPUT, 8-PIN PACKAGE

ML2280BIP (Obs) –40°C to 85°C 8-Pin DIP (P08)
ML2280BIS (Obs)

±1/2 LSB

–40°C to 85°C 8-Pin SOIC (S08)
ML2280BCP (Obs) 0°C to 70°C 8-Pin DIP (P08)
ML2280BCS (Obs) 0°C to 70°C 8-Pin SOIC (S08)
ML2280CIP (Obs) –40°C to 85°C 8-Pin DIP (P08)
ML2280CIS (Obs)
ML2280CCP (Obs) 0°C to 70°C 8-Pin DIP (P08)

±1 LSB

–40°C to 85°CQ 8-Pin SOIC (S08)

ML2280CCS (Obs) 0°C to 70°C 8-Pin SOIC (S08)

TWO ANALOG INPUTS, 14-PIN PACKAGE

ML2283BIP (Obs) ADC0833CCN
ML2283BCP (Obs) ADC0833BCN 0°C to 70°C 14-Pin DIP (P014)
ML2283CIP (Obs) ADC0833BCN

ML2283CCP (EOL) ADC0833CCN 0°C to 70°C 14-Pin DIP (P014)

© Micro Linear 1997 is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.

±1/2 LSB

±1 LSB

20

–40°C to 85°C 14-Pin DIP (P014)

–40°C to 85°C 14-Pin DIP (S014)

2092 Concourse Drive

San Jose, CA 95131

Tel: [phone]

Fax: [phone]

DS2280_83-01