Page 1
March 1997
ML2036*
Serial Input Programmable Sine Wave Generator
with Digital Gain Control
GENERAL DESCRIPTION
The ML2036 is a monolithic sine wave generator whose
FEATURES
■ Programmable output frequency - DC to 50kHz
output is programmable from DC to 50kHz. No external
components are required. The frequency of the sinewave
■ Low gain error and total harmonic distortion
output is derived from either an external crystal or clock
input, providing a stable and accurate frequency
reference. The frequency is programmed by a 16-bit serial
■ 3-wire SPI compatible serial microprocessor interface
with double buffered data latch
data word.
■ Fully integrated solution - no external components
The ML2036 provides for a V
±V
REF
or ±V
/2. Also included with the ML2036 is an
REF
inhibit function which allows the sinewave output to be
held at zero volts after completing the last half cycle of the
amplitude of either
OUT
required
■ Frequency resolution of 1.5Hz (±0.75Hz) with a
12MHz clock input
sine wave in progress. Two digital clock outputs are
provided to drive other devices with one half or one eighth
■ Onboard 3 to 12MHz crystal oscillator
of the input clock frequency.
■ Clock outputs of 1/2 or 1/8 of the input clock frequency
The ML2036 is intended for telecommunications and
modem applications that need low cost and accurate
■ Synchronous or asynchronous data loading capability
generation of precise test tones, call progress tones, and
signaling tones.
■ Compatible with ML2031 and ML2032 tone detectors
and ML2004 logarithmic gain/attenuator
BLOCK DIAGRAM (Pin Configuration Shown for 14-Pin PDIP Version)
CLK IN
14
CLK OUT 1
3
CLK OUT 2
4
LATI
4
SCK
2
SID
3
* Some Packages Are Obsolete
CRYSTAL
OSCILLATOR
÷2
÷2
÷2
9
V
REF
8-BIT
DAC
8
PHASE
ACCUMULATOR
& 512 POINT
SINE LOOK-UP
TABLE
16
16-BIT DATA LATCH
16
16-BIT SHIFT REGISTER
13
GAIN
SMOOTHING
5kΩ 5kΩ
FILTER
-
+
ZERO
DETECT
PDN-INH
2
V
OUT
V
CC
AGND
DGND
V
10
8
11
12
SS
1
1
Page 2
ML2036
PIN CONFIGURATION
ML2036
14-Pin PDIP (P14)
V
PDN-INH
CLK OUT 1
CLK OUT 2
SCK
SID
LATI
SS
1
2
3
4
5
6
7
TOP VIEW
14
13
12
11
10
9
8
CLK IN
GAIN
DGND
AGND
V
OUT
V
REF
V
CC
PDN-INH
CLK OUT 1
CLK OUT 2
PIN DESCRIPTION (Pin Number in Parentheses is for SOIC Version)
PIN NAME FUNCTION
1 (2) V
SS
Negative supply (-5V).
PIN NAME FUNCTION
8 (9) V
ML2036
16-Pin Wide SOIC (S16W)
NC
V
SCK
SID
LATI
CC
1
2
SS
3
4
5
6
7
8
TOP VIEW
Positive supply (5V).
16
15
14
13
12
11
10
CLK IN
GAIN
NC
DGND
AGND
V
OUT
V
REF
9
V
CC
2 (3) PDN-INH Three level input which controls
the inhibit and power down
modes. Current source pull-up to
VCC.
3 (4) CLK OUT 1 Digital clock output from the
internal clock generator that can
drive other devices at f
f
/2.
CLK IN
CLK OUT 1
4 (5) CLK OUT 2 Digital clock output from the
internal clock generator that can
drive other devices at f
f
/8.
CLK IN
CLK OUT 2
5 (6) SCK Serial clock. Digital input which
clocks in serial data on its rising
edges.
6 (7) SID Serial input data which programs
the frequency of V
OUT
.
7 (8) LATI Digital input which latches serial
data into the internal data latch on
falling edges.
=
=
9 (10) V
REF
Reference input. The voltage on
this pin determines the peak-topeak swing of V
OUT
. V
REF
can be
tied to VCC.
10 (11) V
OUT
Analog output.
11 (12) AGND Analog ground. All analog inputs
and outputs are referenced to this
point.
12 (13) DGND Digital ground. All digital inputs
and outputs are referenced to this
point.
13 (15) GAIN Sets V
or V
peak amplitude to V
OUT
/2. Current source pull-
REF
REF
down to DGND.
14 (16) CLK IN Clock input. The internal clock can
be generated by tying a 3 to
12MHz crystal from this pin to
DGND, or by applying a digital
clock signal directly to the pin.
2
Page 3
ABSOLUTE MAXIMUM RATINGS
ML2036
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
Thermal Resistance (qJA)
14-Pin PDIP ..................................................... 88ºC/W
16-Pin Wide SOIC .......................................... 105ºC/W
device operation is not implied.
V
.............................................................................................. 6.5V
CC
V
............................................................................................. -6.5V
SS
V
.................................................... V
OUT
- 0.3V to VCC + 0.3V
SS
Voltage on any other pin ........ GND - 0.3V to VCC + 0.3V
Input Current ........................................................±25mA
Junction Temperature .............................................. 150ºC
Storage Temperature Range...................... –65ºC to 150ºC
OPERATING CONDITIONS
Temperature Range
ML2036CX................................................. 0ºC to 70ºC
ML2036IX ............................................... -40ºC to 85ºC
VCC Range ...................................................4.5V to 5.5V
VSS Range ................................................. -4.5V to -5.5V
Lead Temperature (Soldering, 10 sec) ...................... 260ºC
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 4.5V to 5.5V, VSS = -4.5V to -5.5V, V
CL = 100pF, RL = 1kW, TA = Operating Temperature Range (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
OUTPUT
HD Harmonic Distortion (Note 2) 20Hz to 5kHz -45 dB
(2nd and 3rd Harmonic) 5kHz to 50kHz -40 dB
= 2.5V to VCC, CLK IN = 12.352MHz,
REF
SND Signal to Noise + Distortion (Note 2) 200Hz to 3.4kHz, -45 dB
f
BW = 200Hz to 4kHz
OUT
20Hz to 50kHz, -40 dB
f
BW = 20 Hz to 150kHz
OUT
V
ICN Idle Channel Noise Power Down Mode, Cmsg Weighted -20 0 dBrnc
PSRR Power Supply Rejection Ratio 200mV
V
V
R
OSCILLATOR
Gain Error (Note 2) 20Hz < f
GN
5kHz < f
Power Down Mode, 1kHz 50 nV/ÖHz
Inhibit Mode, 1kHz 500 nV/ÖHz
Sine, Measured on V
V
OS
P-P
REF
Offset Voltage (Note 3) ±(2.5+V
OUT
Peak-to-Peak Output Voltage (Note 2) GAIN = V
GAIN = DGND ±V
V
Swing GAIN = V
OUT
Reference Input Resistance 1 6 MW
< 5kHz ±0.15 dB
OUT
< 50kHz ±0.3 dB
OUT
, 0 - 10kHz V
P-P
OUT
CC
CC
CC
V
SS
±V
REF
/2 V
REF
VSS + 1.5 VCC -1.5 V
-40 dB
-40 dB
P-P
100
) V
V
VIL CLK CLK IN Input Low Voltage 1.5 V
VIH CLK CLK IN Input High Voltage 3.5 V
IIL CLK CLK IN Input Low Current -250 µA
IIH CLK CLK IN Input High Current 250 µA
CIN CLK CLK IN Input Capacitance 12 pF
3
Page 4
ML2036
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
OSCILLATOR (Continued)
t
CKI
CLK IN On/Off Period tR = tF = 10ns, 2.5V Midpoint 30 ns
CLK OUT 1/CLK IN Frequency Ratio See Figure 2 0.49 0.51
CLK OUT 2/CLK IN Frequency Ratio See Figure 2 0.122 0.128
t1R, t
CLK OUT 1, CLK OUT 2 Rise Time CL = 40pF, 10% to 90% 20 ns
2R
CL = 100pF, 0.8V to 2.0V Transition 20 ns
t1F, t
CLK OUT 1, CLK OUT 2 Fall Time CL = 40pF, 90% to 10% 20 ns
2F
CL = 100pF, 2.0V to 0.8V Transition 20 ns
LOGIC
V
V
V
V
V
IIL-P
IIH-GAIN GAIN Input High Current GAIN = V
Input Low Voltage (LATI, SCK, SID, GAIN) 0.8 V
IL
Input High Voltage (LATI, SCK, SID, GAIN) 2.0 V
IH
Input Low Voltage - PDN-INH -0.5 0.8 V
I1
Inhibit Stage Voltage - PDN-INH VSS + 0.5 V
I2
Input High Voltage - PDN-INH 2.0 V
I3
DNPDN
-INH Input Low Current PDN-INH = 0V -70 -20 -5 µA
CC
52070µA
IILInput Low Current (LATI, SCK, SID, GAIN) VIN = 0V -1 µA
I
Input High Current (LATI, SCK, SID, GAIN) VIN = V
IH
CC
1µA
CINInput Capacitance 5pF
V
V
OH
t
SCK
t
DS
t
DH
t
LPW
t
LH
t
Output Low Voltage IOL = -2mA 0.4 V
OL
Output High Voltage IOH = 2mA 4.0 V
Serial Clock On/Off Period 100 ns
SID Data Setup Time 50 ns
SID Data Hold Time 50 ns
LATI Pulse Width 50 ns
LATI Hold Time 50 ns
LATI Setup Time 50 ns
LS
SUPPLY
I
CC
VCC Current No Load, VCC = V
= 5.5V 5.5 mA
REF
No Load, Power Down Mode 2 mA
I
VSS Current No Load, VCC = V
SS
= 5.5V, -3.5 mA
REF
VSS = -5.5V
No Load, Power Down Mode -100 µA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Note 2: Maximum peak-to-peak voltage for the output sine wave is: V
Note 3: Offset voltage is a function of the peak-to-peak output voltage. For example, if V
OUT(P-P)
£ (125kV x Hz)/f
OUT(P-P)
. For example, at 50kHz, the maximum output voltage swing is 2.5V
OUT
= 2.5V, VOS = ±50mV max.
P-P
.
4
Page 5
CLK
ML2036
t
CKItCKI
CLK IN
t
t
SCK
SCK
SCK
t
DStDH
SID
t
t
LS
LATI
t
LPW
Figure 1. Serial Interface Timing.
f
CLKIN
IN
1
f
CLK
LH
t
1R
t
1F
CLK
CLK
OUT
OUT
1
2
f
CLK
2
t
2F
f
PARAMETERS REFERRED TO 1.4V MIDPOINT
CLK
t
2R
Figure 2. Digital Clock Output Timing.
100
75
50
25
0
-25
INPUT CURRENT (µA)
-50
-75
-100
01
INPUT VOLTAGE (V)
2
3
54
Figure 3. CLK IN Input Current vs. Input Voltage.
5
Page 6
ML2036
PHASE ACCUMULATOR
CLK
IN
BINARY
CRYSTAL
OSCILLATOR
÷4
SID
LATI
f
REF
LEAST
SIGNIFICANT
(12 BITS)
PHASE SAMPLES
(7 BITS)
16-BIT
SHIFT REGISTER
(16 BITS)
• • •
16-BIT
DATA LATCH
(16 BITS)
• • •
A16A
0
21-BIT
–
–
ADDER
A20A
15
SUM (21 BITS)
• • •
21-BIT
LATCH
Q
0
••••••
QUADRANT
COMPLEMENTER
• • •
(7 BITS)
• • •
B0–B
20
Q
20
SIGN BIT
QUADRANT
BIT
INPUT TO
QUADRANT
COMPLEMENTOR
INPUT TO
SIGN
BIT
ROM
T =
1
f
REF
f
REF
DIGITAL-TO-ANALOG
READ-ONLY
MEMORY
X 7)
(128
• • •
(7 BITS)
SIGN
COMPLEMENTOR
• • •
(7 BITS)
OUTPUT
LATCH
• • •
(7BITS)
8-BIT
CONVERTER
LOW-PASS
FILTER
SINEWAVE
OUTPUT
SIGN
BIT
SIGN
BIT
INPUT TO SIGN
COMPLEMENTOR
INPUT TO
OUTPUT LATCH
INPUT TO D/A
CONVERTER
PICTORIAL
PRESENTATION
OF DIGITAL DATA
INPUT TO
LOW-PASS
FILTER
(ANALOG
SIGNAL)
OUTPUT OF
LOW-PASS
FILTER
(ANALOG
SIGNAL)
Figure 4. Detailed Block Diagram of the ML2036.
6
Page 7
FUNCTIONAL DESCRIPTION
ML2036
The ML2035 is composed of a programmable frequency
generator, a sine wave generator, a crystal oscillator, and a
serial digital interface. The ML2036 frequency and sine
wave generator functional block diagram is shown in
Figure 4.
PROGRAMMABLE FREQUENCY GENERATOR
The programmable frequency generator produces a digital
output whose frequency is determined by a 16-bit digital
word.
The frequency generator is composed of a phase
accumulator which is clocked at f
stored in the data latch is added to the phase accumulator
every 4 cycles of CLK IN. The frequency of the analog
output is equal to the rate at which the accumulator
overflows and is given by the equation:
fDD
×−15 0
05
23
2
f
CLKIN
23
2
= 12.352MHz, Df
DEC
MIN
MIN
CLK IN
=
CLKIN
=
f
OUT
The frequency resolution and the minimum frequency are
the same and is given by the following equation:
∆f
When f
Lower frequencies are obtained by using a lower input
clock frequency.
Due to the phase quantization nature of the frequency
generator, spurious tones can be present in the output
range of –55dB relative to fundamental. The energy from
these tones is included in the signal to noise + distortion
specification. The frequency of these tones can be very
close to the fundamental. Therefore, it is not practical to
filter them out.
SINE WAVE GENERATOR
The sine wave generator is composed of a sine look-up
table, a DAC, and an output smoothing filter. The sine
look-up table is addressed by the phase accumulator. The
DAC is driven by the output of the look-up table and
generates a staircase representation of a sine wave.
/4. The value
CLK IN
= 1.5Hz (±0.75Hz).
(1)
(2)
The ML2036 has a V
generated from an external voltage. With the GAIN input
equal to a logic "1", the sine wave peak-to-peak voltage is
equal to ±V
peak voltage is ±V
voltage swing is limited to no closer than 1.5V to either
rail. This means that to avoid clipping, V
tied to VCC when GAIN is a logic "0". The sinewave output
is referenced to AGND.
The analog section is designed to operate over a range
from DC to 50kHz. Due to slew rate limitations, the peakto-peak output voltage must be limited to V
(125kV x Hz)/f
be limited to 2.5V
and swing to within 1.5V of VCC and VSS, provided the
slew rate limitations mentioned above are not exceeded.
The output offset voltage, VOS, is a function of the peak-topeak output voltage and is specified as:
V
OS MAX
For example, if V
VmV
OS MAX
CRYSTAL OSCILLATOR
The crystal oscillator generates an accurate reference
clock for the programmable frequency generator. The
internal clock can be generated with a crystal or external
clock.
If a crystal is used, it must be placed between CLK IN and
DGND of the ML2036. An on-chip crystal oscillator will
then generate the internal clock. No other external
capacitors or components are required. The crystal should
be a parallel-resonant type with a frequency between
3MHz to 12.4MHz. It should be placed physically as close
as possible to the CLK IN and DGND.
An external clock can drive CLK IN directly if desired. The
frequency of this clock can be anywhere between 0 and
12MHz.
; with the GAIN equal to a logic "0", the
REF
OUT
=±
05
=±
05
input that can be tied to VCC or
REF
/2. However, the overall output
REF
can only be
REF
. For example, an output at 50kHz must
. V
P-P
25
.
OUT(P-P)
25 25
..
100
can drive a 1kW, 100pF load
OUT
V
+
100
+
OUT P P
= 2.5V:
05
=±
−
50
OUT(P-P)
£
(3)
The output filter smoothes the analog output by removing
the high frequency sampling components. The resultant
voltage on V
harmonic distortion components at least 45dB below the
fundamental.
SCK
SID
LATI
is a sinusoid with the second and third
OUT
Figure 5. Serial Interface Timing.
1514131211109876543210
7
Page 8
ML2036
FUNCTIONAL DESCRIPTION (Continued)
The crystal must have the following characteristics:
1. Parallel resonant type
2. Frequency: 3MHz to 12.4MHz
3. Maximum equivalent series resistance of 15W at a
drive levels of 1µW to 200µW, and 30W at drive levels
of 10nW to 1µW
4. Typical load capacitance: 18pF
5. Maximum case capacitance: 7pF
The frequency of oscillation will be a function of the
crystal parameters and PC board capacitance. Crystals that
meet these requirements at 12.352000MHz are M-tron
3709-010 12.352 for 0ºC to 70ºC and 3709-020 12.352
for -40ºC to 85ºC operation.
The ML2036 has two clock outputs that can be used to
drive other external devices. The CLK OUT 1 output is a
buffered output from the oscillator divided by 2. The
CLK OUT 2 output is a buffered output from the oscillator
divided by 8.
SERIAL DIGITAL INTERFACE
The digital interface consists of a shift register and data
latch. The serial 16-bit data word on SID is clocked into a
16-bit shift register on rising edges of the serial shift clock,
SCK. The LSB should be shifted in first and the MSB last as
shown in Figure 4. The data that has been shifted into the
shift register is loaded into a 16-bit data latch on the falling
edge of LATI. To insure that true data is loaded into the
data latch from the shift register, LATI falling edge should
occur when SCK is low, as shown in figure 1. LATI should
be low while shifting data into the shift register to avoid
inadvertently entering the power down mode. Note that all
data is entered and latched on the edges, not levels, of
SCK and LATI.
INHIBIT AND POWER DOWN MODES
The ML2036 has an inhibit mode and a power down
mode which are controlled by the three-level PDN–INH
input as described in Table 1. If a logic "1", (VI3) is applied
to the PDN–INH pin, the power down mode is entered by
entering all zeros in the shift register and applying a logic
"1" to LATI and holding it high. A zero data detect circuit
detects when all bits in the shift register are zeros. In this
state, the power consumption is reduced to 11.5mW max,
and V
10kW to AGND. CLK IN can be left active or removed
during power down mode. Also, the ML2036 can be
placed in the power down mode by applying a logic “0”
to the PDN–INH pin, regardless of the contents of the shift
register and the state of LATI.
If VSS to VSS + 0.5V (VI2) is applied to the PDN–INH pin,
the inhibit mode is entered by shifting all zeros into the
shift register and applying a logic “1” to the LATI pin.
Once the inhibit mode is entered V
last half cycle of the sinewave and then be held at
approximately VOS, such that no voltage step occurs, as
shown in Figure 6.
POWER SUPPLIES
The analog circuits in ML2036 are powered from VCC to
VSS and are referenced to AGND. The digital circuits in the
device are powered from VCC to DGND. It is
recommended that AGND and DGND be connected
together close to the device, and have a good connection
back to the power source.
It is recommended that the power supplies to the device
should be bypassed by placing decoupling capacitors from
VCC to AGND and VSS to AGND as physically close to the
device as possible.
goes to 0V as shown in Figure 6 and appears as
OUT
will complete the
OUT
8
Page 9
PDN–INH PDN–INH DATA IN
MODE PIN SHIFT REG. LATI SINE WAVE OUTPUT
(1)
P
DN
VI1, Logic "0" X X V
OUT
(10kW to AGND)
Inhibit V
, Inhibit State All 0‘s Logic "1" V
I2
goes to approximately V
OUT
Voltage, VSS to at the next VOS crossing
VSS + 0.5V (See Figure 6)
(1)
P
DN
VI3, Logic "1" All 0‘s Logic "1" V
OUT
(10kW to AGND)
Note 1: In the power down mode, the oscillator, CLK OUT 1 and CLK OUT 2, shift register, and data latch are all functional.
Table 1. Three Level PDN-INH Functions.
ML2036
= 0V
OS
= 0V
POWER DOWN MODE
INHIBIT MODE
0V
0 V
SCK
SID
LATI
V
OS
V
V
OS
0123456789101112131415
X
|V
|V
X
X
| =
| ≤
V
PEAK
256
V
PEAK
256
FOR f
, FOR f
+ V
OUT
>
PEAK
OUT
SIN
f
CLK
2048
f
CLK
≤
2048
OUT
π
+
512
8 π f
f
CLK
Figure 6. Power Down and Inhibit Mode Waveforms.
9
Page 10
ML2036
TYPICAL APPLICATIONS
RECEIVE
LINE
INTERFACE
TRANSMIT
LINE
INTERFACE
ML2003
ML2031
ML2032
TONE
DETECTOR
ML2004
ML2008
ML2009
ATTENUATION
/GAIN
ML2003
ML2004
ML2008
ML2009
ATTENUATION
/GAIN
µP
ML2020
ML2021
LINE
EQUALIZER
ML2036
TONE
GENERATOR
Figure 7. 4-Wire Termination Equipment.
LOOPBACK
RELAY
5V
ML2036
V
GAIN
CC
0.1µF
GND
V
OUT
–5V
0.1µF
V
V
SS
REF
2.5V
REF
Figure 8. Sine Wave Generator with ±2.5V
P-P
.
10
Page 11
PHYSICAL DIMENSIONS inches (millimeters)
Package: P14
14-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
14
ML2036
0.070 MIN
(1.77 MIN)
(4 PLACES)
0.170 MAX
(4.32 MAX)
16
0.125 MIN
(3.18 MIN)
0.400 - 0.414
(10.16 - 10.52)
PIN 1 ID
1
0.050 - 0.065
(1.27 - 1.65)
0.016 - 0.022
(0.40 - 0.56)
0.240 - 0.260
(6.09 - 6.61)
0.100 BSC
(2.54 BSC)
SEATING PLANE
Package: S16W
16-Pin Wide SOIC
0.015 MIN
(0.38 MIN)
0.295 - 0.325
(7.49 - 8.25)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.090 - 0.094
(2.28 - 2.39)
1
PIN 1 ID
0.050 BSC
(1.27 BSC)
0.012 - 0.020
(0.30 - 0.51)
0.291 - 0.301
(7.39 - 7.65)
0.095 - 0.107
(2.41 - 2.72)
SEATING PLANE
0.398 - 0.412
(10.11 - 10.47)
0.005 - 0.013
(0.13 - 0.33)
0º - 8º
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
11
Page 12
ML2036
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE
ML2036CP 0ºC to 70ºC 14-Pin PDIP (P14)
ML2036CS 0ºC to 70ºC 16-Pin Wide SOIC (S16W)
ML2036IP -40ºC to 85ºC 14-Pin PDIP (P14)
ML2036IS (Obsolete) -40ºC to 85ºC 16-Pin Wide SOIC (S16W)
© Micro Linear 1997. is a registered trademark of Micro Linear Corporation.
Products described in this document may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no
responsibility or liability for use of any application herein. The customer is urged to consult with appropriate
legal counsel before deciding on a particular application.
12
2092 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-0295
DS2036-01
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