Page 1
February 1997
ML2035
Serial Input Programmable Sine Wave Generator
GENERAL DESCRIPTION
The ML2035 is a monolithic sinewave generator whose
output is programmable from DC to 25kHz. No external
components are required. The frequency of the sinewave
output is derived from either an external crystal or clock
input, providing a stable and accurate frequency
reference. The frequency is programmed by a 16-bit serial
data word. The ML2035 has a V
OUT
amplitude of ±VCC/2.
The ML2035 is intended for telecommunications and
modem applications that need low cost and accurate
generation of precise test tones, call progress tones, and
signaling tones.
BLOCK DIAGRAM
FEATURES
■ Programmable output frequency - DC to 25kHz
■ Low gain error and total harmonic distortion
■ 3-wire SPI compatible serial microprocessor interface
with double buffered data latch
■ Fully integrated solution - no external components
required
■ Frequency resolution of 1.5Hz (±0.75Hz) with a
12MHz clock input
■ Onboard 3 to 12MHz crystal oscillator
■ Synchronous or asynchronous data loading capability
■ Compatible with ML2031 and ML2032 tone detectors
and ML2004 logarithmic gain/attenuator
V
OUT
LATI
SCK
SID
4
2
3
6
8-BIT
DAC
PHASE
ACCUMULATOR
& 512 POINT
SINE LOOK-UP
TABLE
8
16
16
16-BIT DATA LATCH
16-BIT SHIFT REGISTER
CRYSTAL
OSCILLATOR
÷4
CLK IN
8
GND
7
V
CC
5
V
SS
1
-
+
5kΩ 5kΩ
ZERO
DETECT
SMOOTHING
FILTER
REV. 1.0 10/10/2000
Page 2
ML2035
2 REV. 1.0 10/10/2000
PIN CONFIGURATION
PIN DESCRIPTION
PIN NAME FUNCTION
1V
SS
Negative supply (-5V).
2 SCK Serial clock. Digital input which
clocks in serial data on its rising
edges.
3 SID Serial input data which programs the
frequency of V
OUT
.
4 LATI Digital input which latches serial data
into the internal data latch on falling
edges.
PIN NAME FUNCTION
5V
CC
Positive supply (5V).
6V
OUT
Analog output. V
OUT
swing is ±VCC/2.
7 GND Ground. All inputs and outputs are
referenced to this point.
8 CLK IN Clock input. The internal clock can be
generated by tying a 3 to 12MHz
crystal from this pin to GND, or
applying a digital clock signal directly
to the pin.
1
2
3
4
8
7
6
5
V
SS
SCK
SID
LATI
CLK IN
GND
V
OUT
V
CC
TOP VIEW
ML2035
8-Pin PDIP (P08)
Page 3
ML2035
REV. 1.0 10/10/2000 3
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 4.5V to 5.5V, VSS = -4.5V to -5.5V, CLK IN = 12.352MHz, CL = 100pF, RL = 1kΩ,
T
A
= Operating Temperature Range (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
OUTPUT
HD Harmonic Distortion 20Hz to 5kHz -45 dB
(2nd and 3rd Harmonic) 5kHz to 25kHz -40 dB
SND Signal to Noise + Distortion 200Hz to 3.4kHz, -45 dB
f
OUT
BW = 20Hz to 4kHz
20Hz to 25kHz, -40 dB
f
OUT
BW = 20 Hz to 75kHz
V
GN
Gain Error 20Hz < f
OUT
< 5kHz ±0.15 dB
5kHz < f
OUT
< 25kHz ±0.3 dB
ICN Idle Channel Noise Power Down Mode, Cmsg Weighted -20 0 dBrnc
Power Down Mode, 1kHz 50 nV/ Hz
PSRR Power Supply Rejection Ratio 200mV
P-P
, 0 - 10kHz V
CC
-40 dB
Sine, Measured on V
OUT
V
SS
-40 dB
V
OS
V
OUT
Offset Voltage ±75 mV
V
P-P
Peak-to-Peak Output Voltage ±VCC/2 V
OSCILLATOR
VIL CLK CLK IN Input Low Voltage 1.5 V
VIH CLK CLK IN Input High Voltage 3.5 V
IIL CLK CLK IN Input Low Current -250 µA
IIH CLK CLK IN Input High Current 250 µA
CIN CLK CLK IN Input Capacitance 12 pF
t
CKI
CLK IN On/Off Period tR = tF = 10ns, 2.5V Midpoint 30 ns
LOGIC (LATI, SID, SCK)
V
IL
Input Low Voltage 0.8 V
V
IH
Input High Voltage 2.0 V
I
IL
Input Low Current VIN = 0V -1 µA
I
IH
Input High Current VIN = V
CC
1 µA
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
V
CC
.............................................................................................
6.5V
V
SS
............................................................................................
-6.5V
V
OUT
...................................................
VSS - 0.3V to VCC + 0.3V
Voltage on any other pin ........ GND - 0.3V to V
CC
+ 0.3V
Input Current........................................................ ±25mA
Junction Temperature ............................................. 150ºC
Storage Temperature Range ......................–65ºC to 150ºC
Lead Temperature (Soldering, 10 sec) ..................... 260ºC
Thermal Resistance (θ
JA
).....................................110ºC/W
OPERATING CONDITIONS
Temperature Range
ML2035CP .................................................0ºC to 70ºC
ML2035IP ............................................... -40ºC to 85ºC
V
CC
Range ................................................... 4.5V to 5.5V
V
SS
Range ..................................................-4.5V to -5.5V
Page 4
ML2035
4 REV. 1.0 10/10/2000
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC (Continued)
V
OL
Output Low Voltage IOL = -2mA 0.4 V
V
OH
Output High Voltage IOH = 2mA 4.0 V
t
SCK
Serial Clock On/Off Period 100 ns
t
DS
SID Data Setup Time 50 ns
t
DH
SID Data Hold Time 50 ns
t
LPW
LATI Pulse Width 50 ns
t
LH
LATI Hold Time 50 ns
t
LS
LATI Setup Time 50 ns
SUPPLY
I
CC
VCC Current No Load, VCC = 5.5V 5.5 mA
No Load, Power Down Mode 2 mA
I
SS
VSS Current No Load, VCC = 5.5V, VSS = -5.5V -3.5 mA
No Load, Power Down Mode -100 µA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Figure 1. Serial Interface Timing. Figure 2. CLK IN Input Current vs. Input Voltage.
100
75
50
25
0
-25
-50
-75
-100
INPUT CURRENT (µA)
INPUT VOLTAGE (V)
01
3
54
2
CLK IN
SCK
SID
LATI
t
LPW
t
LS
t
LH
t
DStDH
t
SCK
t
SCK
t
CKItCKI
Page 5
ML2035
REV. 1.0 10/10/2000 5
FUNCTIONAL DESCRIPTION
The ML2035 is composed of a programmable frequency
generator, a sine wave generator, a crystal oscillator, and a
serial digital interface. The ML2035 frequency and sine
wave generator functional block diagram is shown in
Figure 3.
PROGRAMMABLE FREQUENCY GENERATOR
The programmable frequency generator produces a digital
output whose frequency is determined by a 16-bit digital
word.
The frequency generator is composed of a phase
accumulator which is clocked at f
CLK IN
/4. The value
stored in the data latch is added to the phase accumulator
every 4 cycles of CLK IN. The frequency of the analog
output is equal to the rate at which the accumulator
overflows and is given by the equation:
(1)
The frequency resolution and the minimum frequency are
the same and is given by the following equation:
(2)
When f
CLK IN
= 12.352MHz, ∆f
MIN
= 1.5Hz (±0.75Hz).
Lower frequencies are obtained by using a lower input
clock frequency.
Due to the phase quantization nature of the frequency
generator, spurious tones can be present in the output
range of –55dB relative to fundamental. The energy from
these tones is included in the signal to noise + distortion
specification. The frequency of these tones can be very
close to the fundamental. Therefore, it is not practical to
filter them out.
SINEWAVE GENERATOR
The sinewave generator is composed of a sine look-up
table, a DAC, and an output smoothing filter. The sine
look-up table is addressed by the phase accumulator. The
DAC is driven by the output of the look-up table and
generates a staircase representation of a sine wave.
The output filter smoothes the analog output by removing
the high frequency sampling components. The resultant
voltage on V
OUT
is a sinusoid with the second and third
harmonic distortion components at least 45dB below the
fundamental.
The ML2035 provides a peak sinewave voltage of ±V
CC
/2,
referenced to GND.
The analog section is designed to operate over a range
from DC to 25kHz. Due to slew rate limitations, the peakto-peak output voltage must be limited to V
OUT(P-P)
≤
(125kV x Hz)/f
OUT
. Since the ML2035 peak-to-peak
output voltage is equal to V
CC
, the maximum output
frequency must be limited to 25kHz for V
CC
= 5V. V
OUT
can drive a 1kΩ, 100pF loads, provided the slew rate
limitations mentioned above are not exceeded.
The output offset voltage, V
OS
, is a function of the peak-
to-peak output voltage and is specified as:
(3)
For example, if V
OUT(P-P)
= 2.5V:
CRYSTAL OSCILLATOR
The crystal oscillator generates an accurate reference
clock for the programmable frequency generator. The
internal clock can be generated with a crystal or external
clock.
If a crystal is used, it must be placed between CLK IN and
GND of the ML2035. An on-chip crystal oscillator will
then generate the internal clock. No other external
capacitors or components are required. The crystal should
be a parallel-resonant type with a frequency between
3MHz to 12.4MHz. It should be placed physically as
close as possible to the CLK IN and GND.
An external clock can drive CLK IN directly if desired. The
frequency of this clock can be anywhere between 0 and
12MHz.
The crystal must have the following characteristics:
1. Parallel resonant type
2. Frequency: 3MHz to 12.4MHz
3. Maximum equivalent series resistance of 15Ω at a drive
levels of 1µW to 200µW, and 30Ω at drive levels of
10nW to 1µW
4. Typical load capacitance: 18pF
5. Maximum case capacitance: 7pF
The frequency of oscillation will be a function of the
crystal parameters and PC board capacitance. Crystals that
meet these requirements at 12.352000MHz are M-tron
3709-010 12.352 for 0ºC to 70ºC and 3709-020 12.352
for -40ºC to 85ºC operation.
f
f
CLKIN
× (D15–D0)
DEC
OUT
=
2
23
f
f
MIN
CLKIN
2
22
=
∆
Page 6
ML2035
6 REV. 1.0 10/10/2000
Figure 3. Detailed Block Diagram of the ML2035.
16-BIT
SHIFT REGISTER
16-BIT
DATA LATCH
21-BIT
ADDER
A16A
0
A20A
15
B0–B
20
–
–
21-BIT
LATCH
SUM (21 BITS)
Q
20
Q
0
BINARY
PHASE ACCUMULATOR
f
REF
QUADRANT
COMPLEMENTER
LEAST
SIGNIFICANT
(12 BITS)
PHASE SAMPLES
(7 BITS)
SIGN BIT
QUADRANT
BIT
(16 BITS)
• • •
• • •
(16 BITS)
• • •
• • •
••••••
INPUT TO
QUADRANT
COMPLEMENTOR
T =
1
f
REF
INPUT TO
ROM
PICTORIAL
PRESENTATION
OF DIGITAL DATA
INPUT TO SIGN
COMPLEMENTOR
SIGN
BIT
(7 BITS)
• • •
READ-ONLY
MEMORY
(128
X
7)
(7 BITS)
• • •
(7 BITS)
• • •
(7BITS)
• • •
SIGN
COMPLEMENTOR
OUTPUT
LATCH
8-BIT
DIGITAL-TO-ANALOG
CONVERTER
LOW-PASS
FILTER
SINEWAVE
OUTPUT
OUTPUT OF
LOW-PASS
FILTER
(ANALOG
SIGNAL)
INPUT TO
LOW-PASS
FILTER
(ANALOG
SIGNAL)
INPUT TO D/A
CONVERTER
INPUT TO
OUTPUT LATCH
SIGN
BIT
SIGN
BIT
f
REF
CLK IN
CRYSTAL
OSCILLATOR
÷4
LATI
SID
Page 7
ML2035
REV. 1.0 10/10/2000 7
FUNCTIONAL DESCRIPTION (Continued)
SERIAL DIGITAL INTERFACE
The digital interface consists of a shift register and data
latch. The serial 16-bit data word on SID is clocked into a
16-bit shift register on rising edges of the serial shift clock,
SCK. The LSB should be shifted in first and the MSB last as
shown in Figure 4. The data that has been shifted into the
shift register is loaded into a 16-bit data latch on the
falling edge of LATI. To insure that true data is loaded into
the data latch from the shift register, LATI falling edge
should occur when SCK is low, as shown in figure 1. LATI
should be low while shifting data into the shift register to
avoid inadvertently entering the power down mode. Note
that all data is entered and latched on the edges, not
levels, of SCK and LATI.
POWER DOWN MODE
The power down mode of the ML2035 can be selected by
entering all zeros in the shift register and applying a logic
“1” to LATI and holding it high. A zero data detect circuit
detects when all bits in the shift register are zeros. In this
state, the power consumption is reduced to 11.5mW max,
and V
OUT
goes to 0V as shown in Figure 5 and appears as
10kΩ to ground. The master clock, CLK IN, can be left
active or removed during power down mode.
Figure 4. Serial Interface Timing.
SCK
SID
LATI
1514131211109876543210
Figure 5. Power Down Mode Waveforms.
POWER SUPPLIES
The analog circuits in ML2035 are powered from V
CC
to
V
SS
and are referenced to GND. The digital circuits in the
device are powered from V
CC
to GND.
It is recommended that the power supplies to the device
should be bypassed by placing decoupling capacitors
from V
CC
to GND and VSS to GND as physically close to
the device as possible.
V
OS
0V
POWER DOWN MODE
SCK
SID
LATI
0123456789101112131415
Page 8
ML2035
8 REV. 1.0 10/10/2000
TYPICAL APPLICATIONS
RECEIVE
LINE
INTERFACE
ML2003
ML2004
ML2008
ML2009
ATTENUATION
/GAIN
ML2031
ML2032
TONE
DETECTOR
TRANSMIT
LINE
INTERFACE
ML2035
TONE
GENERATOR
LOOPBACK
RELAY
ML2020
ML2021
LINE
EQUALIZER
µP
ML2003
ML2004
ML2008
ML2009
ATTENUATION
/GAIN
Figure 6. 4-Wire Termination Equipment.
Figure 7. Sine Wave Ratiometric to
±V
CC
/2.
5V
–5V
ML2035
V
CC
GND
V
OUT
0.1µF
V
CC
/2
V
CC
/2
0 TO 25kHz SINEWAVE
0.1µF
V
SS
Page 9
ML2035
REV. 1.0 10/10/2000 9
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE
ML2035CP 0ºC to 70ºC 8-Pin PDIP (P08)
ML2035IP -40ºC to 85ºC 8-Pin PDIP (P08)
PHYSICAL DIMENSIONS inches (millimeters)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.60)
PIN 1 ID
0.299 - 0.335
(7.59 - 8.50)
0.365 - 0.385
(9.27 - 9.77)
0.016 - 0.020
(0.40 - 0.51)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.015 MIN
(0.38 MIN)
8
0º - 15º
1
0.055 - 0.065
(1.39 - 1.65)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.020 MIN
(0.51 MIN)
(4 PLACES)
Package: P08
8-Pin PDIP
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com © 2000 Fairchild Semiconductor Corporation
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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