The MK3754 is ICS/Microclock’s lowest cost, low
jitter, high performance 3.3 Volt VCXO and PLL
clock synthesizer designed to replace expensive
54 MHz VCXOs. The on-chip Voltage Controlled
Crystal Oscillator accepts a 0 to 3.3 V input voltage
to vary the output clocks by ±100 ppm. Using
ICS/Microclock’s patented VCXO and
analog/digital Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive external
13.5 MHz pullable crystal input to produce a
54 MHz output clock.
The MK3754A is a drop-in replacement to the
earlier MK3754S.
Low Cost 54 MHz 3.3 Volt VCXO
Features
• Packaged in 8 pin SOIC
• 3.3 V only operating voltage
• Uses an inexpensive 13.500 MHz external crystal
• On-chip VCXO (patented) with pull range of
200ppm (minimum)
• VCXO tuning voltage of 0 to 3.3 V
• 12mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• The A version is the latest, manufactured in a
smaller geometry process. The MK3754A gives a
wider pull range than the MK3754S, and so is
recommended for all new designs, and cost
Block Diagram
VIN
13.5 MHz
pullable
crystal
X1
X2
Voltage
Controlled
Crystal
Oscillator
reductions of existing designs.
PLL/Clock
Synthesis
Circuitry
Output
Buffer
54MHz
MDS 3754 D1Revision 060100 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
Page 2
MK3754
ICRO
C
LOCK
Low Cost 54 MHz 3.3 Volt VCXO
Pin Assignment
MK3754
X1
VDD
GND
18
2
3
4
X2
7
GND
6
CLKVIN
5
VDD
8 pin (150 mil) SOIC
Pin Descriptions
NumberName Description
1X1Crystal connection. Connect to a pullable 13.5 MHz crystal.
2VDDVDD. Connect to +3.3 V.
3VINVoltage input to VCXO. Zero to 3.3V analog input which controls the frequency of the VCXO.
4GNDConnect to ground.
5VDDVDD. Connect to +3.3 V.
6CLK54 MHz clock output.
7GNDConnect to ground.
8X2Crystal connection. Connect to a pullable 13.5 MHz crystal.
Pullable Crystal Specifications:
Correlation (load) Capacitance14 pF
C0/C1240 max
ESR35 Ω max
Operating Temperature0 to 70 °C
Initial Accuracy±20 ppm
Temperature plus Aging Stability±50 ppm
MDS 3754 D2Revision 060100 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
Page 3
MK3754
ABSOLUTE MAXIMUM RATINGS (note 1)
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With an ICS approved pullable crystal. The A version has a typical range of ±180 ppm.
ICRO
C
LOCK
Low Cost 54 MHz 3.3 Volt VCXO
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply voltage, VDDReferenced to GND7V
Inputs and Clock OutputsReferenced to GND-0.5VDD+0.5V
Ambient Operating Temperature070°C
Soldering TemperatureMax of 10 seconds260°C
Storage temperature-65150°C
Operating Voltage, VDD 3.153.45V
Output High Voltage, VOHIOH=-12mA2.4V
Output Low Voltage, VOLIOL=12mA0.4V
Output High Voltage, VOH, CMOS levelIOH=-4mAVDD-0.4V
Operating Supply Current, IDD No Load9mA
Short Circuit Current±50mA
VIN, VCXO control voltage03.3V
Input Crystal Frequency13.50000MHz
Output Clock Rise Time0.8 to 2.0V1.5ns
Output Clock Fall Time2.0 to 0.8V1.5ns
Output Clock Duty CycleAt 1.4V405060%
Maximum Absolute Jitter, short term100ps
54 MHz output pullability, note 20V ≤ VIN ≤ 3.3 V±100ppm
Notes:1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
External Components
The MK3754 requires a minimum number of external components for proper operation. A decoupling
capacitor of 0.01µF should be connected between VDD and GND on pins 2 and 4, as close to the
MK3754 as possible. A series termination resistor of 33 Ω may be used for the clock output. The input
crystal must be connected as close to the chip as possible. The input crystal should be a parallel mode,
pullable, AT cut, 13.5 MHz, with 14 pF load capacitance. Consult ICS for recommended suppliers.
IMPORTANT - read application note MAN05 before laying out the PCB.
MDS 3754 D3Revision 060100 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
Page 4
MK3754
Inches
Millimeters
ICRO
C
LOCK
Low Cost 54 MHz 3.3 Volt VCXO
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
CHANGE HISTORY
Version Date first publishedStatusComments
D6/01/00Added A version
C12/29/99PreliminaryAdded JEDEC dimensions. Changed VDD to ±5%. Added crystal specs.
B5/25/99PreliminaryUpdated specs for crystal capacitance, IDD, jitter.
A4/19/99PreliminaryOriginal
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 3754 D4Revision 060100 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com
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