The MK3720 is a low cost, low jitter, high
performance 3.3 Volt VCXO and PLL clock
synthesizer designed to replace expensive 13.5, 27,
or 54MHz VCXOs. The patented on-chip
Voltage Controlled Crystal Oscillator accepts a
0 to 3.3 V input voltage to cause the output clocks
to vary by ±100 ppm. Using our patented VCXO
and analog/digital Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive external
13.5 MHz pullable crystal input to produce output
clocks of 13.5 MHz, 27 MHz, and 54 MHz .
The MK3720A is a drop-in replacement to the
earlier MK3720S.
Block Diagram
Features
• Packaged in 8 pin SOIC
• 3.3 V only operating voltage
• Output clocks of 54, 27, and 13.5MHz
• Uses an inexpensive 13.500 MHz external crystal
• On-chip patented VCXO with pull range
of 200ppm (minimum)
• VCXO tuning voltage of 0 to 3.3 V
• 12 mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• The A version is the latest, manufactured in a smaller
geometry process. The MK3720A gives a wider pull
range than the MK3720S, and so is recommended
for all new designs, and cost reductions of existing
designs.
Output
VIN
13.5 MHz
pullable
crystal
MDS 3720 D1Revision 053100 Printed 11/16/00
Integrated Circuit Systems, Inc. •525 Race Street • San Jose • CA• 95126• (408)295-9800tel • www.icst.com
X1
X2
Voltage
Controlled
Crystal
Oscillator
PLL/Clock
Synthesis
Circuitry
Buffer
Output
Buffer
Output
Buffer
54 MHz Clock
27 MHz Clock
13.5 MHz Clock
Page 2
Pin Assignment
MK3720
27 MHz and 54 MHz 3.3 Volt VCXO
MK3720
X1
VDD27M
VIN
GND
18
2
3
4
X2
7
6
13.5M
5
54M
8 pin (150 mil) SOIC
Pin Descriptions
NumberName Description
1X1Crystal connection. Connect to a pullable 13.5 MHz crystal.
2VDDVDD. Connect to +3.3 V.
3VINVoltage input to VCXO. Zero to 3.3 V analog input which controls the frequency of the VCXO.
4GNDConnect to ground.
554M54 MHz VCXO clock output.
613.5M13.5 MHz VCXO clock output.
727M27 MHz VCXO clock output.
8X2Crystal connection. Connect to a pullable 13.5 MHz crystal.
Pullable Crystal Specifications:
Correlation (load) Capacitance14 pF
C0/C1240 max
ESR35 Ω max
Operating Temperature0 to 70 °C
Initial Accuracy±20 ppm
Temperature plus Aging Stability±50 ppm
MDS 3720 D2Revision 053100 Printed 11/16/00
Integrated Circuit Systems, Inc. •525 Race Street • San Jose • CA• 95126• (408)295-9800tel • www.icst.com
Page 3
MK3720
ABSOLUTE MAXIMUM RATINGS (note 1)
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With an ICS approved pullable crystal. The MK3720A has a typical pull range of ±180 ppm.
27 MHz and 54 MHz 3.3 Volt VCXO
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply voltage, VDDReferenced to GND7V
Inputs and Clock OutputsReferenced to GND-0.5VDD+0.5V
Ambient Operating Temperature070°C
Soldering TemperatureMax of 10 seconds260°C
Storage temperature-65150°C
Operating Voltage, VDD 3.153.45V
Output High Voltage, VOHIOH=-12mA2.4V
Output Low Voltage, VOLIOL=12mA0.4V
Output High Voltage, VOH, CMOS levelIOH=-4mAVDD-0.4V
Operating Supply Current, IDD No Load11mA
Short Circuit Current±50mA
VIN, VCXO control voltage03.3V
Input Crystal Frequency13.50000MHz
Output Clock Rise Time0.8 to 2.0V1.5ns
Output Clock Fall Time2.0 to 0.8V1.5ns
Output Clock Duty CycleAt 1.4V455055%
Maximum Absolute Jitter, short term100ps
Output pullability, note 20V ≤ VIN ≤ 3.3 V±100ppm
Notes:1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
External Components
The MK3720 requires a minimum number of external components for proper operation. A decoupling
capacitor of 0.01µF should be connected between VDD and GND on pins 2 and 4, as close to the
MK3720 as possible. A series termination resistor of 33 Ω may be used for the clock output. The input
crystal must be connected as close to the chip as possible. The input crystal should be a parallel mode,
pullable, AT cut, 13.5 MHz, with 14 pF load capacitance. Consult ICS for recommended suppliers.
IMPORTANT - read application note MAN05 before laying out the PCB.
MDS 3720 D3Revision 053100 Printed 11/16/00
Integrated Circuit Systems, Inc. •525 Race Street • San Jose • CA• 95126• (408)295-9800tel • www.icst.com
Page 4
27 MHz and 54 MHz 3.3 Volt VCXO
Inches
Millimeters
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
CHANGE HISTORY
Version Date first publishedStatusComments
D5/31/00Added A version
C12/29/99ReleasedChanged to JEDEC dimensions. Changed VDD to ±5%. Added Crystal specs.
B 5/25/99PreliminaryUpdated specs for crystal capacitance, IDD, jitter.
A 4/19/99PreliminaryOriginal
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize
or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 3720 D4Revision 053100 Printed 11/16/00
Integrated Circuit Systems, Inc. •525 Race Street • San Jose • CA• 95126• (408)295-9800tel • www.icst.com
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