Page 1
MIC59P50 Micrel
MIC59P50
8-Bit Parallel-Input Protected Latched Driver
General Description
The MIC59P50 parallel-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common CLEAR, STROBE, and OUTPUT ENABLE functions. Similar to the MIC5801, additional protection circuitry
supplied on this device includes thermal shutdown, under
voltage lockout (UVLO), and over-current shutdown.
The bipolar/MOS combination provides an extremely lowpower latch with maximum interface flexibility. The MIC59P50
has open-collector outputs capable of sinking 500mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V above V
(50V sustaining). The drivers can be operated with a split
supply, where the negative supply is down to –20V and may
be paralleled for higher load current capability.
With a 5V logic supply, the MIC59P50 will typically operate at
better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compatible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors.
Each of these eight outputs has an independent over-current
shutdown at 500 mA. Upon current shutdown, the affected
channel will turn OFF and the flag will go low until VDD is
cycled or the ENABLE/RESET pin is pulsed high. Current
pulses less than 2µs will not activate over-current shutdown.
Temperatures above 165°C will shut down the device and
activate the open collector FLAG output at pin 1. The UVLO
circuit disables the outputs at low VDD; hysteresis of 0.5V is
provided.
Features
• 4.4 MHz Minimum Data Input Rate
• High-Voltage, High-Current Outputs
• Per-Output Over-Current Shutdown (500mA Typical)
• Undervoltage Lockout
• Thermal Shutdown
• Output Fault Flag
• Output Transient Protection Diodes
• CMOS, PMOS, NMOS, and TTL Compatible Inputs
• Internal Pull-Down Resistors
• Low-Power CMOS Latches
• Single or Split Supply Operation
EE
Ordering Information
Part Number Temperature Range Package
MIC59P50BN –40°C to +85°C 24-Pin Plastic DIP*
MIC59P50BV –40°C to +85°C 28-Pin PLCC
MIC59P50BWM –40°C to +85°C 24-Pin Wide SOIC
* 300-mil “skinny DIP”
Functional Diagram
STROBE
V
DD
2.2R
+
–
1.25V
R
UVLO
IN
CLEAR
FLAG
THERMAL
SHUTDOWN
ENABLE/RESET
SRQ
Circuitry below dashed line is
included in each of the 8 channels.
I
SHUTDOWN
Pin Configuration
(DIP and SOIC)
I
1
FLAG
I
REF
–
+
R1
70k
COMMON
V
EE
I
OUT
R2
3k
/ N
OUTPUT
CLEAR
STROBE
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
V
2
3
4
5
6
7
8
9
10
11
12
EE
7-58 October 1998
THERMAL
SHUTDOWN
LATCHES
UVLO
LIMIT
24
V
SS
OUTPUT
23
ENABLE/RESET
22
V
DD
21
OUT 1
20
OUT 2
19
OUT 3
OUT 4
18
OUT 5
17
OUT 6
16
15
OUT 7
14
OUT 8
13
COMMON
Page 2
MIC59P50 Micrel
Absolute Maximum Ratings T
= +25°C
A
Output Voltage (VCE) ....................................................80V
Supply Voltage (VDD) ....................................................15V
(VDD – VEE) ...............................................................25V
Input Voltage (VIN) ............................... –0.3V to VDD+0.3V
Continuous Collector Current (IC) ............................500mA
Protected Current............................................1.5A, Note 1
Power Dissipation (PD)
Plastic DIP (N).........................................................2.4W
Derate above TA = +25°C ............................24mW/°C
PLCC (V).................................................................1.6W
Derate above TA = +25°C ............................16mW/°C
Wide SOIC (WM) ....................................................1.4W
Derate above TA = +25°C ............................14mW/°C
Operating Temperature (TA)
Plastic DIP (N), PLCC (V), SOIC (WM)..–40°C to +85°C
Storage Temperature (TS) .......................–65°C to +150°C
Junction Temperature (TJ) ...................................... +150°C
ESD ......................................................................... Note 2
Note 1: Each channel. VEE connection must be designed to minimize
Note 2: Devices are input-static protected but can be damage by
inductance and resistance.
extremely high static charges.
PLCC Pin Configuration
SS
EE
V
V
CLEAR
FLAG
2
28 27 26
1
MIC59P50BV
1615
14
EE
NC
NC
NC
V
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
STROBE
4
3
5
6
7
8
9
10
11
12 13
IN 8
Allowable Output Current
MIC59P50BN
450
DD
V
OE/RESET
18
17
OUT 8
COMMON
25
OUT 1
24
OUT 2
OUT 3
23
22
OUT 4
OUT 5
21
20
OUT 6
19
OUT 7
Typical Input
IN
Pin Description
Pin Name Description
1 FLAG Error Flag. Open Collector Output is Low upon Overcurrent Fault or
2 CLEAR Sets All Latches OFF (open).
3 STROBE Input Strobe Pin. Loads output latches when High.
4–11 INPUT Parallel Inputs, 1 through 8
12 V
13 COMMON Transient suppression diodes cathode common pin.
14–21 OUTPUT Parallel Outputs, 8 through 1.
22 V
23 OUTPUT ENABLE RESET Output Enable Reset. When Low, Outputs are active. When High, outputs
24 V
EE
DD
SS
400
350
V
DD
300
250
200
NUMBER OF OUTPUTS
150
CONDUCTING
SIMULTANEOUSLY
100
0102030405060708090100
ALLOWABLE COLLECTOR CURRENT IN mA AT 50°C
PERCENT DUTY CYCLE
4
5
6
7
8
1 or 2
3
7
Overtemperature Fault. OUTPUT ENABLE/RESET must be pulled high to
reset the flag and fault condition.
Output Ground (Substrate). Most negative voltage in the system connects
here.
Logic Positive Supply voltage.
are inactive and the Flag and outputs are reset from a fault condition. An
undervoltage condition emulates a high OE input.
Logic reference (Ground) pin.
October 1998 7-59
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MIC59P50 Micrel
Electrical Characteristics
VDD = 5V; TA = +25°C; unless noted.
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Leakage Current I
Collector-Emitter V
CEX
CE(SAT)
Saturation Voltage I
Input Voltage V
Input Resistance R
Flag Output Current I
Flag Output Leakage I
Supply Current I
IN(0)
V
IN(1)
IN
OL
OH
DD(ON)
(One output V
active) VDD = 5.0V, Outputs Open 2.4 3.6
I
DD(ON)
(All outputs V
active) VDD = 5.0V, Outputs Open 4.7 7.5
I
DD(OFF)
(Total) VDD = 5.0V, Outputs Open, Inputs = 0V 2.2 3.6
Clamp Diode I
Leakage Current VR = 80V, TA = +70°C 100
Over-Current Threshold I
Start-Up Voltage V
Minimum Operating V
DD
Clamp Diode Forward Voltage V
R
LIM
SU
V
DD MIN
F
Thermal Shutdown 165 °C
Thermal Shutdown Hysteresis 10
NOTE 3: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic “1”.
NOTE 4: Undervoltage lockout is guaranteed to release device at no more than 4.5V and disable the device at no less than 3.0V input logic voltage.
VCE = 80V, TA = +25°C50µA
VCE = 80V, TA = +70°C 100
IC = 100 mA 0.9 1.1 V
= 200 mA 1.1 1.3
C
IC = 350 mA 1.3 1.6
1.0 V
VDD = 12V 10.5
= 10V 8.5
V
DD
VDD = 5.0V Note 3 3.5
VDD = 12V 50 200 kΩ
= 10V 50 300
V
DD
VDD = 5.0V 50 600
VOL = 0.4V 15 mA
VOH = 12.0V 50 nA
VDD = 12V, Outputs Open 3.3 4.5 mA
= 10V, Outputs Open 3.1 4.5
DD
VDD = 12V, Outputs Open 6.4 10.0 mA
= 10V, Outputs Open 6.0 9.0
DD
VDD = 12V, Outputs Open, Inputs = 0V 3.0 4.5 mA
VR = 80V, TA = +25°C50µA
Each Output 500 mA
Note 4 3.5 4.0 4.5 V
3.0 3.5 4.0 V
IF = 350 mA 1.7 2.0 V
T ruth Tab le
Output OUT
IN
N
Strobe Clear Enable t–1 t
0 1 0 0 X OFF
11 0 0XON
X X 1 X X OFF
X X X 1 X OFF
X 0 0 0 ON ON
X 0 0 0 OFF OFF
X = Irrelevant
t–1 = previous output state
t = present output state
N
Information present at an input is transferred to its latch when
the STROBE is high. A high CLEAR input will set all latches
to the output OFF condition regardless of the data or STROBE
input levels. A high OUTPUT ENABLE will set all outputs to
the off condition, regardless of any other input conditions.
When the OUTPUT ENABLE is low, the outputs depend on
the state of their respective latches. If current shutdown is
activated, the OUTPUT ENABLE must be pulsed high to
restore operation and reset the Flag. Over temperature
faults are not latched and require no reset pulse.
7-60 October 1998
Page 4
MIC59P50 Micrel
100
120
140
160
180
200
220
240
260
56789101112131415
OUTPUT DELAY (ns)
SUPPLY VOLTAGE (V)
Output Enable Delay
vs. Supply Voltage
TD OFF
TD ON
RL = 50Ω
CLEAR
F
STROBE
OUTPUT
ENABLE
IN
OUT
C
BA
G
N
D
N
C
B
E
C
BA
G
E
Timing Conditions
(TA = +25°C, Logic Levels are VDD and VSS, VDD = 5V).
A. Minimum data active time before strobe enabled (data set-up time) ......................................................................50 ns
B. Minimum data active time after strobe disabled (data hold time)............................................................................50 ns
C. Minimum strobe pulse width..................................................................................................................................125 ns
D. Typical time between strobe activation and output on to off transition..................................................................500 ns
E. Typical time between strobe activation and output off to on transition..................................................................500 ns
F. Minimum clear pulse width ....................................................................................................................................300 ns
G. Minimum data pulse width.....................................................................................................................................225 ns
Typical Characteristic Curves
Output Saturation
Voltage vs. Temperature
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
SATURATION VOLTAGE (V)
0.6
–50 0 50 100 150
IL = 350mA
VDD = 5V to 12V
IL = 100mA
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
Supply Current
vs. Temperature
6
5
4
3
2
1
0
–50 0 50 100 150
ALL OUTPUTS ON
VDD = 5V
ALL OUTPUTS OFF
TEMPERATURE (°C)
Current Shutdown
Delay vs. Output Current
7
6
5
4
3
2
1
CURRENT SHUTDOWN DELAY (µs)
0
0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT CURRENT (A)
VDD = 5V
VDD = 12V
7
Current Shutdown
Threshold vs. Temperature
0.60
0.55
0.50
0.45
0.40
0.35
SHUTDOWN THRESHOLD (A)
–50 0 50 100 150
October 1998 7-61
VDD = 5V
VDD = 12V
TEMPERATURE (°C)
Supply Current
vs. Temperature
8
7
6
ALL OUTPUTS ON
5
4
3
ALL OUTPUTS OFF
2
SUPPLY CURRENT (mA)
1
0
–50 0 50 100 150
TEMPERATURE (°C)
VDD = 12V
Page 5
MIC59P50 Micrel
Typical Applications
MIC59P50 Protected Relay Driver
FLAG
OUTPUT
STROBE
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
INPUT 6
INPUT 7
INPUT 8
10kΩ
10
11
12
1
2
3
4
5
6
7
8
9
+5V
THERMAL
SHUTDOWN
LATCHES
UVLO
I
LIMIT
24
23
22
21
20
19
18
17
16
15
14
13
+5V
0.1µF
+24V
22µF
+
K1
K2
K3
K4
K5
K6
K7
K8
7-62 October 1998
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