Datasheet MIC58P42BWM, MIC58P42BN, MIC58P42BV Datasheet (MICREL)

MIC58P42 Micrel

MIC58P42

8-Bit Serial-Input Protected Latched Driver

General Description

The MIC58P42 serial-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common STROBE, CLOCK, SERIAL DATA INPUT, and
OUTPUT ENABLE functions. Similar to the MIC5842, addi­tional protection circuitry supplied on this device includes
thermal shutdown, under voltage lockout (UVLO), and over­current shutdown.

The bipolar/CMOS combination provides an extremely low­power latch with maximum interface flexibility. The MIC58P42
has open-collector outputs capable of sinking 500 mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply,
where the negative supply is down to –20V and may be
paralleled for higher load current capability.

With a 5V logic supply, the MIC58P42 will typically operate at
better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compat­ible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors. By using the serial data
output, drivers may be cascaded for interface applications
requiring additional drive lines.

Features

• 3.3 MHz Minimum Data-Input Rate

• CMOS, PMOS, NMOS, and TTL Compatible

• Internal Pull-Up/Pull-Down Resistors

• Low Power CMOS Logic and Latches

• High Voltage (80V) Current-Sink Outputs

• Output Transient-Protection Diodes

• Single or Split Supply Operation

• Thermal Shutdown

• Under-Voltage Lockout

• Per-Output Over-Current Shutdown (500mA typical)

Ordering Information

Part Number Temperature Range Package

MIC58P42BN –40°C to +85°C 18-Pin Plastic DIP
MIC58P42BV –40°C to +85°C 20-Pin PLCC
MIC58P42BWM –40°C to +85°C 18-Pin Wide SOIC

Each of these eight outputs has an independent over current
shutdown of 500 mA. Upon over-current detection, the
affected channel will turn OFF until VDD is cycled or the
ENABLE/RESET pin is pulsed high. Current pulses less than
2µs will not activate current shutdown. Temperatures above
165°C will shut down the device. The UVLO circuit prevents
operation at low VDD; hysteresis of 0.5V is provided. See the
MIC59P60 for a similar device that additionally provides an
error flag output.

Functional Diagram

CLOCK

SERIAL

DATA IN

THERMAL

SHUTDOWN

2

3

V

4

SS

UVLO

I

LIMIT

K OUT

8-BIT SERIAL–PARALLEL SHIFT REGISTER

LATCHES

OUT

OUT

OUT

OUT

1

3

2

MOS

BIPOLAR

SUB

OUT

OUT

OUT

6

5

4

8

7

1

V

EE

SERIAL DATA OUT

6
5

V

DD

7

STROBE

8

OUTPUT
ENABLE/RESET

910 1112131415161718

Pin Configuration

(DIP and SOIC)

V

1

EE

CLOCK

2

SERIAL DATA IN

SERIAL DATA OUT

STROBE
OUTPUT

ENABLE/RESET

3

V

4

SS

V

DD

5

6

7

8

V

9

EE

SUB

SHIFT REGISTER

SUB

UVLO

LATCHES

I LIMIT
THERMAL

SHUTDOWN

7

OUT

18

1

OUT

17

2

OUT

16

3

OUT

15

4

OUT

14

5

OUT

13

6

OUT

12

7

OUT

11

8

K

10

October 1998 7-49

MIC58P42 Micrel

PLCC Pin Configuration

SERIAL DATA IN

CLOCK

2

3

NC

4

V

5

SS

V

DD

SERIAL DATA OUT

NC

MIC58P42BV

6

7

8

9 10

STROBE

OE/RESET

Typical Input Circuits

Absolute Maximum Ratings (Note 1, 2)

at 25°C Free-Air Temperature and VSS = 0V

Output Voltage 80V
Output Voltage, V

CE(SUS)

Logic Supply Voltage Range, V

EE

OUT 1

20 19

12 1311

K

OUT 2

18

17

16

15

14

OUT 8

OUT 3
OUT 4
OUT 5
OUT 6
OUT 7

V

1

EE

V

VDD with Reference to V
Emitter Supply Voltage (Substrate), V
Input Voltage Range, V
Package Power Dissipation, P
MIC58P42BN 1.82W
Derate above TA = +25°C 18mW/°C
MIC58P42BV 1.4W
Derate above TA = +25°C 14mW/°C
MIC58P42BWM 1.2W
Derate above TA = +25°C 12mW/°C
Operating Temperature Range, T
Storage Temperature Range, T

Note 1:For Inductive load applications.

Note 2: CMOS devices have input-static protection but are susceptible to

damage when exposed to extremely high static electrical
charges.

(Note 1) 50V

4.5V to 15V

–55°C to +125°C
–65°C to +150°C

IN

DD

EE

EE

–0.3V to VDD + 0.3V

D

A

S

25V

–20V

Typical Output Driver

SUB

K

NOUT

V

EE

STROBE
OUTPUT
ENABLE

V

V

DD

CLOCK
SERIAL

DATA IN

V

SS

DD

V

SS

3K

Pin Description

Pin Name Description

(DIP & S.O.)
1,9 V

EE

2 CLOCK Serial Data Clock. A CLEAR input must also be clocked into the latches.
3 SERIAL DATA IN Serial Data Input pin.
4V
5V

SS
DD

6 SERIAL DATA OUT Serial Data Output pin. (Flow–through).

Substrate. Most Negative voltage in the system connects here.

Logic reference (Ground) pin.
Logic Positive Supply voltage.

7 STROBE Output Strobe pin. Loads output latches when high. Strobe is needed to clear latch.
8 OUTPUT When Low, Outputs are active. When High, device is reset from a fault condition.

ENABLE/RESET
10 K Transient suppression diode's cathode common pin.
11—18 OUTPUT N Open Collector outputs 8 through 1.

7-50 October 1998

MIC58P42 Micrel

Electrical Characteristics at T

= +25°C, VDD = 5V, VSS = VEE = 0V (unless otherwise noted)

A

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Output Leakage Current I

Collector-Emitter V

CEX

CE(SAT)

Saturation Voltage I

Collector-Emitter V

CE(SUS)

V

= 80V 50 µA

OUT

V

= 80V, TA = +70°C 100

OUT

I

= 100mA 0.9 1.1 V

OUT

= 200mA 1.1 1.3

OUT

I

= 350mA 1.3 1.6

OUT

I

= 350mA, L = 2mH 50 V

OUT

Sustaining Voltage
Input Voltage V

Input Resistance R

Supply Current I

Clamp Diode I

IN(0)

V

IN(1)

IN

DD(ON)

I

DD (1 ON)

I

DD(OFF)

R

VDD = 12V 10.5

= 10V 8.5

V

DD

VDD = 5.0V, Note 1 3.5
VDD = 12V 50 200 kΩ

= 10V 50 300

V

DD

VDD = 5.0V 50 600
All Drivers ON, VDD = 12V 6.4 10.0 mA

All Drivers ON, V
All Drivers ON, VDD = 5.0V 4.6 7.5

= 10V 6.0 9.0

DD

One Driver ON, All others OFF, VDD = 12V 3.1 4.5
One Driver ON, All others OFF, V
One Driver ON, All others OFF, VDD = 5V 2.3 3.6

= 10V 2.9 4.5

DD

All Drivers OFF, VDD = 12V 2.6 4.2
All Drivers OFF, V
All Drivers OFF, VDD = 5.0V 1.9 3.0

= 10V 2.4 3.6

DD

VR = 80V 50 µA

1.0 V

Leakage Current
Clamp Diode V

F

IF = 350mA 1.7 2.0 V

Forward Voltage
Output Current I

Shutdown Threshold
Start Up Voltage V
Minimum Supply (VDD)V

LIM

SU
DD MIN

Note 2 3.5 4.0 4.5 V

3.0 3.5 4.0 V

500 mA

Thermal Shutdown 165 °C
Thermal Shutdown Hysteresis 10 °C

Note 1: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic "1".
Note 2: Undervoltage Lockout is guaranteed to release device at no more than 4.5V, and disable the device at no less than 3.0V.

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October 1998 7-51

MIC58P42 Micrel

CLOCK

D

B

E

C

F

G

DATA IN

STROBE

OUTPUT
ENABLE

OUT

A

N

Timing Conditions

(TA = +25°C, Logic Levels are VDD and VSS), VDD = 5V

A. Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ...........................................................................75 ns

B. Minimum Data Active Time After Clock Pulse (Data Hold Time)..............................................................................75 ns

C. Minimum Data Pulse Width .....................................................................................................................................150 ns

D. Minimum Clock Pulse Width....................................................................................................................................150 ns

E. Minimum Time Between Clock Activation and Strobe .............................................................................................300 ns

F. Minimum Strobe Pulse Width...................................................................................................................................100 ns

G. Typical Time Between Strobe Activation and Output Transition .............................................................................500 ns

SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform.

Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.

When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches
or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OUTPUT ENABLE/
RESET pulse resets the output after a current shutdown fault. Thermal limit faults are not latched and require no reset pulse.

MIC58P42 T ruth T able

Shift Register Contents Serial Latch Contents Output Contents

Serial Data Clock Data Strobe Output

Input Input I

HHR

LLR

XR1R2R

L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF

I

1

I3…… I8Output Input I1I

2

1R2
1R2

…… R
…… R
…… R

3

7
7
8

R

7

R

7

R

8

2I3

…… I8Enable I1I

OOO……O L
XXX……X X L R1R2R3…… R

P1P2P3…… P

8

P

HP1P2P3…… P

8

XX X……X H H H H……H

2I3

8

LP1P2P3……P

8

…… I

8

8

7-52 October 1998

MIC58P42 Micrel

0

1

2

3

4

5

–50 0 50 100 150

SUPPLY CURRENT (mA)

TEMPERATURE (°C)

ALL OUTPUTS ON

ALL OUTPUTS OFF

Supply Current

vs. Temperature

VDD = 5V

0

1

2

3

4

5

6

7

–50 0 50 100 150

SUPPLY CURRENT (mA)

TEMPERATURE (°C)

Supply Current

vs. Temperature

ALL OUTPUTS ON

ALL OUTPUTS OFF

VDD = 12V

0

2

4

6

8

10

12

14

16

18

20

0.3 0.4 0.5 0.6 0.7 0.8 0.9

CURRENT LIMIT DELAY (µs)

OUTPUT CURRENT (A)

Current Shutdown

Delay vs. Output Current

VDD = 12V

VDD = 5V

Typical Characteristic Curves

Output Saturation

Voltage vs. Temperature

1.5

1.4

1.3

1.2

1.1
1

0.9

0.8

0.7

0.6

SATURATION VOLTAGE (V)

0.5

–50 0 50 100 150

IL = 350mA

VDD = 5V to 12V

IL = 100mA

TEMPERATURE (°C)

Output Delay

vs. Supply Voltage

300

250

200

150

100

OUTPUT DELAY (ns)

50

5 7 9 11 13 15

SUPPLY VOLTAGE (VDD)

RL = 50Ω

TD OFF

T

D

ON

Current Shutdown

Threshold vs. Temperature

0.60

0.55

0.50

0.45

0.40

0.35

SHUTDOWN THRESHOLD (A)

–50 0 50 100 150

TEMPERATURE (°C)

V

DD

= 12V

VDD = 5V

Maximum Allowable Duty Cycle, Plastic DIP

VDD = 5.0V

VDD = 12V

October 1998 7-53

Number of Outputs ON

(I

= 200mA Max. Allowable Duty Cycle at Ambient Temperature of:

OUT

V

= 5.0V) 25°C40°C50°C60°C70°C

DD

8 85% 72% 64% 55% 46%
7 97% 82% 73% 63% 53%
6 100% 96% 85% 73% 62%
5 100% 100% 100% 88% 75%
4 100% 100% 100% 100% 93%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%

Number of Outputs ON

(I

= 200mA Max. Allowable Duty Cycle at Ambient Temperature of:

OUT

VDD = 12V) 25°C40°C50°C60°C70°C

8 80% 68% 60% 52% 44%
7 91% 77% 68% 59% 50%

6 100% 90% 79% 69% 58%
5 100% 100% 95% 82% 69%
4 100% 100% 100% 100% 86%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%

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