Page 1
Preliminary Spec.
Some contents are subject to change without notice.
for easy interchange or addition of modules.
APPLICATION
4096 refresh cycle /64ms
(Component SDRAM)
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
DESCRIPTION
The MH8S64DBKG is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
FEATURES
Frequency
-7,-7L
-8,-8L
100MHz
PC100 compliant
CLK Access Time
6.0ns(CL=2)
6.0ns(CL=3)100MHz
Utilizes industry standard 4M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
PCB Outline
(Front)
(Back)
main memory or graphic memory in computer systems
1
2
143
144
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Page 2
Preliminary Spec.
Some contents are subject to change without notice.
PIN CONFIGURATION
Number
Pin Name
Pin Name
Number
1
357911131517192468101214161820
Number
Pin Name
Pin Name
Number
73747576777879808182838485
868788899091922122939423249596252697982728991002930
101
1023132
103
1043334
105
1063536
107
1083738
109
1103940
111
1124142
113
1144344
115
1164546
117
1184748
119
1204950
121
1225152
123
1245354
125
1265556
127
1285758
129
1305960
131
1326162
133
1346364
135
1366566
137
1386768
139
1406970
141
1427172
143
144
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
NC
CLK1
Vss
VssNCNCNCNC
Vcc
Vcc
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
Vss
Vss
Vss
Vss
DQ20
DQ52
DQMB0
DQMB4
DQ21
DQ53
DQMB1
DQMB5
DQ22
DQ54
Vcc
Vcc
DQ23
DQ55
A0A3Vcc
VccA1A4A6A7A2A5A8BA0
Vss
Vss
Vss
Vss
DQ8
DQ40
A9
BA1
DQ9
DQ41
A10
A11
DQ10
DQ42
Vcc
Vcc
DQ11
DQ43
DQMB2
DQMB6
Vcc
Vcc
DQMB3
DQMB7
DQ12
DQ44
Vss
Vss
DQ13
DQ45
DQ24
DQ56
DQ14
DQ46
DQ25
DQ57
DQ15
DQ47
DQ26
DQ58
Vss
Vss
DQ27
DQ59
NCNCVcc
VccNCNC
DQ28
DQ60
CLK0
CKE0
DQ29
DQ61
Vcc
Vcc
DQ30
DQ62
/RAS
/CAS
DQ31
DQ63
/WE
CKE1
Vss
Vss
/S0NCSDA
SCL
/S1NCVcc
Vcc
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
PIN
Front side
PIN
Back side
PIN
Front side
PIN
Back side
MIT-DS-0340-0.0
NC = No Connection
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Page 3
Preliminary Spec.
Some contents are subject to change without notice.
Block Diagram
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
/S0
/S1
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10Ω
CLK1
CLK0
CKE0
CKE1
/RAS
/CAS
/WE D0 - D7
BA0,BA1,A<11:0>
Vcc
Vss
MIT-DS-0340-0.0
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D0
/CS
D1
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
4loads
4loads
D0 - D3
D4 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
/CS
D4
/CS
D5
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SCL
MITSUBISHI
ELECTRIC
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SERIAL PD
A0 A1 A2
/CS
D2
/CS
D3
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDA
17.Sep.1999
/CS
D6
/CS
D7
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Page 4
Preliminary Spec.
Some contents are subject to change without notice.
Serial Presence Detect Table I
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Non-PARITY
Minimum Clock Delay,Back to Back Random Column Addresses
1/2/4/8/Full page
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8,8L
-8,8L
-7,7L
-7,7L
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Byte Function described SPD enrty data SPD DATA(hex)
Defines # bytes written into serial memory at module mfgr 128
0
1 Total # bytes of SPD memory device
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 SDRAM Cycle time(2nd highest CAS latency)
24
25
26
27
28
29
30
DIMM Configuration type (Non-parity,Parity,ECC)
SDRAM Cycle time(3rd highest CAS latency)
Fundamental memory type SDRAM 04
# Row Addresses on this assembly A0-A11 0C
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly... x64 40
... Data Width continuation 0 00
Voltage interface standard of this assembly LVTTL 01
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
Refresh Rate/Type self refresh(15.625uS) 80
SDRAM width,Primary DRAM
Error Checking SDRAM data width N/A 00
Burst Lengths Supported
# Banks on Each SDRAM device 4bank 04
CAS# Latency 2/3 06
CS# Latency 0 01
Write Latency 0 01
SDRAM Module Attributes
SDRAM Device Attributes:General
Cycle time for CL=2
tAC for CL=2
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
Active to Precharge Min
256 Bytes 08
A0-A7 08
2BANK 02
10ns
6ns 60
x16 10
1 01
10ns
13ns D0
6ns 60
7ns 70
N/A 00
N/A 00
20ns 14
20ns 14
20ns 14
50ns 32
80
A0
00
8F
00
0E
A0
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Page 5
Preliminary Spec.
Some contents are subject to change without notice.
Serial Presence Detect Table II
4D483853363444424B472D38202020202020
Manufacturing date
4D483853363444424B472D384C2020202020
4D483853363444424B472D374C2020202020
-7,7LCF-8,8L
4D483853363444424B472D37202020202020
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
31 Density of each bank on module 32MByte 08
32 Command and Address signal input setup time 2ns 20
33 Command and Address signal input hold time
34
35 Data signal input hold time
36-61
62 SPD Revision
63 Checksum for bytes 0-62
64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location Miyoshi,Japan 01
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr
93-94
95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacture Specific Data option 00
126 Intetl specification frequency
127 Intel specification CAS# Latency support
128+ Unused storage locations open 00
Data signal input setup time
Superset Information (may be used in future) option 00
1ns 10
2ns
1ns 10
rev 1.2A 12
Check sum for -7,7L 05
Check sum for -8,-8L 45
Tajima,Japan 02
NC,USA 03
Germany 04
MH8S64DBKG-7
MH8S64DBKG-7L
MH8S64DBKG-8
MH8S64DBKG-8L
year/week code yyww
100MHz 64
20
CD
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Page 6
Preliminary Spec.
Some contents are subject to change without notice.
PIN FUNCTION
Combination of /RAS,/CAS,/WE defines basic commands.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CLK
(CLK0 ~ CLK1)
CKE0, CKE1 Input
/S0, /S1
/RAS,/CAS,/WE Input
A0-11 Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1 Input
DQ0-63
DQMB0-7 Input
Vdd,Vss
SCL
SDA
MIT-DS-0340-0.0
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Input/Output
Power Supply Power Supply for the memory mounted module.
Input
Output
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Serial clock for serial PD
Serial data for serial PD
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Page 7
Preliminary Spec.
Some contents are subject to change without notice.
The MH8S64DBKG provides basic functions,bank(row)activate,burst read / write,
To know the detailed definition of commands please see the command truth table.
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
CK
/S
Chip Select : L=select, H=deselect
/RAS
/CAS
/WE
CKE
A10
Command
Command
Command
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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Page 8
Preliminary Spec.
Some contents are subject to change without notice.
Precharge All Bank
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND MNEMONIC
CKE
n-1
CKE
n
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
/S
/RAS
/CAS
/WE BA0,1 A10
A11
A0-9
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
Burst Terminate TERM
Mode Register Set
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
MRS
H X L L H L X H X
H X L H L L V L V
L H L H H H X X X
H X L H H L X X X
H X L L L L L L
X
X
V
X
X
X
X
X
X
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Page 9
Preliminary Spec.
Some contents are subject to change without notice.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L
L H L X
L L H H
L L H L
L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST NOP
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
BA TBST ILLEGAL*2
BA,CA,A10
BA,RA
BA,A10 PRE/PREA NOP*4
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
Op-Code,
Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
Action
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Page 10
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
BA,RA
Op-Code,
Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
ILLEGAL
ILLEGAL
Action
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Page 11
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
MIT-DS-0340-0.0
Op-Code,
Mode-Add
MITSUBISHI
MRS ILLEGAL
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Page 12
Preliminary Spec.
Some contents are subject to change without notice.
1. All entries assume that CKE was High during the preceding clock cycle and the current
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
MITSUBISHI LSIs
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
NOP(Idle after tRC)
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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Preliminary Spec.
Some contents are subject to change without notice.
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
CK
CK
n-1
L H L H H H X
L H L H H L X
L H L H L X X
L H L L X X X
L L X X X X X
L L X X X X X
H L H X X X X
H L L H H H X
H L L H H L X
H L L H L X X
H L L L X X X
n
/RAS /CAS /WE Add
/S
Action
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
L X X X X X X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
L L X X X X X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0340-0.0
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Preliminary Spec.
Some contents are subject to change without notice.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
WRITE
CKEH
WRITEA READA
MRS
IDLE
ACT
CKEL
CKEH
ROW
ACTIVE
WRITE READ
WRITEA
WRITE
WRITEA
READA
READ
READA
REFA
CKEL
CKEH
READ
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
MIT-DS-0340-0.0
WRITEA
SUSPEND
POWER
APPLIED
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PRE PRE
PRE
CHARGE
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READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
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Preliminary Spec.
Some contents are subject to change without notice.
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
SDRAM is ready for new command.
LENGTH
LATENCY
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power.Attempt to maintain CKE high,DQM0-7
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
0 0
LTMODE BT BL
BURST
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
WRITE
MODE
MIT-DS-0340-0.0
BURST
0
SINGLE BIT FP: Full Page
1
MITSUBISHI
R:Reserved for Future Use
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Preliminary Spec.
Some contents are subject to change without notice.
READ
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK
frequency,i.e.,the speed of CLK determines which CL should be used.First output data is
available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
DQ
DQ
ACT
tRCD
X
READ
Y
CL=2
Q0 Q1 Q2 Q3
CL=3
Q0 Q1 Q2 Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page
the output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
ACT
Address
DQ
DQ
DQ
DQ
DQ
MIT-DS-0340-0.0
X
Y
Q0
Q0 Q1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
m=255
MITSUBISHI
Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
BL=1
BL=2
BL=4
BL=8
BL=FP
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Preliminary Spec.
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536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CK
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
Command
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
CL= 3
BL= 4
BL
8
Read
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Write
Y
D0 D1
D2
D3
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0340-0.0
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
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Preliminary Spec.
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OPERATION DESCRIPTION
BANK ACTIVATE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
tRP from the precharge, an ACT command can be issued.
depends on /CAD Latency. The next ACT command can be issued after tRP from the internal
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.
PRECHARGE
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After
Bank Activation and Precharge All (BL=4, CL=3)
CK
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
Xa
00
tRRD
tRCD
ACT
Xb
Xb
01
READ
Y
0
00
PRE
tRAS tRP
1
Qa0 Qa1 Qa2 Qa3
Precharge all
ACT
Xb
Xb
01
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A7-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active
bank, so the row precharge time(tRP) can be hidden behind continuous output data(in case
of BL=8) by interleaving the dual banks. When A10 is high at a READ command, the autoprecharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same
bank is inhibited till the internal precharge is complete. The internal precharge start timing
precharge timing.
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Preliminary Spec.
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536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Dual Bank Interleaving READ (BL=4, CL=3)
CK
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
Command
A0-9,11
A10
BA0,1
DQ
CK
Command
A0-9,11
A10
ACT
tRCD
Xa
Xa
0
READ
Y
0
0
ACT
Xb
Xb
1
/CAS latency
READ
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
ACT
tRCD tRP
Xa
Xa
READ
Y
1
PRE
Y
0
0
1
0
ACT
Xa
Xa
BA0,1
DQ
CK
Command
CL=3
CL=2
0
0
Qa0 Qa1 Qa2 Qa3
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
ACT READ
DQ Qa0 Qa1 Qa2 Qa3
DQ Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
0
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Preliminary Spec.
Some contents are subject to change without notice.
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
WRITE
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A7-0, and the address sequence of
burst data is defined by the Burst Type. A WRITE command may be applied to any active
bank, so the row precharge time(tRP) can be hidden behind continuous input data (in case
of BL=8) by interleaving the dual banks. From the last input data to the PRE command, the
write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge(WRITEA) is performed. Any command(READ, WRITE, PRE, ACT) to the same
bank is inhibited till the internal precharge is complete. The internal precharge begins at
tWR after the last input data cycle. The next ACT command can be issued after tRP from the
internal precharge timing.
Dual Bank Interleaving WRITE (BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQ
CK
Command
A0-9,11
ACT
tRCD
Xa
Xa
0
Write
ACT
tRCD
Y
Xb
0
Xb
0
1
Da0 Da1 Da2 Da3
Burst Length
WRITE with Auto-Precharge (BL=4)
ACT
tRCD tRP
Xa
Write
Y
Write
PRE
Y
tWR
0
0
1
0
Db0 Db1 Db2 Db3
ACT
Xa
A10
BA0,1
DQ
MIT-DS-0340-0.0
Xa
0
1
0
Da0 Da1 Da2 Da3
MITSUBISHI
Xa
0
tWR
Internal precharge begins
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Preliminary Spec.
Some contents are subject to change without notice.
A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in
burst length can be set to 1,2,4,8,and full-page,like burst read operations.
A single write operation is enabled by setting A9=1 at MRS.In a single write
input is 0.)
READ
READ
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ BURST WRITE ]
the same cycle as a write command set.(The latency of data input is 0.) The
tRCD
CK
MITSUBISHI LSIs
Command
Address
DQ
DQ
DQ
DQ
DQ
ACT
[ SINGLE WRITE ]
X
Y
Q0
Q0 Q1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
m=255
Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
BL=1
BL=2
BL=4
BL=8
BL=FP
operation,data is written only to the column address specified by the write
command set cycle without regard to the burst length setting.(The latency of data
CK
Command
Address
DQ
MIT-DS-0340-0.0
ACT
X
tRCD
Y
Q0
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Preliminary Spec.
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BURST INTERRUPTION
MH8S64BBKG allows random column access. READ to READ interval is minimum 1 CK
Yl
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of the same or the other bank.
Read Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9,11
A10
BA0,1
DQ
READ
Yi
0
0
READ
Yj
0
0
READ
Yk
0
1
Qai0 Qaj1 Qbk0 Qbk1
Qaj0 Qbk2 Qal0
READ
0
0
Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
READ
Write
A0-9,11
A10
BA0,1
DQMB0-7
Q
D
MIT-DS-0340-0.0
Yi
0
0
Qai0
Yj
0
0
Daj0 Daj1 Daj2 Daj3
DQM control Write control
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Preliminary Spec.
Some contents are subject to change without notice.
[ Read Interrupted by Precharge ]
terminated.
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst read operation can be interrupted by precharge of the same or the other bank.
Read to PRE interval is minimum 1 CK. A PRE command disables the data output,
depending on the /CAS Latency. The figure below shows examples, when the dataout is
Read Interrupted by Precharge (BL=4)
CK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
READ
READ PRE
READ
Q0 Q2 Q3Q1
READ PRE
Q0 Q1
PRE
Q0 Q1
Q0 Q1
PRE
Q2 Q3
MIT-DS-0340-0.0
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command,TBST, can interrupt burst read
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST
is mainly used to interrupt FP bursts.The figure below show examples, of how the output
data is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
READ TBST
Q0 Q1
READ
READ TBST
READ
READ
TBST
Q0 Q1 Q2
Q0
TBST
Q0 Q1 Q2 Q3
TBST
Q0 Q1 Q2
Q2 Q3
MIT-DS-0340-0.0
Command
DQ
READ
TBST
Q0
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Preliminary Spec.
Some contents are subject to change without notice.
Yi
Yi
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQ
Write
Write
Yj
0
0
0
0
Dai0 Daj0 Daj1 Dbk0
Write
Yk
0
1
Dbk1 Dbk2
Write
Yl
0
0
Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9,11
A10
BA0,1
DQMB0-7
DQ
MIT-DS-0340-0.0
Write
0
0
READ
Yj
0
0
Qaj0
Qaj1Dai0 Dak0 Dak1
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Write
Yk
0
0
READ
Yl
0
1
Qbl0
17.Sep.1999
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Preliminary Spec.
Some contents are subject to change without notice.
[ Write Interrupted by Precharge ]
DQMB0-7 shown as below.
[ Write Interrupted by Burst Terminate ]
WRITE to TERM interval is minimum 1 CK.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required
between the last input data and the next PRE, 3rd data should be masked with
Write Interrupted by Precharge (BL=4)
CK
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
Command
A0-9,11
A10
BA0,1
DQMB0-7
DQ
Write
Yi
0
0
Dai0 Dai1
PRE
tWR tRP
0
0
This data should be masked to satisfy tWR requirement.
ACT
Xb
Xb
0
Burst terminate command can terminate burst write operation. In this case, the
write recovery time is not required and the bank remains active. The figure below
shows the case 3 words of data are written. Random column access is allowed.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQMB0-7
DQ
MIT-DS-0340-0.0
Write
Yi
0
0
Dai0 Dai1
Dai2
TERM
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Preliminary Spec.
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4bank alternately(ping-pong refresh). Before performing an auto-refresh, both banks
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on
must be in the idle state. Additional commands must not be supplied to the device
before tRC from the REFA command.
Auto-Refresh
CK
/S
/RAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
NOP or DESLECT
/CAS
/WE
CKE
A0-11
BA0,1
minimum tRC
Auto Refresh on Bank 0 Auto Refresh on Bank 1
MIT-DS-0340-0.0
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Preliminary Spec.
Some contents are subject to change without notice.
SELF REFRESH
asserting CKE(REFSX). After tRC from REFSX both banks are in the idle state and a
asserted till then.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input (but asynchronous), all other inputs including CK0 are disabled and ignored,
and power consumption due to synchronous inputs is saved. To exit the selfrefresh, supplying stable CK0 inputs, asserting DESEL or NOP command and then
new command can be issued after tRC, but DESEL or NOP commands must be
Self-Refresh
CK
/S
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
Stable CK
NOP
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry Self Refresh Exit
new command
X
0
minimum tRC
for recovery
MIT-DS-0340-0.0
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Preliminary Spec.
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CLK SUSPEND
when the banks are active or idle, but a command at the following cycle is ignored.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
CK
(ext.CLK)
CKE
int.CLK
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CK
CKE
Command
CKE
Command
CK
CKE
PRE
ACT
Power Down by CKE
Standby Power Down
NOP NOP NOP NOP NOP NOP
NOP
Active Power Down
NOP NOP NOP NOP NOP NOP
NOP
DQ Suspend by CKE
Command
DQ
MIT-DS-0340-0.0
Write
D0 D1 D2 D3
READ
Q0 Q1 Q2 Q3
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Page 30
Preliminary Spec.
Some contents are subject to change without notice.
DQM CONTROL
latency is 2.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
CK
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
DQM Function
Command
DQMB0-7
DQ
Write
D0 D2 D3
masked by DQM=H
READ
Q0 Q1 Q3
disabled by DQM=H
MIT-DS-0340-0.0
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Page 31
Preliminary Spec.
Some contents are subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
mA
RECOMMENDED OPERATING CONDITION
CAPACITANCE
VI = 1.4V
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
Symbol Parameter
Vdd
VI
VO
IO
Pd
Topr
Tstg
(Ta=0 ~ 70°C, unless otherwise noted)
Symbol
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Parameter
Condition Ratings Unit
with respect to Vss
with respect to Vss
with respect to Vss
Ta=25°C
Limits
Min. Typ. Max.
-0.5 ~ 4.6
-0.5 ~ Vdd+0.5
-0.5 ~ Vdd+0.5
50
8
0 ~ 70
-40 ~ 100
V
V
V
W
°C
°C
Unit
Vdd
Vss
VIH
VIL
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK pin
Input Capacitance, I/O pin
Supply Voltage
Supply Voltage
Parameter
3.0
0
2.0
-0.3
Test Condition Limits(max.)
f=1MHz
Vi=200mVrms
3.3
0
Vdd+0.3
45
45
35
22
3.6
0
0.8
V
V
V
V
Unit
pF
pF
pF
pF
MIT-DS-0340-0.0
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Page 32
Preliminary Spec.
Some contents are subject to change without notice.
AVERAGE SUPPLY CURRENT from Vdd
AC OPERATING CONDITIONS AND CHARACTERISTICS
Limits
-8, -8L
Limits
(max)
active stanby current
one bank active (discrete)
CKE=VILmax,tCLK=15ns
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
Parameter
operating current
one bank active (discrete)
precharge stanby current
in non power-down mode
active stanby current
in power-down mode
in non power-down mode
burst current
auto-refresh current
self-refresh current
Note:Input signals are changed one time during 30ns.
Note:All other pins not under test are 0V.
Symbol
Icc1
Icc2N
Icc2NS
Icc3P
Icc3PS
Icc3N
Icc3NS
Icc4
Icc5
Icc6
tRC=min.tCLK=min, BL=1, CL=3
CKE=/CS=VIHmin,tCLK=15ns(Note), VIH>Vcc-0.2V, VIL<0.2V
CKE=VIHmin,CLK=VILmax(fixed), VIH>Vcc-0.2V, VIL<0.2V
CKE=CLK=VILmax(fixed)
CKE=/CS=VIHmin,tCLK=15ns
CKE=VIHmin,CLK=VILmax(fixed)
tCLK=min, BL=4, CL=3,All banks active(discerte)
tRC=min, tCLK=min
CKE <0.2V
Test Condition
-7, -8
-7L,-8L
-7, -7L
440
160
120
16
200
180
320
440
Unit
mA
mA
mA
mA
8
8
4
mA
mA
mA
mA
mA
mA
mA
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol Parameter Test Condition
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA 2.4 V
VOL(DC)
VOH(AC) High-Level Output Voltage(AC) CL=50pF, IOH=-
VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V
MIT-DS-0340-0.0
IOZ Off-stare Output Current Q floating VO=0 ~ Vdd -10 10 uA
Low-Level Output Voltage(DC)
Input Current
Ii
IOL=2mA 0.4 V
2mA
VIH=0 ~ Vdd+0.3V
MITSUBISHI
ELECTRIC
Min. Max.
2 V
-40 40
Unit
uA
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Preliminary Spec.
Some contents are subject to change without notice.
AC TIMING REQUIREMENTS
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
Row to Column Delay
tSRX
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
(SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Symbol Parameter
-7,-7L Unit
Min. Max.
Limits
MITSUBISHI LSIs
-8,-8L
Min. Max.
Note
tCLK
CK cycle time
tCH CK High pulse width
tCL CK Low pilse width
tT Transition time of CK
tIS Input Setup time(all inputs)
tIH Input Hold time(all inputs)
tRC Row cycle time
tRCD
tRAS Row Active time
tRP Row Precharge time
tWR Write Recovery time
tRRD Act to Act Deley time
tRSC Mode Register Set Cycle time
Self Refresh Exit time
tREF Refresh Interval time
CL=2
CL=3
10
13
10 10
3
3 ns
1 10 ns
2 ns
1
70 ns
20 ns
50
100K
20 ns
20 ns
20 ns
10 ns
10 ns
3
3
1 10
2
1
70
20
50
100K
20
20
20
10
10
64 ms
ns
ns
ns
ns
ns
64
1
1
1
1
CK
1.4V
Any AC timing is
referenced to the input
Signal
1.4V
signal crossing
through 1.4V.
MIT-DS-0340-0.0
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Page 34
Preliminary Spec.
Some contents are subject to change without notice.
1.4V
1.4V
SWITCHING CHARACTERISTICS
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
(SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.165V, Vss = 0V, unless otherwise noted)
Limits
Symbol Parameter
-7,-7L
Min.
Max.
MITSUBISHI LSIs
-8,-8L
Unit
Min. Max.
tAC
tOH
Access time from CK
Output Hold time
from CK
Delay time, output low
tOLZ
impedance from CK
Delay time, output high
tOHZ
impedance from CK
Note:3 If tr(clock rising time) is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
50Ω
VOUT
50pF
VTT=1.4V
CL=2
CL=3
3
0
3 6
CK
Output Timing
Measurement
Reference Point
DQ
6
6
7
6
ns
ns
3 ns
0 ns
3 ns6
1.4V
1.4V
CK
DQ
MIT-DS-0340-0.0
tAC tOH
tOHZ
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Preliminary Spec.
Some contents are subject to change without notice.
Burst Write (single bank) @BL=4
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
/RAS
/CAS
CKE
DQM
A0-7
A10
tRAS
tRCD
tWR
X
X
Y
tRP
tRCD
X
X
Y
A8,9,11
BA0,1
DQ
MIT-DS-0340-0.0
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 0
D0 D0 D0 D0
X
0
Italic parameter indicates minimum case
0
D0 D0 D0 D0
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17.Sep.1999
Page 36
Preliminary Spec.
Some contents are subject to change without notice.
Burst Write (multi bank) @BL=4
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
/CS
/RAS
/CAS
CKE
DQM
A0-7
A10
tRRD
tRAS
tRCD
tWR
X
X
Y
X
X
Y
tRP
tWR
tRRD
tRCD
X
X
Y
X
X
A8,9,11
BA0,1
DQ
MIT-DS-0340-0.0
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
X
0 1
1
D0 D0 D0 D0
ACT#1 WRITE#1 PRE#1
0
D1 D1 D1 D1
Italic parameter indicates minimum case
X
0
1
ACT#2
X
0
2
D0 D0 D0 D0
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17.Sep.1999
Page 37
Preliminary Spec.
Some contents are subject to change without notice.
Burst Read (single bank) @BL=4 CL=3
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
/RAS
/CAS
CKE
DQM
A0-7
A10
tRAS
tRCD
DQM read latency =2
X
X
Y
tRP
tRCD
X
X
Y
A8,9,11
BA0,1
DQ
MIT-DS-0340-0.0
X
0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
0 0
CL=3
Q0 Q0 Q0 Q0
READ to PRE ≥BL allows full data out
X
0
Italic parameter indicates minimum case
0
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Q0 Q0
17.Sep.1999
Page 38
Preliminary Spec.
Some contents are subject to change without notice.
Burst Read (multiple bank) @BL=4 CL=3
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
tRC
/CS
/RAS
/CAS
CKE
DQM
A0-7
A10
X
X
tRRD
tRCD
tRRD
tRAS tRP
tRCD
DQM read latency =2
Y
X
X
Y
X
X
Y
X
X
A8,9,11
BA0,1
DQ
MIT-DS-0340-0.0
X
0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
X
0 0
1
CL=3
ACT#1
1
CL=3
Q0 Q0 Q0 Q0
READ#1 PRE#1 ACT#2
Italic parameter indicates minimum case
X
0
Q1 Q1 Q1 Q1
X
21
0
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38
Q0
17.Sep.1999
Page 39
Preliminary Spec.
Some contents are subject to change without notice.
Burst Write (multi bank) with Auto-Precharge @BL=4
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
/RAS
tRCD
/CAS
BL-1+ tWR + tRP
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
tRRD
tRCD
BL-1+ tWR + tRP
tRCD
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 with
ACT#1 WRITE#1 with
Y
X
X
X
0 1
1
D0 D0 D0 D0
AutoPrecharge
Y X
D1 D1 D1 D1
AutoPrecharge
Y
X
X
0
ACT#0 WRITE#0
0
D0 D0 D0 D0
X
X
X
1
ACT#1 WRITE#1
Y
1
D1
Italic parameter indicates minimum case
MIT-DS-0340-0.0
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17.Sep.1999
Page 40
Preliminary Spec.
Some contents are subject to change without notice.
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
/RAS
tRCD
/CAS
BL+tRP
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
tRRD
tRCD
BL+tRP
tRCD
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
DQM read latency =2
X
X
X
0
ACT#0 READ#0 with
ACT#1
Y
X
X
X
0
1
CL=3
Auto-Precharge
Y
1
CL=3
Q0 Q0 Q0 Q0
READ#1 with
Auto-Precharge
X
X
X
0
Q1 Q1 Q1 Q1
ACT#0 READ#0
Y
0
X
X
X
1
CL=3
ACT#1
Q0
Y
1
Q0
Italic parameter indicates minimum case
MIT-DS-0340-0.0
MITSUBISHI
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17.Sep.1999
Page 41
Preliminary Spec.
Some contents are subject to change without notice.
Page Mode Burst Write (multi bank) @BL=4
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0
Y
X
X
X
0 0
1
D0 D0 D0 D0
ACT#1
Y Y
D0 D0 D0 D0 D0 D0 D0
WRITE#0
Y
1
D1 D1 D1 D1
WRITE#1
0
MIT-DS-0340-0.0
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Italic parameter indicates minimum case
17.Sep.1999
Page 42
Preliminary Spec.
Some contents are subject to change without notice.
Page Mode Burst Read (multi bank) @BL=4 CL=3
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 READ#0
Y
X
X
X
0 0
1
CL=3 CL=3 CL=3
ACT#1
Y Y
Q0 Q0 Q0
Q0
READ#0
Y
1
Q0 Q0 Q0 Q0
READ#1
0
Q1 Q1 Q1 Q1
MIT-DS-0340-0.0
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Italic parameter indicates minimum case
17.Sep.1999
Page 43
Preliminary Spec.
Some contents are subject to change without notice.
Write Interrupted by Write / Read @BL=4
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0
ACT#1
Y
X
X
X
0
1
D0 D0 D0 D0
Y Y
0 0 0
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#0 READ#0
WRITE#0
Y
1
WRITE#1
Y
CL=3
Q0
Burst Write can be interrupted by Write or Read of any active bank.
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MITSUBISHI
ELECTRIC
43
Italic parameter indicates minimum case
17.Sep.1999
Page 44
Preliminary Spec.
Some contents are subject to change without notice.
Read Interrupted by Read / Write @BL=4 CL=3
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 WRITE#0
ACT#1
Y
X
X
X
0 0
1
Y Y
Y
0
Q0 Q0 Q0
Q0
READ#0 READ#0
READ#0
Y
1
READ#1
Y
0
Q0 Q0 Q1 Q1
blank to prevent bus contention
0
Q0 D0 D0
Burst Read can be interrupted by Read or Write of any active bank.
MIT-DS-0340-0.0
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Italic parameter indicates minimum case
17.Sep.1999
Page 45
Preliminary Spec.
Some contents are subject to change without notice.
Write Interrupted by Precharge @BL=4
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0
ACT#1
Y
X
X
X
0
1
D0 D0 D0 D0
Y
0
1
PRE#1
1 1
D1 D1 D1 D1 D1
PRE#0
WRITE#1
X
X
X
1
ACT#1 WRITE#1
Y
Burst Write is not interrupted
by Precharge of the other bank.
MIT-DS-0340-0.0
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Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
17.Sep.1999
Page 46
Preliminary Spec.
Some contents are subject to change without notice.
Read Interrupted by Precharge @BL=4 CL=3
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
/RAS
/CAS
CKE
DQM
A0-7
A10
X
X
tRRD
tRCD
tRP
tRCD
DQM read latency=2
Y
X
X
Y
X
X
Y
A8,9,11
BA0,1
DQ
MIT-DS-0340-0.0
X
0
ACT#0 READ#0
X
0
1
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
X
1
Q0 Q0 Q0
Q0
PRE#0
READ#1 ACT#1 READ#1
0
1
Q1 Q1
PRE#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
1
MITSUBISHI
1
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Page 47
Preliminary Spec.
Some contents are subject to change without notice.
Mode Register Setting
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
/CS
/RAS
/CAS
CKE
DQM
A0-7
A10
tRC
M
tRSC
tRCD
X
X
Y
A8,9,11
BA0,1
DQ
MIT-DS-0340-0.0
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
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X
0
0
ACT#0 WRITE#0
Italic parameter indicates minimum case
0
D0
D0 D0 D0
17.Sep.1999
Page 48
Preliminary Spec.
Some contents are subject to change without notice.
Auto-Refresh @BL=4
/WE
After tRC from Auto-Refresh,
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
tRCD
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
Auto-Refresh
X
X
X
0
ACT#0 WRITE#0
Y
0
D0
D0 D0 D0
Before Auto-Refresh,
all banks must be idle state.
MIT-DS-0340-0.0
all banks are idle state.
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Italic parameter indicates minimum case
17.Sep.1999
Page 49
Preliminary Spec.
Some contents are subject to change without notice.
Self-Refresh
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
tRC
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
tSRX
CKE must be low to maintain Self-Refresh
X
X
X
0
MIT-DS-0340-0.0
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
After tRC from Self-Refresh Exit,
all banks are idle state.
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Self-Refresh Exit ACT#0
Italic parameter indicates minimum case
17.Sep.1999
Page 50
Preliminary Spec.
Some contents are subject to change without notice.
DQM Write Mask @BL=4
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0 WRITE#0
Y
0 0
D0 D0 D0 D0
Y
masked masked
Y
0
D0 D0 D0
MIT-DS-0340-0.0
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Italic parameter indicates minimum case
17.Sep.1999
Page 51
Preliminary Spec.
Some contents are subject to change without notice.
DQM Read Mask @BL=4 CL=3
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 READ#0 READ#0
Y
0 0
Q0 Q0 Q0 Q0
Y
Y
0
masked
masked
Q0 Q0 Q0
MIT-DS-0340-0.0
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Italic parameter indicates minimum case
17.Sep.1999
Page 52
Preliminary Spec.
Some contents are subject to change without notice.
Power Down
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
Standby Power Down
CKE latency=1
X
X
X
0
Precharge All ACT#0
Active Power Down
MIT-DS-0340-0.0
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Italic parameter indicates minimum case
17.Sep.1999
Page 53
Preliminary Spec.
Some contents are subject to change without notice.
CLK Suspend @BL=4 CL=3
/WE
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
CKE
DQM
A0-7
A10
A8,9,11
BA0,1
DQ
CKE latency=1 CKE latency=1
X
X
X
0
ACT#0 WRITE#0 READ#0
Y
0 0
D0 D0 D0D0
Y
Q0 Q0 Q0 Q0
CLK suspendedCLK suspended
MIT-DS-0340-0.0
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Italic parameter indicates minimum case
17.Sep.1999
Page 54
Preliminary Spec.
Some contents are subject to change without notice.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
OUTLINE
31.75
20.00
4.00
6.00
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
MIT-DS-0340-0.0
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17.Sep.1999
Page 55
Preliminary Spec.
Some contents are subject to change without notice.
Mitsubishi Electric Corporation puts the maximum effort into making
non-flammable material or (iii) prevention against any malfunction or mishap.
1.These materials are intended as a reference to assist our customers in the
the products contained therein.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
Notes regarding these materials
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or ci rcuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
MIT-DS-0340-0.0
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17.Sep.1999
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