J
N-Channel 30-V(D-S) MOSFET, ESD Protection
ME4812/ME4812-G
GENERAL DESCRIPTION
The ME4812 is the N-Channel logic enhancement mode power field
effect transistors are produced using high cell density , DMOS trench
technology integrated Schottky diode. This high density process is
especially tailored to minimize on-state resistance. These devices
are particularly suited for low voltage application such as cellular
phone and notebook computer power management and other battery
powered circuits where high-side switching , and low in-line power
loss are needed in a very small outline surface mount package.
PIN CONFIGURATION
FEATURES
● Integrated Schottky diode
● RDS(ON)≦13mΩ@VGS=10V
● RDS(ON)≦21.5mΩ@VGS=4.5V
● Super high density cell design for extremely low RDS(ON)
● Exceptional on-resistance and maximum DC current
capability
APPLICATIONS
● Power Management in Note book
● Battery Powered System
● DC/DC Converter low side switching
● Load Switch
(SOP-8)
Top View
Ordering Information: ME4812 (Pb-free)
ME4812-G (Green product- Halogen free)
Absolute Maximum Ratings (TA=25℃ Unless Otherwise Noted)
Parameter Symbol Limit Unit
Drain-Source Voltage VDSS 30 V
Gate-Source Voltage VGSS ±20 V
TA=25℃ 11. 3 Continuous Drain
Current( T
Pulsed Drain Current IDM 45 A
Maximum Power Dissipation*
Operating Junction Temperature TJ -55 to 150 ℃
Thermal Resistance-Junction to Ambient*
J =150℃)*
T
A=70℃
TA=25℃ 2.5
TA=70℃
ID
PD
θJA 50
R
8.9
1.6
A
W
℃/W
* The device mounted on 1in
une, 2009-V er1.0
2
FR4 board with 2 oz copper
01
J
N-Channel 30-V(D-S) MOSFET, ESD Protection
Electrical Characteristics (TA =25℃ Unless Otherwise Specified)
ME4812/ME4812-G
Symbol Parameter Limit Min Typ Max Unit
STATIC
GS=0V, ID=250μA
BVDSS Drain-Source Breakdown Voltage
VGS(th) Gate Threshold Voltage
IGSS Gate Leakage Current VDS=0V, VGS=±16V ±10 uA
IDSS Zero Gate Voltage Drain Current VDS=30V, VGS=0V 1 mA
V
DS=VGS, ID=250μA
V
30 V
1 3 V
RDS(ON)
Drain-Source On-State Resistance
a
VSD Diode Forward Voltage IS=1A, VGS=0V 0.4 0.5 V
DYNAMIC
Qg Total Gate Charge(10V) VDS=15V, VGS=10V, ID=11.2A
Qg Total Gate Charge(4.5V)
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
Ciss Input capacitance 830
Coss Output Capacitance 280
Crss Reverse Transfer Capacitance
Rg Gate-Resistance VDS=0V, V
td(on)
tr
td(off)
tf
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
VGS=10V, ID= 11.2A 10 13
V
GS=4.5V, ID= 10A 17.5 21.5
19
9.7
4.2
4.6
14
14
39
4
V
DS=15V, VGS=4.5V,
I
D=11.2A
V
DS=15V, VGS=0V, f=1.0MHz
=0V, f=1MHz 1
GS
V
DD=15V, RL =15Ω
I
D=1A, VGEN=10V
R
G=3Ω
84
mΩ
nC
pF
Ω
ns
Notes: a. Pulse test: pulse width≦ 300us, duty cycle≦ 2%, Guaranteed by design, not subject to production testing.
b. Matsuki reserves the right to improve product design, functions and reliability without notice.
une, 2009-V er1.0
02
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N-Channel 30-V(D-S) MOSFET, ESD Protection
Typical Characteristics (TJ =25℃ Noted)
ME4812/ME4812-G
une, 2009-V er1.0
03
J
N-Channel 30-V(D-S) MOSFET, ESD Protection
Typical Characteristics (TJ =25℃ Noted)
ME4812/ME4812-G
une, 2009-V er1.0
04
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N-Channel 30-V(D-S) MOSFET, ESD Protection
ME4812/ME4812-G
SOP-8 Package Outline
DIM
A 1.35 1.75
A1 0.10 0.25
B 0.35 0.49
C 0.18 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BSC
H 5.80 6.20
L 0.40 1.25
MILLIMETERS (mm)
MIN MAX
une, 2009-V er1.0
θ 0° 7°
ote: 1. Refer to JEDEC MS-012AA.
2. Dimension “D” does not include mold flash, protrusions
or gate burrs . Mold flash, protrusions or gate burrs shall not
exceed 0.15 mm per side.
05
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