The MCT is an MOS Controlled Thyristor designed for s witching currents on and offby negative and positive pulsed control
of an insulated MOS gate. It is designed for use in motor controls, inverters, line switches and other power switching applications. The MCT is especially suited for resonant (zero
voltage or zero current switching) applications. The SCR like
forward drop greatly reduces conduction pow er loss .
MCTs allow the control of high power circuits with very small
amounts of input energy. They feature the high peak current
capability common to SCR type thyristors, and operate at
junction temperatures up to +150
This device features a discrete anti-parallel diode that shunts
current around the MCT in the reverse direction without
introducing carriers into the depletion region.
PART NUMBER INFORMATION
PART NUMBERPACKAGEBRAND
MCTV35P60F1DTO-247M35P60F1D
NOTE: When ordering, use the entire part number.
Formerly developmental type TA9789 (MCT) and TA49054
(diode).
FIGURE 11. BLOCKING VOLTAGE vs dv/dtFIGURE 12. SPIKE VOLTAGE vs di/dt (TYPICAL)
100
PULSE TEST
PULSE DURATION = 250µs
50
DUTY CYCLE < 2%
30
20
10
TJ = +150oC
TJ = -40oC
5
TJ = +25oC
3
2
, CATHODE-ANODE CURRENT (A)
KA
I
1
00.511.52
V
, ANODE-CATHODE VOLTAGE (V)
AK
FIGURE 13. DIODE CATHODE-ANODE CURRENT vs VOLTAGE
(TYPICAL)
1,000
500
t
RR
TJ = +25oC, di/dt = 100A/µs
300
t
200
A
100
50
30
20
, REVERSE RECOVERY TIMES (ns)
RR
t
10
0 10203040
I
KA
t
B
, CATHODE-ANODE CURRENT (A)
FIGURE 14. DIODE REVERSE RECOVERY TIMES vs CURRENT
(TYPICAL)
2-11
Page 5
Test Circuits
200µH
I
K
DUT
MCTV35P60F1D
V
G
1Ω
+
V
K
9V
-
+
500Ω
-
20V
10kΩ
+
V
A
C
S
DUT
9V
-
+
4.7kΩ
I
K
+
-
FIGURE 15. SWITCHING TEST CIRCUITFIGURE 16. V
MAXIMUM RISE AND FALL TIME OF VG IS 200ns
V
G
10%
-V
KA
90%
I
K
10%
t
D(OFF)I
t
FI
90%
t
D(ON)I
t
RI
FIGURE 17. SWITCHING TEST WAVEFORMS
Operating Frequency Information
Operating frequency information for a typical device
(Figure 9) is presented as a guide for estimating device performance for a specific application. Other typical frequency
vs cathode current (I
tion shown for a typical unit in Figures 3 to 8. The operating
frequency plot (Figure 9) of a typical device shows f
f
whichever is lower at each point. The information is
MAX2
based on measurements of a typical device and is bounded
by the maximum rated junction temperature.
f
is defined by f
MAX1
+t
D(OFF)I
deadtime (the denominator) has been arbitrarily
held to 10% of the on-state time for a 50% duty factor. Other
definitions are possible. t
the leading edge of the input pulse and the point where the
cathode current rises to 10% of its maximum value. t
is defined as the 90% point of the trailing edge of the input
pulse and the point where the cathode current falls to 90% of
) plots are possible using the informa-
AK
MAX1
MAX1
= 0.05 / (t
D(ON)I
D(ON)I+tD(OFF)I
is defined as the 10% point of
). t
or
D(ON)I
D(OFF)I
TEST CIRCUIT
SPIKE
V
G
di/dt
I
K
V
AK
FIGURE 18. V
V
SPIKE
V
TEST WAVEFORMS
SPIKE
TM
its maximum value. Device delay can establish an additional
frequency limiting condition for an application other than
T
JMAX.tD(OFF)I
is important when controlling output ripple
under a lightly loaded condition.
f
is defined by f
MAX2
allowable dissipation (P
R
. The sum of device switching and conduction losses
θ
JC
must not exceed P
. A 50% duty factor was used (Figure 9)
D
and the conduction losses (P
(V
AK•IAK
) / (duty factor/100). EONis defined as the sum of
=(PD-PC)/(EON+E
MAX2
) is defined by PD=(T
D
) are approximated by PC=
C
). The
OFF
JMAX-TC
)/
the instantaneous power loss starting at the leading edge of
the input pulse and ending at the point where the anodecathode voltage equals saturation voltage (V
AK=VTM
). E
OFF
is defined as the sum of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the
point where the cathode current equals zero (I
= 0).
K
2-12
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