Datasheet MCP3912 Datasheet
MCP3912
3V Four- Channel Analog Front End
Features:
• Four Synchronous Sampling 24-bit Resolution
Delta-Sigma A/D Converters
• 93.5 dB SINAD, -107 dBc Total Harmonic
Distortion (THD) (up to 35
SFDR for Each Channel
• Enables 0.1% Typical Active Power Measurement
Error over a 10,000:1 Dynamic Range
• Advanced Security Features:
- 16-Bit Cyclic Redundancy Check (CRC)
Checksum on All Communications for Secure
Data Transfers
- 16-Bit CRC Checksum and Interrupt Alert for
Register Map Configuration
- Register Map lock with 8-Bit Secure Key
• 2.7V-3.6V AV
• Programmable Data Rate up to 125 ksps:
- 4 MHz Maximum Sampling Frequency
- 16 MHz Maximum Master Clock
• Oversampling Ratio up to 4096
• Ultra-Low Power Shutdown Mode with < 10 µA
• -122 dB Crosstalk between Channels
• Low-Drift 1.2V Internal Voltage Reference:
9 ppm/°C
• Differential Voltage Reference Input Pins
• High Gain PGA on Each Channel (up to 32 V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Data Ready Pin for Easy
Synchronization
• Individual 24-Bit Digital Offset and Gain Error
Correction for Each Channel
• High-Speed 20 MHz SPI Interface with Mode 0,0
and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication Time with Dedicated 16/32-Bit
Modes
• Available in 28-Lead QFN and 28-Lead SSOP
Packages
• Extended Temperature Range: -40°C to +125°C
DD
, DV
th
Harmonic), 112 dBFS
DD
Description:
The MCP3912 is a 3V four-channel Analog Front End
(AFE) containing four synchronous sampling deltasigma, Analog-to-Digital Converters (ADC), four PGAs,
phase delay compensation block, low-drift internal
voltage reference, digital offset and gain error
calibration registers and high-speed 20 MHz
SPI-compatible serial interface.
The MCP3912 ADCs are fully configurable, with
features such as 16/24-bit resolution, Oversampling
Ratio (OSR) from 32 to 4096, gain from 1x to 32x,
independent Shutdown and Reset, dithering and autozeroing. The communication is largely simplified with 8bit commands, including various continuous read/write
modes and 16/24/32-bit data formats that can be
accessed by the Direct Memory Access (DMA) of an
8/16- or 32-bit MCU, and with the separate Data Ready
pin that can directly be connected to an Interrupt
Request (IRQ) input of an MCU.
The MCP3912 includes advanced security features to
secure the communications and the configuration
settings, such as a CRC-16 checksum on both serial
data outputs and static register map configuration. It
also includes a register-map lock through an 8-bit
secure key to stop unwanted write commands from
processing.
The MCP3912 is capable of interfacing with a variety of
voltage and current sensors, including shunts, current
transformers, Rogowski coils and Hall-effect sensors.
Applications:
• Polyphase Energy Meters
• Energy Metering and Power Measurement
• Automotive
• Portable Instrumentation
• Medical and Power Monitoring
• Audio/Voice Recognition
2014 Microchip Technology Inc. DS20005348A-page 1
MCP3912
2
26
3
4
5
6
10
11
12
13 14
18
17
16
15
28
27
25
CH0+
CH0-
CH1-
DV
DD
SDI
SDO
RESET
A
GND
EP
29
7
CH1+
CH2+
19
20
24
SCK
23
CS
OSC2
CH2-
22
OSC1/CLKI
1
8
9
NC
D
GND
AV
DD
D
GND
21
A
GND
REFIN-
D
GND
AV
DD
DV
DD
CH3-
CH3+
MCP3912
5x5 QFN*
* Includes Exposed Thermal Pad (EP); see Ta bl e 1- 3 .
REFIN+/
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
DD
CH0+
CH0-
CH3+
NC
NC
NC
NC
REFIN+/OUT
CH1-
CH1+
CH2+
CH2-
CH3-
DV
DD
RESET
SDI
D
GND
NC
DR
D
GND
A
GND
REFIN-
SDO
SCK
CS
OSC2
OSC1/CLKI
MCP3912
SSOP
OUT
DR
AMCLK
DMCLK/DRCLK
REFIN+/OUT
REFIN-
POR
AV
DD
Monitoring
Vref+Vref-
VREFEXT
Voltage
Reference
Vref
+
-
Xtal Oscillator
MCLK
OSC1
OSC2
Digital SPI
Interface
Clock
Generation
DMCLK
OSR<2:0>
PRE<1:0>
ANALOG DIGITAL
SDO
SDI
SCK
DR
RESET
CS
A
GND
D
GND
AV
DD
DV
DD
CH0+
CH0-
-
+
PGA
OSR/2-
PHASE1 <11:0>
MOD<3:0>
Modulator
+
OFFCAL_CH0
<23:0>
GAINCAL_CH0
<23:0>
X
DATA_CH0<23:0>
SINC3+
SINC
1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH1+
CH1-
-
+
PGA
OSR/2
MOD<7:4>
Modulator
+
OFFCAL_CH1
<23:0>
GAINCAL_CH1
<23:0>
X
DATA_CH1<23:0>
SINC3+
SINC
1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH2+
CH2-
-
+
PGA
OSR/2-
PHASE1 <23:12>
MOD<11:8>
Modulator
OFFCAL_CH2
<23:0>
GAINCAL_CH2
<23:0>
X
DATA_CH2<23:0>
SINC3+
SINC
1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH3+
CH3-
-
+
PGA
OSR/2
MOD<15:12>
Modulator
OFFCAL_CH3
<23:0>
GAINCAL_CH3
<23:0>
X
DATA_CH3<23:0>
SINC3+
SINC
1
Phase
Shifter
Offset
Cal.
Gain
Cal.
POR
DV
DD
Monitoring
Package Type
Functional Block Diagram
DS20005348A-page 2 2014 Microchip Technology Inc.
MCP3912
1.0 ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other condi-
Absolute Maximum Ratings †
VDD..................................................................... -0.3V to 4.0V
Digital inputs and outputs w.r.t. A
Analog input w.r.t. A
input w.r.t. A
V
REF
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD on all pins (HBM,MM) ....................................4 kV, 300V
.........................................-2V to +2V
GND
............................... -0.6V to VDD +0.6V
GND
................. -0.3V to 4.0V
GND
tions, above those indicated in the operational listings
of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
1.1 Electrical Specifications
TABLE 1-1: ANALOG SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AV
PRE<1:0> = 00
= -40°C to +125°C; VIN= -0.5 dBFS @ 50/60 Hz on all channels.
T
A
; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER<1:0> = 11; BOOST<1:0> = 10, V
DD = DVDD
Characteristic Sym. Min. Typ. Max. Units Conditions
ADC Performance
Resolution
24 — — bits OSR = 256 or greater
(No missing codes)
Sampling Frequency f
Output Data Rate f
Analog Input Absolute
(DMCLK) — 1 4 MHz For maximum condition,
S
(DRCLK) — 4 125 ksps For maximum condition,
D
CHn+/- -1 — +1 V All analog input channels,
Voltage on CHn+/- pins,
n between 0 and 3
Analog Input
I
IN
— +/-1 — nA RESET<3:0> = 1111,
Leakage Current
Differential Input
-CHn-) -600/GAIN — +600/GAIN mV V
(CH
n+
Voltage Range
Offset Error V
OS
-1 0.2 1 mV Note 5
Offset Error Drift — 0.5 — µV/°C
Gain Error GE -5 — +5 % Note 5
Gain Error Drift — 1 — ppm/°C
Note 1:
Dynamic Performance specified at -0.5 dB below the maximum differential input value,
=1.2VPP= 424 mV
V
IN
This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following configuration bit settings apply: SHUTDOWN<3:0> = 0000
RESET<3:0> = 0000
3: For these operating currents, the following configuration bit settings apply: SHUTDOWN<3:0> = 1111
CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all channels
(see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical
performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2V can be applied continuously to
the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in
Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler
settings (PRE<1:0>) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
8: This parameter is established by characterization and not 100% tested.
@ 50/60 Hz, V
RMS
= 1.2V. See Section 4.0 “Terminology And Formulas” for definition.
REF
, VREFEXT = 0, CLKEXT = 0.
= 3V, MCLK = 4 MHz;
BOOST<1:0> = 11
BOOST<1:0> = 11,
OSR = 32
measured to A
GND
MCLK running continuously
=1.2V,
REF
proportional to V
REF
=0V;
CM
,
, VREFEXT = 1,
2014 Microchip Technology Inc. DS20005348A-page 3
MCP3912
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AV
PRE<1:0> = 00
= -40°C to +125°C; VIN= -0.5 dBFS @ 50/60 Hz on all channels.
T
A
; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER<1:0> = 11; BOOST<1:0> = 10, V
DD = DVDD
Characteristic Sym. Min. Typ. Max. Units Conditions
Integral Nonlinearity INL — 5 — ppm
Measurement Error ME — 0.1 — % Measured with a 10,000:1
Differential Input
Impedance
Z
IN
232 — — k G = 1, proportional to 1/AMCLK
142 — — k G = 2, proportional to 1/AMCLK
72 — — k G = 4, proportional to 1/AMCLK
38 — — k G = 8, proportional to 1/AMCLK
36 — — k G = 16, proportional to 1/AMCLK
33 — — k G = 32, proportional to 1/AMCLK
Signal-to-Noise and
SINAD 92 93.5 — dB
Distortion Ratio (Note 1)
Total Harmonic Distortion
THD — -107 -103 dBc Includes the first 35 harmonics
(Note 1)
Signal-to-Noise Ratio
SNR 92 94 — dB
(Note 1)
Spurious Free Dynamic
SFDR — 112 — dBFS
Range (Note 1)
Crosstalk (50, 60 Hz) CTALK — -122 — dB Note 4
AC Power
AC PSRR — -73 — dB AVDD=DVDD= 3V + 0.6VPP
Supply Rejection
DC Power
DC PSRR — -73 — dB AV
Supply Rejection
DC Common
DC CMRR — -100 — dB V
Mode Rejection
Note 1:
Dynamic Performance specified at -0.5 dB below the maximum differential input value,
V
=1.2VPP= 424 mV
IN
This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following configuration bit settings apply: SHUTDOWN<3:0> = 0000
RESET<3:0> = 0000
3: For these operating currents, the following configuration bit settings apply: SHUTDOWN<3:0> = 1111
CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all channels
(see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical
performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2V can be applied continuously to
the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in
Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler
settings (PRE<1:0>) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
8: This parameter is established by characterization and not 100% tested.
@ 50/60 Hz, V
RMS
= 1.2V. See Section 4.0 “Terminology And Formulas” for definition.
REF
, VREFEXT = 0, CLKEXT = 0.
= 3V, MCLK = 4 MHz;
=0V;
CM
dynamic range
(from 600 mV
=DVDD=3V,
AV
DD
Peak
to 60 µV
measurement points averaging
time: 20 seconds, measured on
each channel pair (CH0/1,
CH2/3)
50/60 Hz, 100/120 Hz
= DVDD = 2.7V to 3.6V
DD
from -1V to +1V
CM
,
, VREFEXT = 1,
Peak
),
DS20005348A-page 4 2014 Microchip Technology Inc.
MCP3912
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AV
PRE<1:0> = 00
= -40°C to +125°C; VIN= -0.5 dBFS @ 50/60 Hz on all channels.
T
A
; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER<1:0> = 11; BOOST<1:0> = 10, V
DD = DVDD
Characteristic Sym. Min. Typ. Max. Units Conditions
Internal Voltage Reference
To le r a nc e V
REF
Temperature Coefficient TCV
Output Impedance ZOUTV
Internal Voltage Reference
AI
DDVREF
REF
REF
1.176 1.2 1.224 V VREFEXT = 0,
— 9 — ppm/°C TA = -40°C to +125°C,
—0.6— k VREFEXT = 0
— 54 — µA VREFEXT = 0,
Operating Current
V oltage Reference Input
Input Capacitance — — 10 pF
Differential Input Voltage
Range (V
REF+
– V
REF-
)
Absolute Voltage on
REFIN+ pin
Absolute Voltage
V
V
V
REF
REF+
REF-
1.1 — 1.3 V VREFEXT = 1
V
REF-
+1.1
—V
REF-
+1.3
-0.1 — +0.1 V REFIN- should be connected to
REFIN- pin
Master Clock Input
Master Clock Input
f
MCLK
— — 20 MHz CLKEXT = 1, (Note 7)
Frequency Range
Crystal Oscillator
f
XTAL
1 — 20 MHz CLKEXT = 0, (Note 7)
Operating Frequency
Range
Analog Master Clock AMCLK — — 16 MHz (Note 7)
Crystal Oscillator
DIDDXTAL — 80 — µA CLKEXT = 0
Operating Current
Power Supply
Operating Voltage, Analog AV
Operating Voltage, Digital DV
Note 1:
Dynamic Performance specified at -0.5 dB below the maximum differential input value,
V
=1.2VPP= 424 mV
IN
This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following configuration bit settings apply: SHUTDOWN<3:0> = 0000
RESET<3:0> = 0000
3: For these operating currents, the following configuration bit settings apply: SHUTDOWN<3:0> = 1111
CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all channels
(see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical
performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2V can be applied continuously to
the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in
Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler
settings (PRE<1:0>) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
8: This parameter is established by characterization and not 100% tested.
DD
DD
@ 50/60 Hz, V
RMS
, VREFEXT = 0, CLKEXT = 0.
2.7 — 3.6 V
2.7 — 3.6 V
= 1.2V. See Section 4.0 “Terminology And Formulas” for definition.
REF
= 3V, MCLK = 4 MHz;
TA = +25°C only
VREFEXT = 0,
VREFCAL<7:0> = 0x50
SHUTDOWN<3:0> = 1111
V VREFEXT = 1
A
when VREFEXT = 0
GND
=0V;
CM
,
, VREFEXT = 1,
2014 Microchip Technology Inc. DS20005348A-page 5
MCP3912
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AV
PRE<1:0> = 00
= -40°C to +125°C; VIN= -0.5 dBFS @ 50/60 Hz on all channels.
T
A
; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER<1:0> = 11; BOOST<1:0> = 10, V
DD = DVDD
Characteristic Sym. Min. Typ. Max. Units Conditions
Operating Current, Analog
(Note 2)
I
DD,A
— 2.8 4 mA BOOST<1:0> = 00
— 3.4 4.5 mA BOOST<1:0> = 01
— 4.7 6.4 mA BOOST<1:0> = 10
— 8.1 11.8 mA BOOST<1:0> = 11
Operating Current, Digital I
DD,D
— 0.28 0.6 mA MCLK = 4 MHz,
— 1.1 — mA MCLK = 16 MHz,
Shutdown Current, Analog I
Shutdown Current, Digital I
Pull-down Current on
DDS,A
DDS,D
I
OSC2
—0.01 2 µAAV
—0.01 4 µADV
— 35 — µA CLKEXT = 1
OSC2 Pin (External Clock
mode only)
Note 1:
Dynamic Performance specified at -0.5 dB below the maximum differential input value,
=1.2VPP= 424 mV
V
IN
This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following configuration bit settings apply: SHUTDOWN<3:0> = 0000
RESET<3:0> = 0000
3: For these operating currents, the following configuration bit settings apply: SHUTDOWN<3:0> = 1111
CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all channels
(see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical
performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2V can be applied continuously to
the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in
Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler
settings (PRE<1:0>) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
8: This parameter is established by characterization and not 100% tested.
@ 50/60 Hz, V
RMS
= 1.2V. See Section 4.0 “Terminology And Formulas” for definition.
REF
, VREFEXT = 0, CLKEXT = 0.
= 3V, MCLK = 4 MHz;
proportional to MCLK (Note 2)
proportional to MCLK (Note 2)
pin only (Note 3) (Note 8)
DD
pin only (Note 3) (Note 8)
DD
=0V;
CM
,
, VREFEXT = 1,
1.2 Serial Interface Characteristics
TABLE 1-2: SERIAL DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at DV
T
= -40°C to +125°C, C
A
= 30 pF, applies to all digital I/O.
LOAD
Characteristic Sym. Min. Typ. Max. Units Conditions
High-Level Input Voltage V
Low-Level Input Voltage V
Input Leakage Current I
Output Leakage Current I
Hysteresis Of
V
IH
IL
LI
LO
HYS
0.7 DV
DD
— — V Schmitt-Triggered
——0.3 DVDDV Schmitt-Triggered
——±1µA
——±1µA
—500— mVDV
Schmitt-Trigger Inputs
Low-Level Output Voltage V
OL
——0.2DVDDVIOL = +1.7 mA
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.
DS20005348A-page 6 2014 Microchip Technology Inc.
= 2.7 to 3.6 V,
DD
= DVDD,
CS
= D
V
IN
GND
CS
= DVDD,
V
= D
OUT
= 3.3V only, Note 2
DD
to DV
GND
DD
or DV
DD
TABLE 1-2: SERIAL DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at DV
= -40°C to +125°C, C
T
A
= 30 pF, applies to all digital I/O.
LOAD
Characteristic Sym. Min. Typ. Max. Units Conditions
High-Level Output Voltage V
Internal Capacitance
C
OH
INT
0.75 DV
—— VIOH = -1.7 mA
DD
——7 pFT
(All Inputs And Outputs)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.
= 2.7 to 3.6 V,
DD
= +25°C, SCK = 1.0 MHz,
A
DV
DD
MCP3912
=3.3V (Note 1)
2014 Microchip Technology Inc. DS20005348A-page 7
MCP3912
TABLE 1-3: SERIAL AC CHARACTERISTICS TABLE
Electrical Specifications: Unless otherwise indicated, all parameters apply at DV
= -40°C to +125°C, GAIN = 1, C
T
A
LOAD
= 30 pF
Characteristic Sym. Min. Typ. Max. Units Conditions
Serial Clock Frequency
CS Setup Time
CS
Hold Time
CS Disable Time
Data Setup Time
Data Hold Time
Serial Clock High Time
Serial Clock Low Time
Serial Clock Delay Time
Serial Clock Enable Time
Output Valid from SCK Low
Output Hold Time
Output Disable Time
Reset Pulse Width (RESET)
Data Transfer Time to DR
f
SCK
t
CSS
t
CSH
t
CSD
t
SU
t
HD
t
HI
t
LO
t
CLD
t
CLE
t
DO
t
HO
t
DIS
t
MCLR
t
DODR
—— 20MHz
25 — — ns
50 — — ns
50 — — ns
5— —ns
10 — — ns
20 — — ns
20 — — ns
50 — — ns
50 — — ns
— — 25 ns
0— —nsNote 1
— — 25 ns Note 1
100 — — ns
— — 25 ns Note 2
(Data Ready)
Data Ready Pulse Low Time
t
DRP
— 1/(2 x DMCLK) — µs
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.
TABLE 1-4: TEMPERATURE SPECIFICATIONS TABLE
Electrical Specifications: Unless otherwise indicated, all parameters apply at AV
Parameters Sym. Min. Typ. Max. Units. Conditions
Temperature Ranges
Operating Temperature Range T
Storage Temperature Range T
Thermal Package Resistances
Thermal Resistance, 28L SSOP
Thermal Resistance, 28L QFN
Note 1: The internal junction temperature (T
-40 — +125 °C Note 1
A
-65 — +150 °C
A
JA
JA
—80 — °C/W
—41 — °C/W
) must not exceed the absolute maximum specification of +150°C.
J
= 2.7 to 3.6 V,
DD
= 2.7 to 3.6V, DVDD = 2.7 to 3.6V.
DD
DS20005348A-page 8 2014 Microchip Technology Inc.
FIGURE 1-1: Serial Output Timing Diagram.
t
CSH
t
DIS
t
HI
t
LO
f
SCK
CS
SCK
SDO
MSB out
LSB out
SDI
Mode 1,1
Mode 0,0
t
HO
t
DO
DON’T CARE
CS
SCK
SDI
LSB in
MSB in
Mode 1,1
Mode 0,0
t
CSS
t
SU
t
HD
t
CSD
t
CSH
t
CLD
t
CLE
SDO
HIGH Z
t
HI
t
LO
f
SCK
DR
SCK
t
DRP
SDO
1/f
D
t
DODR
CS
V
IH
Waveform for t
DIS
HI-Z
90%
10%
t
DIS
SDO
SCK
SDO
t
DO
Timing Waveform for t
DO
MCP3912
FIGURE 1-2: Serial Input Timing Diagram.
FIGURE 1-3: Data Ready Pulse / Sampling Timing Diagram.
H
FIGURE 1-4: Timing Diagrams, continued.
2014 Microchip Technology Inc. DS20005348A-page 9
MCP3912
-
-120
-100
-80
-60
-40
-20
0
Amplitude (dB)
Vin= -0.5 dBFS @ 60 Hz
f
D
= 3.9 ksps
OSR = 256
Dithering = Off
16 ksamples FFT
-180
-160
140
0 500 1000 1500 2000
Frequency (Hz)
0
Vin= -60 dBFS @ 60 Hz
-40
-
20
)
f
D
= 3.9 ksps
OSR = 256
Dithering = Off
-80
-60
de (d
B
16 ksamples FFT
-120
-100
mplitu
-140
A
-180
-
160
0
500
1000
1500
2000
Frequency (Hz)
-
-120
-100
-80
-60
-40
-20
0
Amplitude (dB)
Vin= -0.5 dBFS @ 60 Hz
f
D
= 3.9 ksps
OSR = 256
Dithering = Maximum
16 ksamples FFT
-180
-160
140
0 500 1000 1500 2000
Frequency (Hz)
0
-40
-20
0
Vin= -60 dBFS @ 60 Hz
f
D
= 3.9 ksps
OSR = 256
-80
-60
e (dB
)
Dithering = Maximum
16 ksamples FFT
-120
-100
plitu
d
-160
-140
A
m
-180
0 500 1000 1500 2000
Frequency (Hz)
-1.0%
-0.5%
0.0%
0.5%
1.0%
0.01 0.1 1 10 100 1000
Measurement Error (%)
-1.0%
-0.5%
0.0%
0.5%
1.0%
0.01 0.1 1 10 100 1000
% Error Channel 0, 1
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, AV
= 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
DD
OSR = 256; GAIN = 1; Dithering = Maximum; V
BOOST<1:0> = 10.
FIGURE 2-1: Spectral Response.
= -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1;
IN
FIGURE 2-4: Spectral Response .
% Error Channel 0, 1
FIGURE 2-2: Spectral Response.
FIGURE 2-3: Spectral Response.
DS20005348A-page 10 2014 Microchip Technology Inc.
Current Channel Input Amplitude (mV
FIGURE 2-5: Measurement Error with 1-Point Calibration.
Measurement Error (%)
Current Channel Input Amplitude (mV
FIGURE 2-6: Measurement Error with 2-Point Calibration.
Peak
Peak
)
)
MCP3912
rrenc
e
Occu
ncy o
f
requ
e
-108.2 -107.8 -107.4 -107.0 -106.6 -106.2
F
Total Harmonic Distortion (
-
dBc)
uency of Occurrence
111.7 112.3 112.9 113.5 114.1 114.7 115.3 115.9
Fre
q
Spurious Free Dynamic Range (dBFS)
rrenc
e
f Occ
u
ency
o
Frequ
93.3 93.4 93.5 93.6 93.7 93.8
Signal to Noise and Distortion (dB)
ency of Occurrence
Standar deviation = 78 LSB
Noise = 7.4ȝVrms
16 ksamples
448
481
514
548
581
614
647
680
714
747
780
813
846
880
913
946
979
1,012
1,046
1,079
1,112
Freq
u
Output Noise (LSB)
-120
-115
-110
-105
-100
-95
-90
al Harmonic Distortion
(dBc)
Dithering=Maximum
Dithering=Medium
Dithering=Minimum
Dithering=Off
-130
-125
32 64 128 256 512 1024 2048 4096
Tot
Oversampling Ratio (OSR)
110
100
105
nd
B)
90
95
oise a
atio (
d
75
80
85
al-to-
N
rtion
R
=
65
70
Sign
Dist
o
Dithering Maximu
m
Dithering=Medium
60
32 64 128 256 512 1024 2048 4096
Oversampling Ratio (OSR)
Note: Unless otherwise indicated, AV
= 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
DD
OSR = 256; GAIN = 1; Dithering = Maximum; V
BOOST<1:0> = 10.
FIGURE 2-7: THD Repeatability Histogram.
= -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1;
IN
FIGURE 2-10: Output Noise Histogram.
FIGURE 2-8: Spurious Free Dynamic
Range Repeatability Histogram.
FIGURE 2-9: SINAD Repeatability Histogram.
2014 Microchip Technology Inc. DS20005348A-page 11
FIGURE 2-11: THD vs.OSR.
FIGURE 2-12: SINAD vs. OSR.
MCP3912
110
100
105
dB)
90
95
Ratio
(
80
85
Noise
=
65
70
75
nal-to
-
Dithering Maximum
Dithering=Medium
Dithering=Minimum
Dithering=Off
60
32 64 128 256 512 1024 2048 4096
Sig
O
versamplingRatio
(OSR)
120
115
amic
105
110
e Dy
n
dBFS
)
95
100
us Fr
e
ange
(
Dithering=Maximum
85
90
Spuri
o
R
g
Dithering=Medium
Dithering=Minimum
=
80
32 64 128 256 512 1024 2048 4096
Dithering Off
O
versamplingRatio
(OSR)
-95
-90
-85
-80
-75
-70
-65
-60
l Harmonic Distortion
(dB)
Boost = 00
Boost = 01
Boost = 10
Boost = 11
-110
-105
-
100
2 4 6 8 10 12 14 16 18 20
Tot
a
MCLK Frequency (MHz)
100
90
95
and
85
-Nois
e
ortion
dB)
75
80
nal-t
o
Dis
t
(
65
70
Si
g
Boost = 00
Boost = 01
60
2 4 6 8 10 12 14 16 18
Boost = 10
MCLK Frequency (MHz)
100
90
95
io
85
ise Ra
t
75
80
-to-No
(dB
)
65
70
Signal
Boost = 00
Boost = 01
60
2 4 6 8 1012141618
Boost = 10
Boost = 11
MCLK Frequency (MHz)
120
110
amic
100
e Dyn
ge
S)
90
us Fr
e
Ran
(dB
F
70
80
Spuri
o
Boost = 00
Boost = 01
Boost = 10
60
Boost = 11
24681012141618
20
MCLK Frequency (MHz)
Note: Unless otherwise indicated, AV
= 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
DD
OSR = 256; GAIN = 1; Dithering = Maximum; V
BOOST<1:0> = 10.
L
FIGURE 2-13: SNR vs.OSR.
= -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1;
IN
FIGURE 2-16: SI NAD vs. MCLK .
FIGURE 2-14: SFDR vs. OSR.
FIGURE 2-15: THD vs. MCLK.
DS20005348A-page 12 2014 Microchip Technology Inc.
FIGURE 2-17: SNR vs. MCLK.
FIGURE 2-18: SFDR vs. MCLK.
MCP3912
-140
-120
-100
-80
-60
-40
-20
0
Total Harmonic DistorWion (dB)
0
20
40
60
80
100
120
Ratio (dB)
0
20
40
60
80
100
120
0
20
40
60
80
100
120
140
SpuriousFree Dynamic Range
(dBFS)
-120
-100
-80
-60
-40
-20
0.001 0.01 0.1 1 10 100 1000
-20
0
20
40
60
80
100
0.001 0.01 0.1 1 10 100 1000
Signal-to-Noise and Distortion
Ratio (dB)
Note: Unless otherwise indicated, AV
= 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
DD
OSR = 256; GAIN = 1; Dithering = Maximum; V
BOOST<1:0> = 10.
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
12481632
Gain (V/V)
FIGURE 2-19: THD vs. GAIN.
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
Signal-to-Noise and Distortion
OSR = 2048
OSR = 4096
12481632
Gain (V/V)
FIGURE 2-20: SINAD vs. GAIN .
= -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1;
IN
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
12481632
Gain (V/V)
FIGURE 2-22: SFDR vs. GAIN.
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
Total Harmonic Distortion (dB)
Input Signal Amplitude (mVPK)
FIGURE 2-23: THD vs. Input Signal Amplitude.
Signal-to-Noise Ratio (dB)
12481632
FIGURE 2-21: SNR vs. GAIN.
2014 Microchip Technology Inc. DS20005348A-page 13
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
Input Signal Amplitude (mVPK)
FIGURE 2-24: SI NAD vs. Input Si gna l Amplitude.
MCP3912
-20
0
20
40
60
80
100
0.001 0.01 0.1 1 10 100 1000
Signal-to-Noise Ratio (dB)
0
20
40
60
80
100
120
140
0.001 0.01 0.1 1 10 100 1000
SpuriousFree Dyanmic Range
(dBFS)
0
20
40
60
80
100
120
10 100 1000 10000 100000
Signal-to-Noise and Distortion
Ratio (dB)
-120
-100
-80
-60
-40
-20
-50 -25 0 25 50 75 100 125
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125
Signal-to-Noise and Distortion
Ratio (dB)
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125
Note: Unless otherwise indicated, AV
= 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
DD
OSR = 256; GAIN = 1; Dithering = Maximum; V
BOOST<1:0> = 10.
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
Input Signal Amplitude (mVPK)
FIGURE 2-25: SNR vs. Input Signal Amplitude.
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
= -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1;
IN
0
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
Total Harmonic Distortion (dB)
Temperature (°C)
FIGURE 2-28: THD vs. Temperature.
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
Input Signal Amplitude (mVPK)
FIGURE 2-26: SFDR vs. Input Signal Amplitude.
Signal Frequency (Hz)
FIGURE 2-27: SINAD vs. Input Frequency.
DS20005348A-page 14 2014 Microchip Technology Inc.
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
Temperature (°C)
FIGURE 2-29: SI NAD vs. Temperature.
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
Signal-to-Noise Ratio (dB)
GAIN = 32x
Temperature (°C)
FIGURE 2-30: SNR vs. Temperature.
MCP3912
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
SpuriousFree Dyanmic Range
(dBFS)
-140
-120
-100
-80
-60
-40
-20
0123
28LD SSOP
28LD QFN
* All other channels at maximum amplitude V
IN
=600mVPK@60Hz
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-40 -20 0 20 40 60 80 100 120
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-40-20 0 20406080100120
Channel Offset (µV)
Temperature (°C)
Channel 0
Channel 1
Channel 2
Channel 3
-5
-3
-1
1
3
5
7
9
-40 -20 0 20 40 60 80 100 120
Gain Error (%)
1.197
1.198
1.199
1.2
-40 -20 0 20 40 60 80 100 120 140
Internal Voltage Reference (V)
Note: Unless otherwise indicated, AV
= 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
DD
OSR = 256; GAIN = 1; Dithering = Maximum; V
BOOST<1:0> = 10.
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
Temperature (°C)
FIGURE 2-31: SFDR vs. T emperature.
0
Crosstalk (dB)
= -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1;
IN
FIGURE 2-34: Channel Offset Matching vs. Temperature.
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
FIGURE 2-32: Crosstalk vs. Measured Channel.
Offset (µV)
FIGURE 2-33: Offset vs. Temperature vs. Gain.
2014 Microchip Technology Inc. DS20005348A-page 15
Measured Channel*
Temperature (°C)
Temperature (°C)
FIGURE 2-35: Gain Error vs. Temperature vs. Gain.
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
Temperature (°C)
FIGURE 2-36: Internal Voltage Reference vs. Temperature.
MCP3912
1.1961
1.1962
1.1963
1.1964
1.1965
1.1966
1.1967
1.1968
1.1969
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
-10
-8
-6
-4
-2
0
2
4
6
8
10
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Integral NonLinearity Error
(ppm)
-10
-8
-6
-4
-2
0
2
4
6
8
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Integral NonLinearity Error
(ppm)
0
2
4
6
8
10
12
14
246810121416182022242628
I
DD
(mA)
MCLK (MHz)
AIDD Boost =0.5x
AIDD Boost =0.66x
AIDD Boost =1x
AIDD Boost =2x
DIDD
Note: Unless otherwise indicated, AV
OSR = 256; GAIN = 1; Dithering = Maximum; V
= 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
DD
= -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1;
IN
BOOST<1:0> = 10.
Internal Voltage Reference (V)
AVDD(V)
FIGURE 2-37: Internal Voltage Reference vs. Supply Voltage.
FIGURE 2-40: Operating Current vs. MCLK
Frequency vs. Boost, V
DD
= 3V.
Input Voltage (V)
FIGURE 2-38: Integral Nonlinearity (Dithering Maximum).
10
Input Voltage (V)
FIGURE 2-39: Integral Nonlinearity (Dithering Off).
DS20005348A-page 16 2014 Microchip Technology Inc.
NOTES:
MCP3912
2014 Microchip Technology Inc. DS20005348A-page 17
MCP3912
3.0 PIN DESCRIPTION
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: FOUR CHANNEL MCP3912 PIN FUNCTION TABLE
MCP3912
SSOP
125, 11 AVDDAnalog Power Supply Pin
2 27 CH0+ Noninverting Analog Input Pin for Channel 0
3 28 CH0- Inverting Analog Input Pin for Channel 0
4 29 CH1- Inverting Analog Input Pin for Channel 1
5 2 CH1+ Noninverting Analog Input Pin for Channel 1
6 3 CH2+ Noninverting Analog Input Pin for Channel 2
7 4 CH2- Inverting Analog Input Pin for Channel 2
8 5 CH3- Inverting Analog Input Pin for Channel 3
9 6 CH3+ Noninverting Analog Input Pin for Channel 3
10, 11, 12,
13, 19
14 8 REFIN+/OUT Noninverting Voltage Reference Input and Internal Reference Output Pin
15 9 REFIN- Inverting Voltage Reference Input Pin
16 10, 26 A
17, 20 13, 15, 23 D
18 14
21 16 OSC1/CLKI Oscillator Crystal Connection Pin or External Clock Input Pin
22 17 OSC2 Oscillator Crystal Connection Pin
23 18
24 19 SCK Serial Interface Clock Input Pin for SPI
25 20 SDO Serial Interface Data Output Pin
26 21 SDI Serial Interface Data Input Pin
27 22
28 12, 14 DV
— 29 EP Exposed Thermal Pad. Must be connected to A
MCP3912
QFN
7 NC No Connect (for better EMI results connect to A
Symbol Function
GND
GND
DR
CS
RESET
DD
Analog Ground Pin, Return Path for Internal Analog Circuitry
Digital Ground Pin, Return Path for Internal Digital Circuitry
Data Ready Signal Output Pin
Serial Interface Chip Select Input Pin
Master Reset Logic Input Pin
Digital Power Supply Pin
)
GND
or floating.
GND
DS20005348A-page 18 2014 Microchip Technology Inc.
MCP3912
3.1 Analog Power Supply (AVDD)
AVDD is the power supply voltage for the analog
circuitry within the MCP3912. It is distributed on several
pins (pins 11 and 25 in the QFN-28 package, one pin
only in the SSOP-28 package). For optimal
performance, connect these pins together using a star
connection, and connect the appropriate bypass
capacitors (typically a 10 µF in parallel with a 0.1 µF
ceramic). AV
and 3.6V for specified operation.
To ensure proper functionality of the device, at least
one of these pins must be properly connected. To
ensure optimal performance of the device, all the pins
must be properly connected. If any of these pins are left
floating, the accuracy and noise specifications are not
ensured.
should be maintained between 2.7V
DD
3.2 ADC Differential Analog Inputs (CHn+/CHn-)
The CHn+/- pins (n comprised between 0 and 3) are
the four fully-differential analog voltage inputs for the
delta-sigma ADCs.
The linear and specified region of the channels is
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±600 mV/GAIN with
= 1.2V.
V
REF
The maximum absolute voltage, with respect to A
for each CHn+/- input pin is ±1V with no distortion, and
±2V with no breaking after continuous voltage. This
maximum absolute voltage is not proportional to the
V
voltage.
REF
GND
3.3 Noninverting Reference Input, Internal Reference Output (REFIN+/OUT)
This pin is the noninverting side of the differential
voltage reference input for all ADCs or the internal
voltage reference output.
When VREFEXT = 1, an external voltage reference
source can be used, and the internal voltage reference
is disabled. When using an external differential voltage
reference, it should be connected to its V
When using an external single-ended reference, it
should be connected to this pin.
When VREFEXT = 0, the internal voltage reference is
enabled and connected to this pin through a switch.
This voltage reference has minimal drive capability and
thus needs proper buffering and bypass capacitances
(a 0.1 µF ceramic capacitor is sufficient in most cases)
if used as a voltage source.
REF+
pin.
If the voltage reference is only used as an internal
, adding bypass capacitance on REFIN+/OUT is
V
REF
not necessary for keeping ADC accuracy, but a minimal
0.1 µF ceramic capacitance can be connected to avoid
EMI/EMC susceptibility issues due to the antenna
created by the REFIN+/OUT pin if left floating.
3.4 Inverting Reference Input (REFIN-)
This pin is the inverting side of the differential voltage
reference input for all ADCs. When using an external
differential voltage reference, it should be connected to
its V
voltage reference, or when VREFEXT = 0 (default) and
using the internal voltage reference, the pin should be
directly connected to A
3.5 Analog Ground (A
A
GND
circuitry within the MCP3912. It is distributed on several
pins (pins 10 and 26 in the QFN-28 package, one pin
only in the SSOP-28 package). For optimal
performance, it is recommended to connect these pins
together using a star connection, and to connect it to
the same ground node voltage as D
connection.
At least one of these pins needs to be properly
connected to ensure proper functionality of the device.
,
All of these pins need to be properly connected to
ensure optimal performance of the device. If any of
these pins are left floating, the accuracy and noise
specifications are not ensured. If an analog ground
plane is available, it is recommended that these pins be
tied to this plane of the PCB. This plane should also
reference all other analog circuitry in the system.
3.6 Digital Ground (D
D
GND
circuitry within the MCP3912. It is distributed on several
pins (pins 13, 15 and 23 in the QFN-28 package, two
pins only in the SSOP-28 package). For optimal
performance, connect these pins together using a star
connection and connect it to the same ground node
voltage as A
At least one of these pins needs to be properly
connected to ensure proper functionality of the device.
All of these pins need to be properly connected to
ensure optimal performance of the device. If any of
these pins are left floating, the accuracy and noise
specifications are not ensured. If a digital ground plane
is available, it is recommended that these pins be tied
to this plane of the Printed Circuit Board (PCB). This
plane should also reference all other digital circuitry in
the system.
pin. When using an external single-ended
REF-
.
GND
)
GND
is the ground reference voltage for the analog
with a star
GND
)
GND
is the ground reference voltage for the digital
with a star connection.
GND
2014 Microchip Technology Inc. DS20005348A-page 19
MCP3912
3.7 Data Ready Output (DR)
The Data Ready pin indicates if a new conversion
result is ready to be read. The default state of this pin
is logic high when DR_HIZ
when DR_HIZ
finished, a logic low pulse will take place on the data
ready pin to indicate the conversion result is ready as
an interrupt. This pulse is synchronous with the master
clock and has a defined and constant width.
The Data Ready pin is independent of the SPI interface
and acts like an interrupt output. The Data Ready pin
state is not latched, and the pulse width (and period)
are both determined by the MCLK frequency,
over-sampling rate and internal clock prescale settings.
The data ready pulse width is equal to half a DMCLK
period, and the frequency of the pulses is equal to
DRCLK (see Figure 1-3).
Note: This pin should not be left floating when
= 0 (default). After each conversion is
the DR_HIZ
resistor connected to DV
recommended.
= 1, and is high-impedance
bit is low; a 100 k pull-up
is
DD
3.8 Oscillator and Master Clock Input Pin (OSC1/CLKI)
OSC1/CLKI and OSC2 provide the master clock for the
device. When CLKEXT = 0, a resonant crystal or clock
source with a similar sinusoidal waveform must be
placed across the OSC1 and OSC2 pins to ensure
proper operation.
The typical clock frequency specified is 4 MHz. For
proper operation and for optimizing ADC accuracy,
AMCLK should be limited to the maximum frequency
defined in Table 5-2 for the function of the BOOST and
PGA setting chosen. MCLK can take larger values as
long as the prescaler settings (PRE<1:0>) limit
AMCLK = MCLK/PRESCALE in the defined range in
Table 5-2. Appropriate load capacitance should be
connected to these pins for proper operation.
Note: When CLKEXT = 1, the crystal oscillator is
disabled. OSC1 becomes the master clock
input CLKI, a direct path for an external
clock source. One example would be a
clock source generated by an MCU.
3.9 Crystal Oscillator (OSC2)
When CLKEXT = 0, a resonant crystal or clock source
with a similar sinusoidal waveform must be placed
across the OSC1 and OSC2 pins to ensure proper
operation. Appropriate load capacitance should be
connected to these pins for proper operation.
When CLKEXT = 1, this pin should be connected to
at all times (an internal pull-down operates this
D
GND
function if the pin is left floating).
3.10 Chip Select (CS)
This pin is the Serial Peripheral Interface (SPI) chip
select that enables serial communication. When this
pin is logic high, no communication can take place. A
chip select falling edge initiates serial communication,
and a chip select rising edge terminates the
communication. No communication can take place
even when CS
This input is Schmitt-triggered.
is logic low if RESET is also logic low.
3.11 Serial Data Clock (SCK)
This is the serial clock pin for SPI communication. Data
is clocked into the device on the rising edge of SCK.
Data is clocked out of the device on the falling edge of
SCK.
The MCP3912 SPI interface is compatible with SPI 0,0
and 1,1 modes. SPI modes can be changed during a
high time.
CS
The maximum clock speed specified is 20 MHz. SCK
and MCLK are two different and asynchronous clocks;
SCK is only required when a communication happens,
while MCLK is continuously required when the part is
converting analog inputs.
This input is Schmitt-triggered.
3.12 Serial Data Output (SDO)
This is the SPI data output pin. Data is clocked out of
the device on the falling edge of SCK.
This pin remains in a high-impedance state during the
command byte. It also stays high-impedance during the
entire communication for write commands when the CS
pin is logic high or when the RESET pin is logic low.
This pin is active only when a read command is
processed. The interface is half-duplex (inputs and
outputs do not happen at the same time).
3.13 Serial Data Input (SDI)
This is the SPI data input pin. Data is clocked into the
device on the rising edge of SCK. When CS
this pin is used to communicate with a series of 8-bit
commands. The interface is half-duplex (inputs and
outputs do not happen at the same time).
Each communication starts with a chip select falling
edge followed by an 8-bit command word entered
through the SDI pin. Each command is either a read or
a write command. Toggling SDI after a read command
or when CS
This input is Schmitt-triggered.
is logic high has no effect.
is logic low,
DS20005348A-page 20 2014 Microchip Technology Inc.
MCP3912
3.14 Master Reset (RESET)
This pin is active-low and places the entire chip in a
Reset state when active.
When RESE
default value, no communication can take place and no
clock is distributed inside the part, except in the input
structure if MCLK is applied (if MCLK is idle, then no
clock is distributed). This state is equivalent to a PowerOn Reset (POR) state.
Since the default state of the ADCs is on, the analog
power consumption when RESET
equivalent to when RESET
power consumption is largely reduced, because this
current consumption is essentially dynamic and is
reduced drastically when there is no clock running.
All the analog biases are enabled during a Reset, so
that the part is fully operational just after a RESET
rising edge if MCLK is applied when RESET is logic
low. If MCLK is not applied, there is a time after a hard
reset when the conversion may not accurately
correspond to the start-up of the input structure.
This input is Schmitt-triggered.
T is logic low, all registers are reset to their
is logic low is
is logic high. Only the digital
3.15 Digital Power Supply (DVDD)
DVDD is the power supply voltage for the digital circuitry
within the MCP3912. It is distributed on several pins
(pins 12 and 24 in the QFN-28 package, one pin only in
the SSOP-28 package). For optimal performance, it is
recommended to connect these pins together using a
star connection and to connect appropriate bypass
capacitors (typically a 10 µF in parallel with a 0.1 µF
ceramic). DV
and 3.6V for specified operation.
At least one of these pins needs to be properly connected to ensure proper functionality of the device. All
of these pins need to be properly connected to ensure
optimal performance of the device. If any of these pins
are left floating, the accuracy and noise specifications
are not ensured.
should be maintained between 2.7V
DD
3.16 Exposed Thermal Pad
This pin must be connected to A
proper operation. Connecting it to A
for lowest noise performance and best thermal
behavior.
or left floating for
GND
is preferable
GND
2014 Microchip Technology Inc. DS20005348A-page 21
MCP3912
AMCLK
MCLK
PRESCALE
------------------------------ -=
Xtal Oscillator
MCLK
OSC1
OSC2
Multiplexer
OUT
0
1
1/PRESCALE
1/4 1/OSR
AMCLK DMCLK DRCLK
Clock Divider Clock Divider Clock Divider
OSR<2:0>PRE<1:0>CLKEXT
DMCLK
AMCLK
4
---------------------
MCLK
4 PRESCALE
----------------------------------------==
DRCLK
DMCLK
OSR
----------------------
AMCLK
4OSR
---------------------
MCLK
4 OSR PRESCALE
-----------------------------------------------------------===
4.0 TERMINOLOGY AND FORMULAS
This section defines the terms and formulas used
throughout this data sheet. The following terms are
defined:
• MCLK – Master Clock
• AMCLK – Analog Master Clock
• DMCLK – Digital Master Clock
• DRCLK – Data Rate Clock
• OSR – Oversampling Ratio
• Offset Error
• Gain Error
• Integral Nonlinearity Error
• Signal-to-Noise Ratio (SNR)
• Signal-To-Noise Ratio And Distortion (SINAD)
• Total Harmonic Distortion (THD)
• Spurious-Free Dynamic Range (SFDR)
• MCP3912 Delta-Sigma Architecture
• Idle Tones
• Dithering
• Crosstalk
• PSRR
• CMRR
• ADC Reset Mode
• Hard Reset Mode (RESET = 0)
• ADC Shutdown Mode
• Full Shutdown Mode
• Measurement Error
4.1 MCLK – Master Clock
This is the fastest clock present on the device. This is
the frequency of the crystal placed at the OSC1/OSC2
inputs when CLKEXT = 0, or the frequency of the
clock input at the OSC1/CLKI when CLKEXT = 1. See
Figure 4-1.
4.2 AMCLK – Analog Master Clock
AMCLK is the clock frequency that is present on the
analog portion of the device after prescaling has
occurred via the CONFIG0 PRE<1:0> register bits (see
Equation 4-1). The analog portion includes the PGAs
and the delta-sigma modulators.
EQUATION 4-1:
T ABLE 4-1: MCP3912 OVERSAMPLING
RATIO SETTINGS
CONFIG0
PRE<1:0>
00 AMCLK = MCLK/1 (default)
01 AMCLK = MCLK/2
10 AMCLK = MCLK/4
11 AMCLK = MCLK/8
Analog Master Clock
Prescale
FIGURE 4-1: Clock Sub-Circuitry.
4.3 DMCLK – Digital Master Clock
This is the clock frequency that is present on the digital
portion of the device after prescaling and division by
four (Equation 4-2). This is also the sampling
frequency, which is the rate at which the modulator
outputs are refreshed. Each period of this clock
corresponds to one sample and one modulator output.
See Figure 4-1.
EQUATION 4-2:
DS20005348A-page 22 2014 Microchip Technology Inc.
4.4 DRCLK – Data Rate Clock
This is the output data rate, i.e., the rate at which the
ADCs output new data. New data is signaled by a data
ready pulse on the DR
This data rate is depending on the OSR and the
prescaler with the formula in Equation 4-3.
EQUATION 4-3:
pin.
MCP3912
Since this is the output data rate, and because the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
Table 4-2 describes the various combinations of OSR
and PRESCALE, and their associated AMCLK,
DMCLK and DRCLK rates.
TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE,
MCLK = 4 MHZ
PRE<1:0> OSR<2:0> OSR AMCLK DMCLK DRCLK
111114096 MCLK/8 MCLK/32 MCLK/131072 .035 102.5 16.7
111112048 MCLK/8 MCLK/32 MCLK/65536 .061 100 16.3
111111024 MCLK/8 MCLK/32 MCLK/32768 .122 97 15.8
11111512 MCLK/8 MCLK/32 MCLK/16384 .244 96 15.6
11011256 MCLK/8 MCLK/32 MCLK/8192 0.488 94 15.3
11010128 MCLK/8 MCLK/32 MCLK/4096 0.976 90 14.7
1100164 MCLK/8 MCLK/32 MCLK/2048 1.95 83 13.5
1100032 MCLK/8 MCLK/32 MCLK/1024 3.9 70 11.3
101114096 MCLK/4 MCLK/16 MCLK/65536 .061 102.5 16.7
101112048 MCLK/4 MCLK/16 MCLK/32768 .122 100 16.3
101111024 MCLK/4 MCLK/16 MCLK/16384 .244 97 15.8
10111512 MCLK/4 MCLK/16 MCLK/8192 .488 96 15.6
10011256 MCLK/4 MCLK/16 MCLK/4096 0.976 94 15.3
10010128 MCLK/4 MCLK/16 MCLK/2048 1.95 90 14.7
1000164 MCLK/4 MCLK/16 MCLK/1024 3.9 83 13.5
1000032 MCLK/4 MCLK/16 MCLK/512 7.8125 70 11.3
011114096 MCLK/2 MCLK/8 MCLK/32768 .122 102.5 16.7
011112048 MCLK/2 MCLK/8 MCLK/16384 .244 100 16.3
011111024 MCLK/2 MCLK/8 MCLK/8192 .488 97 15.8
01111512 MCLK/2 MCLK/8 MCLK/4096 .976 96 15.6
01011256 MCLK/2 MCLK/8 MCLK/2048 1.95 94 15.3
01010128 MCLK/2 MCLK/8 MCLK/1024 3.9 90 14.7
0100164 MCLK/2 MCLK/8 MCLK/512 7.8125 83 13.5
0100032 MCLK/2 MCLK/8 MCLK/256 15.625 70 11.3
001114096 MCLK MCLK/4 MCLK/16384 .244 102.5 16.7
001102048 MCLK MCLK/4 MCLK/8192 .488 100 16.3
001011024 MCLK MCLK/4 MCLK/4096 .976 97 15.8
00100512 MCLK MCLK/4 MCLK/2048 1.95 96 15.6
00011256 MCLK MCLK/4 MCLK/1024 3.9 94 15.3
00010128 MCLK MCLK/4 MCLK/512 7.8125 90 14.7
0000164 MCLK MCLK/4 MCLK/256 15.625 83 13.5
0000032 MCLK MCLK/4 MCLK/128 31.25 70 11.3
Note 1: For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD
values are given from GAIN = 1.
DRCLK
(ksps)
SINAD
(dB)
Note 1
ENOB
from
SINAD
(bits)
Note 1
2014 Microchip Technology Inc. DS20005348A-page 23
MCP3912
SNR dB 10
SignalPower
NoisePower
----------------------------------
log=
SINAD dB 10
SignalPower
Noise HarmonicsPower+
---------------------------------------------------------------------
log=
SINAD dB 10 10
SNR
10
---------- -
10
THD–
10
--------------- -
+log=
4.5 OSR – Oversampling Ratio
This is the ratio of the sampling frequency to the output
data rate; OSR = DMCLK/DRCLK. The default
OSR<2:0> is 256, or with MCLK = 4 MHz,
PRESCALE = 1, AMCLK = 4 MHz, f
= 3.90625 ksps. The OSR<2:0> bits in Tab le 4 -3 in
f
D
= 1 MHz and
S
the CONFIG0 register are used to change the
oversampling ratio (OSR).
TABLE 4-3: MCP3912 OVERSAMPLING
RATIO SETTINGS
OSR<2:0>
000 32
001 64
010 128
011 256 (Default)
100 512
101 1024
110 2048
111 4096
Oversampling Ratio
OSR
4.6 Offset Error
This is the error induced by the ADC when the inputs
are shorted together (V
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chipto-chip. The offset is specified in µV. The offset error
can be digitally compensated independently on each
channel through the OFFCAL_CHn registers with a
24-bit calibration word.
The offset on the MCP3912 has a low-temperature
coefficient.
= 0V). The specification
IN
4.8 Integral Nonlinearity Error
Integral nonlinearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed or with the end points equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
4.9 Signal-to-Noise Ratio (SNR)
For the MCP3912 ADCs, the signal-to-noise ratio is a
ratio of the output fundamental signal power to the
noise power (not including the harmonics of the signal)
when the input is a sine wave at a predetermined
frequency (see Equation 4-4). It is measured in dB.
Usually, only the maximum signal-to-noise ratio is
specified. The SNR figure depends mainly on the OSR
and DITHER settings of the device.
EQUATION 4-4: SIGNAL-TO-NOISE RATIO
4.10 Signal-To-Noise Ratio And Distortion (SINAD)
The most important Figure of Merit for analog
performance of the ADCs present on the MCP3912 is
the Signal-to-Noise And Distortion (SINAD)
specification.
The Signal-to-Noise And Distortion ratio is similar to
signal-to-noise ratio, with the exception that you must
include the harmonic’s power in the noise power
calculation (see Equation 4-5). The SINAD
specification depends mainly on the OSR and DITHER
settings.
4.7 Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in a percentage, compared to the ideal transfer function
defined in Equation 5-3. The specification incorporates
both PGA and ADC gain error contributions, but not the
contribution (it is measured with an external
V
REF
).
V
REF
This error varies with PGA and OSR settings. The gain
error can be digitally compensated independently on
each channel through the GAINCAL_CHn registers
with a 24-bit calibration word.
The gain error on the MCP3912 has a low temperature
coefficient.
DS20005348A-page 24 2014 Microchip Technology Inc.
EQUATION 4-5: SINAD EQUATION
The calculated combination of SNR and THD per the
following formula also yields SINAD (see Equation 4-6).
EQUATION 4-6: SINAD, THD AND SNR
RELATIONSHIP
MCP3912
THD dB 10
HarmonicsPower
FundamentalPower
---------------------------------------------------- -
log=
THD % 100 10
THD dB
20
------------------ ------
=
SFDR dB 10
FundamentalPower
HighestSpurPower
---------------------------------------------------- -
log=
4.1 1 Total Harmonic Distortion (THD)
The total harmonic distortion is the ratio of the output
harmonics power to the fundamental signal power for a
sine wave input, and is defined in Equation 4-7.
EQUATION 4-7:
The THD calculation includes the first 35 harmonics for
the MCP3912 specifications. The THD is usually
measured only with respect to the ten first harmonics,
which leads artificially to better figures. THD is
sometimes expressed in a percentage. Equation 4-8
converts the THD in percentages.
EQUATION 4-8:
This specification depends mainly on the DITHER
setting.
4.12 Spurious-Free Dynamic Range (SFDR)
Spurious-Free Dynamic Range, or SFDR, is the ratio
between the output power of the fundamental and the
highest spur in the frequency spectrum (see
Equation 4-9). The spur frequency is not necessarily a
harmonic of the fundamental, even though it is usually
the case. This figure represents the dynamic range of
the ADC when a full-scale signal is used at the input.
This specification depends mainly on the DITHER
setting.
EQUATION 4-9:
4.13 MCP3912 Delta-Sigma Architecture
The MCP3912 incorporates four delta-sigma ADCs
with a multi-bit architecture. A delta-sigma ADC is an
oversampling converter that incorporates a built-in
modulator, which digitizes the quantity of charges
integrated by the modulator loop (see Figure 5-1). The
quantizer is the block that is performing the
analog-to-digital conversion. The quantizer is typically
1-bit, or a simple comparator, which helps maintain the
linearity performance of the ADC (the DAC structure is,
in this case, inherently linear).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR, which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
linearity is as difficult to attain, and its linearity limits the
THD of such ADCs.
The quantizer present in each ADC channel in the
MCP3912 is a Flash ADC composed of four
comparators arranged with equally spaced thresholds
and a thermometer coding. The MCP3912 also
includes proprietary five-level DAC architecture that is
inherently linear for improved THD figures.
4.14 Idle Tones
A delta-sigma converter is an integrating converter. It
also has a finite quantization step (LSB) that can be
detected by its quantizer. A DC input voltage that is
below the quantization step should only provide an
all zeros result, since the input is not large enough to
be detected. As an integrating device, any delta-sigma
ADC will show idle tones. This means that the output
will have spurs in the frequency content that depend on
the ratio between quantization step voltage and the
input voltage. These spurs are the result of the
integrated sub-quantization step inputs that will
eventually cross the quantization steps after a long
enough integration. This will induce an AC frequency at
the output of the ADC, and can be shown in the ADC
output spectrum.
These idle tones are residues that are inherent to the
quantization process and the fact that the converter is
integrating at all times without being reset. They are
residues of the finite resolution of the conversion
process. They are very difficult to attenuate and they
are heavily signal dependent. They can degrade the
SFDR and THD of the converter, even for DC inputs.
They can be localized in the baseband of the converter
and are thus difficult to filter from the actual input signal.
For power metering applications, idle tones can be very
disturbing, because energy can be detected even at
the 50 or 60 Hz frequency, depending on the DC offset
of the ADCs, while no power is really present at the
inputs. The only practical way to suppress or attenuate
the idle tones phenomenon is to apply dithering to the
ADC. The amplitudes of the idle tones are a function of
the order of the modulator, the OSR and the number of
levels in the quantizer of the modulator. A higher order,
a higher OSR or a higher number of levels for the
quantizer will attenuate the amplitudes of the idle
tones.
2014 Microchip Technology Inc. DS20005348A-page 25
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