Datasheet MCP3903 Datasheet

MCP3903

Six Channel Delta Sigma A/D Converter

Features

• Six Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters with Proprietary Multi-Bit Architecture

• 91 dB SINAD, -100 dBc Total Harmonic Distortion

th

(THD) (up to 35

harmonic), 102 dB Spurious-free

Dynamic Range (SFDR) for Each Channel

• Programmable Data Rate up to 64 ksps

• Ultra Low-Power Shutdown Mode with <2 μA

• -115 dB Crosstalk Between any Two Channels

• Low Drift Internal Voltage Reference: 5 ppm/°C

• Differential Voltage Reference Input Pins

• High Gain PGA on Each Channel (up to 32 V/V)

• Phase Delay Compensation Between Each Pair of Channels with 1 μs Time Resolution

• High-Speed Addressable 10 MHz SPI Interface with Mode 0,0 and 1,1 Compatibility

• Independent Analog and Digital Power Supplies

4.5V - 5.5V AV

, 2.7V - 3.6V DV

DD

• Available in Small 28-lead SSOP Package

• Extended Temperature Range: -40°C to +125°C

Applications

• Energy Metering and Power Measurement

• Portable Instrumentation

• Medical and Power Monitoring

Description

The MCP3903 is a six-channel Analog Front End (AFE) containing three pairs made out of two synchronous sampling Delta-Sigma Analog-to-Digital Converters (ADC) with PGA, a phase delay compensation block, internal voltage reference, and high-speed 10 MHz SPI compatible serial interface. The converters contain a proprietary dithering algorithm for reduced idle tones and improved THD.

The internal register map contains 24-bit wide ADC data words, a modulator output register as well as six 24-bit writable control registers to program gain, over-sampling ratio, phase, resolution, dithering, shut-down, reset and several communication features.

The communication is largely simplified with various Continuous Read modes that can be accessed by the Direct Memory Access (DMA) of an MCU and with separate Data Ready pins that can directly be connected to the Interrupt Request (IRQ) input of an MCU. The MCP3903 is capable of interfacing to a large variety of voltage and current sensors including shunts, current transformers, Rogowski coils, and Hall-effect sensors.

Package Type

28-Lead SSOP

AV

DD

CH0+ CH0CH1CH1+ CH2+ CH2CH3-

CH3+

CH4+

CH4CH5CH5+

REFIN/OUT+

1

2 3 4 5

6 7 8

9

10

11 12

13

DV

28

DD

RESET

27 26

SDI

25

SDO SCK

24

CS

23

OSC2

22

OSC1

21

DRC

20

19

DRB

DRA

18

DGND

17

AGND

16

1514

REFIN-

MCP3903

Functional Block Diagram

REFIN/OUT+

REFIN -

CH0+

CH0-

CH1+

CH1-

CH2+

CH2-

CH3+

CH3-

Voltage

Reference

+

-

VREFEXT

V

REF

DUAL DS

DUAL DS ADC

REF

+

-

+

PGA

+

-

+

PGA

-

V

REF

AV

ANALOG

+V

Δ -Σ

Modulator

Δ -Σ

Modulator

ADC

Δ -Σ

Modulator

Δ -Σ

Modulator

DD

DV

DD

DIGITAL

SINC

AMCLK

DMCLK/DRCLK

3

DATA_CH0<23:0>

Phase

Φ

Shifter

3

Phase

Φ

Shifter

3

PHASEA <7:0>

DATA_CH1<23:0>

DATA_CH2<23:0>

PHASEB <7:0>

DATA_CH3<23:0>

Clock

Generation

DMCLK

Digital SPI

Interface

Xtal Oscillator

MCLK

OSR<1:0> PRE<1:0>

OSC1

OSC2

A

DR

DRB

CH4+

CH4-

CH5+

CH5-

POR AV

DD

Monitoring

+

-

PGA

+

PGA

DUAL DS ADC

AGND DGND

Δ -Σ

Modulator

Δ -Σ

Modulator

SINC

Φ

SINC

POR

3

Phase

Shifter

3

DATA_CH4<23:0>

PHASEC <7:0>

DATA_CH5<23:0>

DRC

SDO

RESET SDI SCK CS

MCP3903

1.0 ELECTRICAL

1.1 RELIABILITY TARGETS

CHARACTERISTICS

The Reliability Targets section includes the absolute maximum ratings for the device, defining the values that will cause no long term damage regardless of duration.

These tables also represent the testing requirements per the Max. and Min. columns.

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

3.6V, Internal V GAIN = 1, V

Param.

Num.

Internal Voltage Reference

A001 V

A002 TC

A003 ZOUT

V oltage Reference Input

A004 Input Capacitance — — 10 pF

A005 V

A006 V

A007 V

ADC Performance

A008 Resolution (No Missing

A009 f

A010 f

Note 1: This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or

instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range, V

IN

2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting. 7: Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to

the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits

off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to ‘0’.

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,

REF

= 1VPP = 353mV

IN

@ 50/60 Hz.

RMS

Symbol Characteristic Min. Typ. Max. Units Test Conditions

REF

REF+

Voltage -2% 2.35 +2% V VREFEXT = 0

Tempco — 5 — ppm/°C VREFEXT = 0

REF

Output Impedance 7 — kΩ AVDD=5V,

REF

Differential Input Voltage Range (V

REF+

- V

REF-

)

Absolute Voltage on REFIN+

2.2 — 2.6 V V

1.9 — 2.9 V VREFEXT = 1

REF-

Absolute Voltage on REFIN-

-0.3 — +0.3 V V

Codes)

Sampling Frequency See Tab le 4 -2 kHz fS = DMCLK = MCLK / (4 x

S

Output Data Rate See Tab l e 4 -2 ksps fD = DRCLK= DMCLK / OSR

D

= -0.5 dBFS @ 50/60 Hz = 333 mV

RMS

, V

REF

= 2.4V.

ABSOLUTE MAXIMUM RATINGS †

VDD...................................................................................7.0V

Digital inputs and outputs w.r.t. A Analog input w.r.t. A

input w.r.t. A

V

REF

Storage temperature..................................... -65°C to +150°C

Ambient temp. with power applied................ -65°C to +125°C

Soldering temperature of leads (10 seconds)............. +300°C

ESD on the analog inputs (HBM,MM)................. 5.0 kV, 500V

ESD on all other pins (HBM,MM)........................ 5.0 kV, 500V

..................................... ....-6V to +6V

GND

................................-0.6V to VDD +0.6V

GND

= 4.5 to 5.5V, DVDD = 2.7 to

DD

VREFEXT = 0

VREFEXT = 1

to AGND when VREFEXT=0

24 bits OSR = 256 (see Table 5-2)

PRESCALE)

= MCLK / (4 x PRESCALE x OSR)

........-0.6V to VDD +0.6V

GND

= (V

REF

should be connected

REF-

REF+

- V

REF-

),

MCP3903

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

3.6V, Internal V GAIN = 1, V

Param.

Num.

A011 CHn+- Analog Input Absolute

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,

REF

= 1VPP = 353mV

IN

@ 50/60 Hz.

RMS

Symbol Characteristic Min. Typ. Max. Units Test Conditions

-1 +1 V All analog input channels,

Voltage

A012 A

Analog Input Leakage

IN

1nA(Note 4)

Current

A013 (CH

CH

A014 V

Differential Input Voltage

-

n+

)

Range

n-

Offset Error -3 3 mV (Note 6)(Note 2)

OS

500 /

GAIN

A015 Offset Error Drift 1 μV/C From -40°C to 125°C A016 GE Gain Error -3 3 % All Gains

A017 Gain Error Drift — 2 — ppm/°C From -40°C to 125°C

A018 INL Integral Non-Linearity 15 ppm GAIN = 1, DITHER = ON

A019 Z

A020 SINAD Signal-to-Noise and

Input Impedance 350 — — kΩ Proportional to 1/AMCLK

IN

89 91 — dB T = 25°C

Distortion Ratio

80 81.5 dB

A021 THD Total Harmonic Distortion -100 -97 dB OSR = 256, DITHER = ON;

-90 -87 dB

A022 SNR Signal To Noise Ratio 90 91.5 dB T = 25°C

80 81.5 dB

A023 SFDR Spurious Free Dynamic

102 dB OSR = 256, DITHER = ON;

Range

91 dB

A024 CTALK Crosstalk (50 / 60 Hz) — -115 — dB OSR = 256, DITHER = ON;

A025 AC PSRR AC Power Supply Rejection — -68 — dB AV

A026 DC PSRR DC Power Supply Rejection — -68 — dB AVDD = 4.5 to 5.5V, DVDD =

A027 CMRR DC Common Mode Rejection

—-75 — dBV

Ratio

Oscillator Input

Note 1: This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or

instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range, V

= -0.5 dBFS @ 50/60 Hz = 333 mV

IN

2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting. 7: Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to

the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits

off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to ‘0’.

RMS

, V

REF

= 2.4V.

= 4.5 to 5.5V, DVDD = 2.7 to

DD

measured to AGND

(Note 7)

mV

P

(Note 1)

(Note 2)(Note 3)

(Note 2) (Note 3)

(Note 2)(Note 3)

= 5V + 1Vpp @ 50 Hz

DD

3.3V

varies from -1V to +1V;

CM

(Note 2)

MCP3903

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

3.6V, Internal V GAIN = 1, V

Param.

Num.

A028 MCLK Master Clock Frequency

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,

REF

= 1VPP = 353mV

IN

@ 50/60 Hz.

RMS

Symbol Characteristic Min. Typ. Max. Units Test Conditions

1 — 16.384 MHz (Note 8)

Range

Power Specifications

P001 AV

P002 DV

P003 AI

Operating Voltage, Analog 4.5 — 5.5 V

DD

Operating Voltage, Digital 2.7 — 3.6 V

DD

Operating Current, Analog

DD

7.1 9 mA BOOST bits low on all chan-

(Note 4)

12.3 16.8 mA BOOST bits high on all

P004 DI

Operating Current, Digital — 1.2 1.7 mA DVDD = 3.6V, MCLK =

DD

—2.4 3.4 mADV

P005 I

DDS,A

Shutdown Current, Analog — — 1 μA -40°C to 85°C, AV

—— 3 μA -40°C to 125°C, AV

P006 I

DDS,D

Shutdown Current, Digital — — 1 μA -40°C to 85°C, DV

—— 5 μA -40°C to 125°C, DV

Note 1: This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or

instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range, V

= -0.5 dBFS @ 50/60 Hz = 333 mV

IN

2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting. 7: Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to

the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits

off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to ‘0’.

RMS

, V

REF

= 2.4V.

= 4.5 to 5.5V, DVDD = 2.7 to

DD

nels

channels

4MHz

= 3.6V, MCLK =

DD

8.192 MHz

only, (Note 5)

DD

MCP3903

1.2 SERIAL INTERFACE CHARACTERISTICS

SERIAL INTERFACE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

= 2.7 to 3.6V, -40°C < TA <+125°C, C

DV

DD

Parameters Sym Min Typ Max Units Conditions

LOAD

= 30 pF.

= 4.5 to 5.5V,

DD

Serial Clock frequency f

CS

setup time t

hold time

CS

disable time t

CS

Data setup time t

Data hold time t

Serial Clock high time t

Serial Clock low time t

Serial Clock delay time t

Serial Clock enable time t

Output valid from SCK low t

Output hold time t

Output disable time t

Reset Pulse Width (RESET

Data Transfer Time to DR

)t

(Data Ready) t

DODR

Data Ready Pulse Low Time t

Schmitt Trigger High-level Input voltage

SCK

CSS

t

CSH

CSD

SU

HD

HI

LO

CLD

CLE

DO

HO

DIS

MCLR

DRP

V

IH1

—— 10MHz2.7 ≤ DVDD < 3.6 50 — — ns 2.7 ≤ DVDD < 3.6

100 — — ns 2.7 ≤ DVDD < 3.6

50 — — ns — 10 — — ns 2.7 ≤ DVDD < 3.6 20 — — ns 2.7 ≤ DVDD < 3.6 40 — — ns 2.7 ≤ DVDD < 3.6 40 — — ns 2.7 ≤ DVDD < 3.6

50 — — ns —

50 — — ns — — — 50 ns 2.7 ≤ DVDD < 3.6

0——ns

— — 50 ns 2.7 ≤ DVDD < 3.6

100 — — ns 2.7 ≤ DVDD < 3.6

—50ns2.7 ≤ DVDD < 3.6

1/

DMCLK

.7 DV

—DVDD +1 V

DD

(All digital inputs)

Schmitt Trigger Low-level input voltage

V

IL1

-0.3 — 0.25

(All digital inputs)

Hysteresis of Schmitt Trigger Inputs

V

HYS

50 — mV

(All digital inputs)

Low-level output voltage, SDO pin V

Low-level output voltage, DRn

pins V

High-level output voltage, SDO pin V

OL

OH

— — 0.4 V SDO pin only, IOL = 2 mA,

DVDD -

— — V SDO pin only,

0.5

High-level output voltage, DRn

pins

only

Input leakage current I

Output leakage current I

Internal capacitance (all inputs and

V

OH

DVDD -

——VDRn pins only,

0.5

LI

LO

C

INT

— — ±1 µA CS = DVDD, Inputs tied to

—— 7 pFT

outputs)

Note 1: This parameter is periodically sampled and not 100% tested.

—µs2.7 ≤ DV

DD

V

DV

DD

DV

= 3.3V

DD

0.4 V DRn pins only, I

= +1.5 mA, DVDD =3.3V

OL

I

= -2 mA, DVDD = 3.3V

OH

I

= -1.5 mA, DVDD=3.3V

OH

OR DGND

DV

DD

OR DGND

DV

DD

= 25°C, SCK = 1.0 MHz

A

= 3.3V (Note 1)

DV

DD

< 3.6

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

3.3 V.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 28-lead

θ

SSOP

Note 1: The internal junction temperature (T

CS

f

SCK

t

HI

LO

SCK

-40 — +125 °C (Note 1)

A

-65 — +150 °C

A

JA

—71 — °C/W

) must not exceed the absolute maximum specification of +150°C.

J

MCP3903

= 4.5 to 5.5V, DVDD = 2.7 to

DD

t

CSH

Mode 1,1 Mode 0,0

t

DO

SDO

SDI

MSB out

Don’t Care

FIGURE 1-1: Serial Output Timing Diagram.

CS

SCK

SDI

SDO

t

CSS

Mode 1,1 Mode 0,0

t

SU

MSB in

t

HD

f

SCK

t

HI

LO

HI-Z

t

HO

LSB in

t

CSH

t

DIS

LSB out

t

CSD

t

CLE

t

CLD

FIGURE 1-2: Serial Input Timing Diagram.

MCP3903

H

DR

t

DODR

SCK

SDO

FIGURE 1-3: Data Ready Pulse Timing Diagram.

H

1 / DRCLK

t

DRP

Timing Waveform for t

DO

SCK

t

DO

SDO

Timing Waveform for MDAT0/1

Modulator Output

OSC1/CLKI

t

DOMDAT

MDAT0/1

FIGURE 1-4: Specific Timing Diagrams.

OSC1

OSC2

Digital Buffer

Crystal Oscillator

CLKEXT

1

MCLK AMCLK

0

Multiplexer Clock Divider Clock Divider Clock Divider

PRESCALE<1:0>

Prescale

1 /

CS

SDO

1 / 4

Timing Waveform for t

V

IH

90%

t

DIS

10%

OSR<1:0>

f

ADC

S

Sampling Rate

1 / OSR

DMCLK

DIS

HI-Z

ADC

f

D

Output Data Rate

DRCLK

FIGURE 1-5: MCP3903 Clock Detail.

MCP3903

2.0 TYPI CAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, AV

= 1; OSR = 64; GAIN = 1; Dithering OFF; V

.

= 5.0V, DV

DD

FIGURE 2-1: Spectral Response.

= 3.3 V; Internal V

DD

= -0.5 dBFS @ 60 Hz.

IN

; TA = +25°C, MCLK = 4 MHz; PRESCALE

REF

FIGURE 2-4: Spectral Response.

FIGURE 2-2: Spectral Response.

FIGURE 2-3: Spectral Response.

FIGURE 2-5: Spectral Response.

FIGURE 2-6: Spectral Response.

MCP3903

85

Note: Unless otherwise indicated, AV

64; GAIN = 1; Dithering OFF; V

.

IN

= 5.0V, DV

DD

= -0.5 dBFS @ 60 Hz.

FIGURE 2-7: Spectral Response.

120

ic

100

)

ynamic

80

60

ge (dB)

Free Dynamic

40

Range (dB)

ious Free Dynamic

20

Spurious Free Dynamic

0

32 64 128 256

Dithering ON

Dithering OFF

Oversampling Ratio (OSR)

FIGURE 2-8: Spurious Free Dynamic Range vs Oversampling Ratio.

= 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

DD

100

95

95 90

90

)

85

85 80

80

80 75

75

AD (dB)

70

SINAD (dB)

65

65 60

60

60 55

55

55 50

50

OSR = 64

OSR = 32

12481632

OSR = 256

OSR = 128

GAIN (V/V)

FIGURE 2-10: Signal-to-Noise and Distortion vs. Gain (Dithering OFF).

100

95

95 90

90

90 85

85

85 80

80

D (dB)

75

75 70

70

SINAD (dB)

65

65 60

60

60 55

55

55 50

50

OSR = 64

OSR = 32

12481632

OSR = 256

GAIN (V/V)

OSR = 128

FIGURE 2-11: Signal-to-Noise and Distortion vs. Gain (Dithering ON).

120

Dithering ON

100

)

80

60

AD (dB)

40

SINAD (dB)

20

0

Dithering OFF

32 64 128 256

Dithering ON

Oversampling Ratio (OSR)

FIGURE 2-9: Signal-to-Noise and Distortion vs. Oversampling Ratio.

FIGURE 2-12: Total Harmonic Distortion vs. Oversampling Ratio.

MCP3903

Note: Unless otherwise indicated, AV

64; GAIN = 1; Dithering OFF; V

.

-60

n

-70

tortion

-80

-90

Bc)

nic Distortion

(dBc)

-100

armonic Distortion

-110

-110 otal Harmonic Distortion Total Harmonic Distortion

Total Harmonic Distortion

-120

Dithering OFF

Dithering ON

20 50 100 200 500 1000 2000

Input Frequency (Hz)

IN

= 5.0V, DV

DD

= -0.5 dBFS @ 60 Hz.

fs=15.625KHz

fs=15.625KHz OSR=64

OSR=64

FIGURE 2-13: Total Harmonic Distortion vs. Input Signal Frequency.

0

on

-20

istortion

-40

-

-60

dBc)

onic Distortion

(dBc)

-80

fs=15.625KHz

fs=15.625KHz OSR=64

OSR=64

Harmonic Distortion

-100

Total Harmonic Distortion

-

-120

-40 -20 0 25 45 85 105 125

Temperature (°C)

°

FIGURE 2-14: Total Harmonic Distortion vs. Temperature.

= 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

DD

120

100

80

D (dB)

60

40

SINAD (dB)

20

0

-40 -20 0 25 45 85 105 125

Temperature (°C)

fs=15.625KHz

fs=15.625KHz OSR=64

OSR=64

FIGURE 2-16: Signal-to-Noise and Distortion vs. Temperature.

90

90 80

80

80 70

70

70 60

60

B)

50

50 40

40

AD (dB)

30

SINAD (dB)

20

20 10

10

0

-10

0.00001 0.001 0.1 10 1000

0.00001 0.001 0.1 10 1000 Input Signal Amplitude (mV)

FIGURE 2-17: Signal-to-Noise and Distortion vs. Input Signal Amplitude.

100

90

90 80

80

)

70

70 60

60

60 50

50

AD (dB)

40

SINAD (dB)

30

30 20

20

20 10

10

0

Dithering OFF

Dithering ON

=

fs=15.625KHz

fs=15.625KHz OSR=64

OSR=64

20 50 100 200 500 1000 2000

Input Frequency (Hz)

FIGURE 2-15: Signal-to-Noise and Distortion vs. Input Signal Frequency.

FIGURE 2-18: Signal-to-Noise and Distortion vs. Master Clock.

MCP3903

Note: Unless otherwise indicated, AV

64; GAIN = 1; Dithering OFF; V

1.40

1.20

1.00

(mV)

0.80

0.60

Error (mV)

0.40

0.20

ffset Error (mV)

0.00

Offset Error (mV)

-0.20

-

-0.40

G=1

G=4

G=32

-40 -20 0 25 45 85 105 125

Temperature (°C)

IN

= 5.0V, DV

DD

= -0.5 dBFS @ 60 Hz.

G=8

G=16

G=2

°

FIGURE 2-19: Offset Error vs. Temperature (Channel 0).

1.60

1.40

1.20

(mV)

1.00

0.80

Error (mV)

0.60

ffset Error (mV)

0.40

Offset Error (mV)

0.20

0.00

CH2

-40 -20 0 25 45 85 105 125

CH1

CH0

Temperature (°C)

CH3

CH4

CH5

FIGURE 2-20: Channel-to-Channel Offset Match vs. Temperature.

= 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

2.360

V)

2.355

rence (V)

2.350

Reference (V)

ltage Reference (V)

2.345

Int. Voltage Reference (V)

2.340

-40 -20 0 25 45 85 105 125

Temperature (°C)

°

FIGURE 2-22: Internal Voltage Reference vs. Temperature.

2.35473

2.35472

2.35471

ce (V)

2.35470

eference (V)

2.35469

ge Reference (V)

2.35468

2.35467

t. Voltage Reference (V)

2.35466

Int. Voltage Reference (V)

4.5 5 5.5

4.5 5 5.5 Power Supply (V)

FIGURE 2-23: Internal Voltage Reference vs. Supply Voltage.

0.00

G=1

G=16

G=1

-0.05

%)

-0.10

-

G=2

-0.15

Error (%)

-0.20

Gain Error (%)

-0.25

-0.30

G=2

G=32

G=4

-40 -20 0 25 45 85 105 125

G=8

Temperature (°C)

FIGURE 2-21: Gain Error vs. Temperature.

FIGURE 2-24: Noise Histogram.

MCP3903

Note: Unless otherwise indicated, AV

64; GAIN = 1; Dithering OFF; V

50

50 40

40

40 30

30

30 20

20

)

10

0

(ppm)

-10

INL (ppm)

-20

-30

-40

-50

-0.5 -0.25 0 0.25 0.5

CH1

Input Voltage (V)

IN

= 5.0V, DV

DD

= -0.5 dBFS @ 60 Hz.

FIGURE 2-25: Integral Non-Linearity (Dithering OFF).

50

50 40

40

40 30

30

30 20

20

20 10

10

0

ppm)

-10

-20

INL (ppm)

-30

-40

-

-50

-0.5 -0.25 0 0.25 0.5

-0.5 -0.25 0 0.25 0.5 Input Voltage (V)

Input Voltage (V)

CH0

CH1

CH0

= 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

DD

FIGURE 2-26: Integral Non-Linearity (Dithering ON).

9

8

7

6

5

(mA)

4

IDD (mA)

3

2

1

0

1234

AIDD Boost OFF

DIDD

MCLK Frequency(MHz)

FIGURE 2-27: Operating Current vs. Master Clock (MCLK).

MCP3903

3.0 PIN DESCRIPTION

TABLE 3-1: PIN FUNCTION TABLE

Pin No. Symbol Function

1AV

2 CH0+ Non-Inverting Analog Input Pin for Channel 0

3 CH0- Inverting Analog Input Pin for Channel 0

4 CH1- Inverting Analog Input Pin for Channel 1

5 CH1+ Non-Inverting Analog Input Pin for Channel 1

6 CH2+ Non-Inverting Analog Input Pin for Channel 2

7 CH2- Inverting Analog Input Pin for Channel 2

8 CH3- Inverting Analog Input Pin for Channel 3

9 CH3+ Non-Inverting Analog Input Pin for Channel 3

10 CH4+ Non-Inverting Analog Input Pin for Channel 4

11 CH4- Inverting Analog Input Pin for Channel 4

12 CH5- Inverting Analog Input Pin for Channel 5

13 CH5+ Non-Inverting Analog Input Pin for Channel 5

14 REFIN+/OUT Non-Inverting Voltage Reference Input and Internal Reference Output Pin

15 REFIN- Inverting Voltage Reference Input Pin

16 A

17 D

18 DR

19 DR

20 DR

21 OSC1 Oscillator Crystal Connection Pin or Clock Input Pin

22 OSC2 Oscillator Crystal Connection Pin

23 CS

24 SCK Serial Interface Clock Pin

25 SDO Serial Interface Data Output Pin

26 SDI Serial Interface Data Input Pin

27 RESET

28 DV

DD

GND

A Data Ready Signal Output for channels pair A

B Data Ready Signal Output for channels pair B

C Data Ready Signal Output for channels pair C

DD

Analog Power Supply Pin

Analog Ground Pin, Return Path for internal analog circuitry

Digital Ground Pin, Return Path for internal digital circuitry

Chip Select for Serial Interface

Master Reset Logic Input Pin

Digital Power Supply Pin

3.1 RESET

This pin is active low and places the entire chip in a reset state when active.

When RESET value, no communication can take place, no clock is distributed inside the part. This state is equivalent to a POR state.

Since the default state of the ADCs is on, the analog power consumption when RESET when RESET is largely reduced because this current consumption is essentially dynamic and is reduced drastically when there is no clock running. All the analog biases are

=0, all registers are reset to their default

= 0 is equivalent to

= 1. Only the digital power consumption

enabled during a reset so that the part is fully operational just after a RESET is Schmitt triggered.

3.2 Digital V

DV

is the power supply pin for the digital circuitry

DD

within the MCP3903. This pin requires appropriate bypass capacitors and should be maintained between

2.7V and 3.6V for specified operation.

DD

(DV

rising edge. This input

)

DD

MCP3903

3.3 Analog V

AV

is the power supply pin for the analog circuitry

DD

within the MCP3903.

This pin requires appropriate bypass capacitors and should be maintained to 5V ±10% for specified operation.

DD

(AV

DD

)

3.4 ADC Differential Analog Inputs(CHn+/CHn-)

CHn- and CHn+, are the two fully-differential analog voltage inputs for the Delta-Sigma ADCs. There are six channels in total grouped in three channel pairs.

The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±500 mV/GAIN with

= 2.4V. The maximum absolute voltage, with

V

REF

respect to AGND, for each CHn+/- input pin is +/-1V with no distortion and ±6V with no breaking after continuous voltage.

3.5 Analog Ground (AGND)

AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). To ensure accuracy and noise cancellation, this pin must be connected to the same ground as DGND, preferably with a star connection. If an analog ground plane is available, it is recommended that this pin be tied to this plane of the PCB. This plane should also reference all other analog circuitry in the system.

3.6 Non-Inverting Reference Input, Internal Reference Output (REFIN+/OUT)

This pin is the non-inverting side of the differential voltage reference input for all ADCs or the internal voltage reference output. When VREFEXT = 1, and an external voltage reference source can be used, the internal voltage reference is disabled. When using an external differential voltage reference, it should be connected to its V

When using an external single-ended reference, it should be connected to this pin.

When VREFEXT = 0, the internal voltage reference is enabled and connected to this pin through a switch. This voltage reference has minimal drive capability and thus needs proper buffering and bypass capacitances (10 μF tantalum in parallel with 0.1 μF ceramic) if used as a voltage source.

For optimal performance, bypass capacitances should be connected between this pin and AGND at all times even when the internal voltage reference is used.

REF+

pin.

3.7 Inverting Reference Input (REFIN-)

This pin is the inverting side of the differential voltage reference input for both ADCs. When using an external differential voltage reference, it should be connected to its V voltage reference, or when VREFEXT = 0 (Default) and using the internal voltage reference, this pin should be directly connected to AGND.

pin. When using an external single-ended

REF-

3.8 Digital Ground Connection (DGND)

DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). To ensure accuracy and noise cancellation, DGND must be connected to the same ground as AGND, preferably with a star connection. If a digital ground plane is available, it is recommended that this pin be tied to this plane of the Printed Circuit Board (PCB). This plane should also reference all other digital circuitry in the system.

3.9 DRn (Data Ready Pins)

The Data Ready pins indicate if a new conversion result is ready to be read on each of the A, B and C pairs of ADCs. The default state of this pin is high when DR_HIZN=1 and is high impedance when DR_HIZN=0 (Default). After each conversion is finished, a low pulse will take place on the data ready pins to indicate the conversion result is ready as an interrupt. This pulse is synchronous with the master clock and has a defined and constant width.

The Data Ready pins are independent of the SPI interface and act like an interrupt output.The Data Ready pins state is not latched and the pulse width (and period) are both determined by the MCLK frequency, over-sampling rate, and internal clock prescale settings. The DR pulse width is equal to one DMCLK period and the frequency of the pulses is equal to DRCLK (see Figure 1-3).

Note: These pins should not be left floating

when DR_HIZ resistor connected to DV mended.

bit is low; a 100kΩ pull-up

is recom-

DD

MCP3903

3.10 Oscillator And Master Clock Input Pins (OSC1/CLKI, OSC2)

OSC1/CLKI and OSC2 provide the master clock for the device. When CLKEXT = 0 (Default), a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 4 MHz. However, the clock frequency can be 1 MHz to 5 MHz without disturbing ADC accuracy. With the current boost circuit enabled, the master clock can be used up to 8.192 MHz without disturbing ADC accuracy. Appropriate load capacitance should be connected to these pins for proper operation.

Note: When CLKEXT = 1, the crystal oscillator

is disabled, as well as the OSC2 input. The OSC1 becomes the master clock input CLKI, direct path for an external clock source, for example a clock source generated by an MCU.

3.11 CS (Chip Select)

This pin is the SPI Chip Select that enables the serial communication. When this pin is high, no communication can take place. A chip select falling edge initiates the serial communication and a chip select rising edge terminates the communication. No communication can take place even when CS and when RESET

This input is Schmitt-triggered.

is low.

is low

3.12 SCK (Serial Data Clock)

This is the serial clock pin for SPI communication. Data is clocked into the device on the RISING edge of SCK. Data is clocked out of the device on the FALLING edge of SCK. The MCP3903 interface is compatible with both SPI 0,0 and 1,1 modes. The maximum clock speed specified is 10 MHz. This input is Schmitt triggered.

3.13 SDO (Serial Data Output)

This is the SPI data output pin. Data is clocked out of the device on the FALLING edge of SCK. This pin stays at high impedance during the control byte. It also stays at high impedance during the whole communication for write commands and when the CS pin is high or when the RESET pin is low. This pin is active only when a read command is processed. Each read is processed by a packet of 24 bits (size of each register), except on the ADC output registers when WIDTH=0.

3.14 SDI (Serial Data Input)

This is the SPI data input pin. Data is clocked into the device on the RISING edge of SCK. When CS is low, this pin is used to communicate with a series of 8-bit commands. The interface is half-duplex (inputs and outputs do not happen at the same time). Each communication starts with a chip select falling edge followed by an 8-bit control byte entered through the SDI pin. Each write is processed by packets of 24 bits (size of each register). Each command is either a Read or a Write command. Toggling SDI during a Read command has no effect. This input is Schmitt-triggered.

MCP3903

4.0 TERMINOLOGY AND FORMULAS

This section defines the terms and formulas used throughout this data sheet. The following terms are defined:

MCLK - Master Clock

AMCLK - Analog Master Clock

DMCLK - Digital Master Clock

DRCLK - Data Rate Clock

OSR - Oversampling Ratio

Offset Error

Gain Error

Integral Non-Linearity Error

Signal-To-Noise Ratio (SNR)

Signal-To-Noise Ratio And Distortion (SINAD)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

MCP3903 Delta-Sigma Architecture

Idle Tones

Dithering

Crosstalk

PSRR

CMRR

ADC Reset Mode

Hard Reset Mode (RESET = 0)

ADC Shutdown Mode

Full Shutdown Mode

4.1 MCLK - Master Clock

4.2 AMCLK - Analog Master Clock

This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG PRESCALE<1:0> register bits. The analog portion includes the PGAs and the two sigma-delta modulators.

EQUATION 4-1:

AMCLK

MCLK

------------------------------ -=

PRESCALE

T ABLE 4-1: MCP3903 OVERSAMPLING

RATIO SETTINGS

Config

PRE<1:0>

00AMCLK = MCLK/ 1 (default) 01 AMCLK = MCLK/ 2 10 AMCLK = MCLK/ 4 11 AMCLK = MCLK/ 8

Analog Master Clock

Prescale

4.3 DMCLK - Digital Master Clock

This is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. This is also the sampling frequency, that is the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output.

EQUATION 4-2:

DMCLK

AMCLK

--------------------4

MCLK

----------------------------------------== 4 PRESCALE×

This is the fastest clock present in the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1.

4.4 DRCLK - Data Rate Clock

This is the output data rate i.e. the rate at which the ADCs output new data. Each new data is signaled by a data ready pulse on the DR pin.

This data rate is depending on the OSR and the prescaler with the following formula:

EQUATION 4-3:

DMCLK

DRCLK

---------------------OSR

AMCLK

--------------------4OSR×

-----------------------------------------------------------=== 4 OSR PRESCALE××

MCLK

Datasheet MCP3903 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 RELIABILITY TARGETS

1.2 SERIAL INTERFACE CHARACTERISTICS

FIGURE 1-1: Serial Output Timing Diagram.

FIGURE 1-2: Serial Input Timing Diagram.

FIGURE 1-3: Data Ready Pulse Timing Diagram.

FIGURE 1-4: Specific Timing Diagrams.

FIGURE 1-5: MCP3903 Clock Detail.

2.0 TYPI CAL PERFORMANCE CURVES

FIGURE 2-1: Spectral Response.

FIGURE 2-4: Spectral Response.

FIGURE 2-2: Spectral Response.

FIGURE 2-3: Spectral Response.

FIGURE 2-5: Spectral Response.

FIGURE 2-6: Spectral Response.

FIGURE 2-7: Spectral Response.

FIGURE 2-8: Spurious Free Dynamic Range vs Oversampling Ratio.

FIGURE 2-10: Signal-to-Noise and Distortion vs. Gain (Dithering OFF).

FIGURE 2-11: Signal-to-Noise and Distortion vs. Gain (Dithering ON).

FIGURE 2-9: Signal-to-Noise and Distortion vs. Oversampling Ratio.

FIGURE 2-12: Total Harmonic Distortion vs. Oversampling Ratio.

FIGURE 2-13: Total Harmonic Distortion vs. Input Signal Frequency.

FIGURE 2-14: Total Harmonic Distortion vs. Temperature.

FIGURE 2-16: Signal-to-Noise and Distortion vs. Temperature.

FIGURE 2-17: Signal-to-Noise and Distortion vs. Input Signal Amplitude.

FIGURE 2-15: Signal-to-Noise and Distortion vs. Input Signal Frequency.

FIGURE 2-18: Signal-to-Noise and Distortion vs. Master Clock.

FIGURE 2-19: Offset Error vs. Temperature (Channel 0).

FIGURE 2-20: Channel-to-Channel Offset Match vs. Temperature.

FIGURE 2-22: Internal Voltage Reference vs. Temperature.

FIGURE 2-23: Internal Voltage Reference vs. Supply Voltage.

FIGURE 2-21: Gain Error vs. Temperature.

FIGURE 2-24: Noise Histogram.

FIGURE 2-25: Integral Non-Linearity (Dithering OFF).

FIGURE 2-26: Integral Non-Linearity (Dithering ON).

FIGURE 2-27: Operating Current vs. Master Clock (MCLK).

3.0 PIN DESCRIPTION

TABLE 3-1: PIN FUNCTION TABLE

3.1 RESET

3.4 ADC Differential Analog Inputs(CHn+/CHn-)

3.5 Analog Ground (AGND)

3.6 Non-Inverting Reference Input, Internal Reference Output (REFIN+/OUT)

3.7 Inverting Reference Input (REFIN-)

3.8 Digital Ground Connection (DGND)

3.9 DRn (Data Ready Pins)

3.10 Oscillator And Master Clock Input Pins (OSC1/CLKI, OSC2)

3.11 CS (Chip Select)

3.12 SCK (Serial Data Clock)

3.13 SDO (Serial Data Output)

3.14 SDI (Serial Data Input)

4.0 TERMINOLOGY AND FORMULAS

4.1 MCLK - Master Clock

4.2 AMCLK - Analog Master Clock

4.3 DMCLK - Digital Master Clock

4.4 DRCLK - Data Rate Clock