Datasheet MCP3903 Datasheet

MCP3903

Six Channel Delta Sigma A/D Converter

Features

• Six Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters with Proprietary Multi-Bit Architecture

• 91 dB SINAD, -100 dBc Total Harmonic Distortion

th

(THD) (up to 35

harmonic), 102 dB Spurious-free

Dynamic Range (SFDR) for Each Channel

• Programmable Data Rate up to 64 ksps

• Ultra Low-Power Shutdown Mode with <2 μA

• -115 dB Crosstalk Between any Two Channels

• Low Drift Internal Voltage Reference: 5 ppm/°C

• Differential Voltage Reference Input Pins

• High Gain PGA on Each Channel (up to 32 V/V)

• Phase Delay Compensation Between Each Pair of Channels with 1 μs Time Resolution

• High-Speed Addressable 10 MHz SPI Interface with Mode 0,0 and 1,1 Compatibility

• Independent Analog and Digital Power Supplies

4.5V - 5.5V AV

, 2.7V - 3.6V DV

DD

• Available in Small 28-lead SSOP Package

• Extended Temperature Range: -40°C to +125°C

Applications

• Energy Metering and Power Measurement

• Portable Instrumentation

• Medical and Power Monitoring

Description

The MCP3903 is a six-channel Analog Front End (AFE) containing three pairs made out of two synchronous sampling Delta-Sigma Analog-to-Digital Converters (ADC) with PGA, a phase delay compensation block, internal voltage reference, and high-speed 10 MHz SPI compatible serial interface. The converters contain a proprietary dithering algorithm for reduced idle tones and improved THD.

The internal register map contains 24-bit wide ADC data words, a modulator output register as well as six 24-bit writable control registers to program gain, over-sampling ratio, phase, resolution, dithering, shut-down, reset and several communication features.

The communication is largely simplified with various Continuous Read modes that can be accessed by the Direct Memory Access (DMA) of an MCU and with separate Data Ready pins that can directly be connected to the Interrupt Request (IRQ) input of an MCU. The MCP3903 is capable of interfacing to a large variety of voltage and current sensors including shunts, current transformers, Rogowski coils, and Hall-effect sensors.

Package Type

28-Lead SSOP

AV

DD

CH0+ CH0CH1CH1+ CH2+ CH2CH3-

CH3+

CH4+

CH4CH5CH5+

REFIN/OUT+

1

2 3 4 5

6 7 8

9

10

11 12

13

DV

28

DD

RESET

27 26

SDI

25

SDO SCK

24

CS

23

OSC2

22

OSC1

21

DRC

20

19

DRB

DRA

18

DGND

17

AGND

16

1514

REFIN-

MCP3903

Functional Block Diagram

REFIN/OUT+

REFIN -

CH0+

CH0-

CH1+

CH1-

CH2+

CH2-

CH3+

CH3-

Voltage

Reference

+

-

VREFEXT

V

REF

DUAL DS

DUAL DS ADC

REF

+

-

+

PGA

+

-

+

PGA

-

V

REF

AV

ANALOG

+V

Δ -Σ

Modulator

Δ -Σ

Modulator

ADC

Δ -Σ

Modulator

Δ -Σ

Modulator

DD

DV

DD

DIGITAL

SINC

AMCLK

DMCLK/DRCLK

3

DATA_CH0<23:0>

Phase

Φ

Shifter

3

Phase

Φ

Shifter

3

PHASEA <7:0>

DATA_CH1<23:0>

DATA_CH2<23:0>

PHASEB <7:0>

DATA_CH3<23:0>

Clock

Generation

DMCLK

Digital SPI

Interface

Xtal Oscillator

MCLK

OSR<1:0> PRE<1:0>

OSC1

OSC2

A

DR

DRB

CH4+

CH4-

CH5+

CH5-

POR AV

DD

Monitoring

+

-

PGA

+

PGA

DUAL DS ADC

AGND DGND

Δ -Σ

Modulator

Δ -Σ

Modulator

SINC

Φ

SINC

POR

3

Phase

Shifter

3

DATA_CH4<23:0>

PHASEC <7:0>

DATA_CH5<23:0>

DRC

SDO

RESET SDI SCK CS

MCP3903

1.0 ELECTRICAL

1.1 RELIABILITY TARGETS

CHARACTERISTICS

The Reliability Targets section includes the absolute maximum ratings for the device, defining the values that will cause no long term damage regardless of duration.

These tables also represent the testing requirements per the Max. and Min. columns.

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

3.6V, Internal V GAIN = 1, V

Param.

Num.

Internal Voltage Reference

A001 V

A002 TC

A003 ZOUT

V oltage Reference Input

A004 Input Capacitance — — 10 pF

A005 V

A006 V

A007 V

ADC Performance

A008 Resolution (No Missing

A009 f

A010 f

Note 1: This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or

instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range, V

IN

2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting. 7: Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to

the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits

off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to ‘0’.

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,

REF

= 1VPP = 353mV

IN

@ 50/60 Hz.

RMS

Symbol Characteristic Min. Typ. Max. Units Test Conditions

REF

REF+

Voltage -2% 2.35 +2% V VREFEXT = 0

Tempco — 5 — ppm/°C VREFEXT = 0

REF

Output Impedance 7 — kΩ AVDD=5V,

REF

Differential Input Voltage Range (V

REF+

- V

REF-

)

Absolute Voltage on REFIN+

2.2 — 2.6 V V

1.9 — 2.9 V VREFEXT = 1

REF-

Absolute Voltage on REFIN-

-0.3 — +0.3 V V

Codes)

Sampling Frequency See Tab le 4 -2 kHz fS = DMCLK = MCLK / (4 x

S

Output Data Rate See Tab l e 4 -2 ksps fD = DRCLK= DMCLK / OSR

D

= -0.5 dBFS @ 50/60 Hz = 333 mV

RMS

, V

REF

= 2.4V.

ABSOLUTE MAXIMUM RATINGS †

VDD...................................................................................7.0V

Digital inputs and outputs w.r.t. A Analog input w.r.t. A

input w.r.t. A

V

REF

Storage temperature..................................... -65°C to +150°C

Ambient temp. with power applied................ -65°C to +125°C

Soldering temperature of leads (10 seconds)............. +300°C

ESD on the analog inputs (HBM,MM)................. 5.0 kV, 500V

ESD on all other pins (HBM,MM)........................ 5.0 kV, 500V

..................................... ....-6V to +6V

GND

................................-0.6V to VDD +0.6V

GND

= 4.5 to 5.5V, DVDD = 2.7 to

DD

VREFEXT = 0

VREFEXT = 1

to AGND when VREFEXT=0

24 bits OSR = 256 (see Table 5-2)

PRESCALE)

= MCLK / (4 x PRESCALE x OSR)

........-0.6V to VDD +0.6V

GND

= (V

REF

should be connected

REF-

REF+

- V

REF-

),

MCP3903

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

3.6V, Internal V GAIN = 1, V

Param.

Num.

A011 CHn+- Analog Input Absolute

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,

REF

= 1VPP = 353mV

IN

@ 50/60 Hz.

RMS

Symbol Characteristic Min. Typ. Max. Units Test Conditions

-1 +1 V All analog input channels,

Voltage

A012 A

Analog Input Leakage

IN

1nA(Note 4)

Current

A013 (CH

CH

A014 V

Differential Input Voltage

-

n+

)

Range

n-

Offset Error -3 3 mV (Note 6)(Note 2)

OS

500 /

GAIN

A015 Offset Error Drift 1 μV/C From -40°C to 125°C A016 GE Gain Error -3 3 % All Gains

A017 Gain Error Drift — 2 — ppm/°C From -40°C to 125°C

A018 INL Integral Non-Linearity 15 ppm GAIN = 1, DITHER = ON

A019 Z

A020 SINAD Signal-to-Noise and

Input Impedance 350 — — kΩ Proportional to 1/AMCLK

IN

89 91 — dB T = 25°C

Distortion Ratio

80 81.5 dB

A021 THD Total Harmonic Distortion -100 -97 dB OSR = 256, DITHER = ON;

-90 -87 dB

A022 SNR Signal To Noise Ratio 90 91.5 dB T = 25°C

80 81.5 dB

A023 SFDR Spurious Free Dynamic

102 dB OSR = 256, DITHER = ON;

Range

91 dB

A024 CTALK Crosstalk (50 / 60 Hz) — -115 — dB OSR = 256, DITHER = ON;

A025 AC PSRR AC Power Supply Rejection — -68 — dB AV

A026 DC PSRR DC Power Supply Rejection — -68 — dB AVDD = 4.5 to 5.5V, DVDD =

A027 CMRR DC Common Mode Rejection

—-75 — dBV

Ratio

Oscillator Input

Note 1: This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or

instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range, V

= -0.5 dBFS @ 50/60 Hz = 333 mV

IN

2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting. 7: Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to

the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits

off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to ‘0’.

RMS

, V

REF

= 2.4V.

= 4.5 to 5.5V, DVDD = 2.7 to

DD

measured to AGND

(Note 7)

mV

P

(Note 1)

(Note 2)(Note 3)

(Note 2) (Note 3)

(Note 2)(Note 3)

= 5V + 1Vpp @ 50 Hz

DD

3.3V

varies from -1V to +1V;

CM

(Note 2)

MCP3903

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

3.6V, Internal V GAIN = 1, V

Param.

Num.

A028 MCLK Master Clock Frequency

, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,

REF

= 1VPP = 353mV

IN

@ 50/60 Hz.

RMS

Symbol Characteristic Min. Typ. Max. Units Test Conditions

1 — 16.384 MHz (Note 8)

Range

Power Specifications

P001 AV

P002 DV

P003 AI

Operating Voltage, Analog 4.5 — 5.5 V

DD

Operating Voltage, Digital 2.7 — 3.6 V

DD

Operating Current, Analog

DD

7.1 9 mA BOOST bits low on all chan-

(Note 4)

12.3 16.8 mA BOOST bits high on all

P004 DI

Operating Current, Digital — 1.2 1.7 mA DVDD = 3.6V, MCLK =

DD

—2.4 3.4 mADV

P005 I

DDS,A

Shutdown Current, Analog — — 1 μA -40°C to 85°C, AV

—— 3 μA -40°C to 125°C, AV

P006 I

DDS,D

Shutdown Current, Digital — — 1 μA -40°C to 85°C, DV

—— 5 μA -40°C to 125°C, DV

Note 1: This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or

instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range, V

= -0.5 dBFS @ 50/60 Hz = 333 mV

IN

2: See terminology section for definition. 3: This parameter is established by characterization and not 100% tested. 4: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

5: For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

6: Applies to all gains. Offset error is dependant on PGA gain setting. 7: Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to

the part with no risk for damage.

8: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits

off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to ‘0’.

RMS

, V

REF

= 2.4V.

= 4.5 to 5.5V, DVDD = 2.7 to

DD

nels

channels

4MHz

= 3.6V, MCLK =

DD

8.192 MHz

only, (Note 5)

DD

MCP3903

1.2 SERIAL INTERFACE CHARACTERISTICS

SERIAL INTERFACE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

= 2.7 to 3.6V, -40°C < TA <+125°C, C

DV

DD

Parameters Sym Min Typ Max Units Conditions

LOAD

= 30 pF.

= 4.5 to 5.5V,

DD

Serial Clock frequency f

CS

setup time t

hold time

CS

disable time t

CS

Data setup time t

Data hold time t

Serial Clock high time t

Serial Clock low time t

Serial Clock delay time t

Serial Clock enable time t

Output valid from SCK low t

Output hold time t

Output disable time t

Reset Pulse Width (RESET

Data Transfer Time to DR

)t

(Data Ready) t

DODR

Data Ready Pulse Low Time t

Schmitt Trigger High-level Input voltage

SCK

CSS

t

CSH

CSD

SU

HD

HI

LO

CLD

CLE

DO

HO

DIS

MCLR

DRP

V

IH1

—— 10MHz2.7 ≤ DVDD < 3.6 50 — — ns 2.7 ≤ DVDD < 3.6

100 — — ns 2.7 ≤ DVDD < 3.6

50 — — ns — 10 — — ns 2.7 ≤ DVDD < 3.6 20 — — ns 2.7 ≤ DVDD < 3.6 40 — — ns 2.7 ≤ DVDD < 3.6 40 — — ns 2.7 ≤ DVDD < 3.6

50 — — ns —

50 — — ns — — — 50 ns 2.7 ≤ DVDD < 3.6

0——ns

— — 50 ns 2.7 ≤ DVDD < 3.6

100 — — ns 2.7 ≤ DVDD < 3.6

—50ns2.7 ≤ DVDD < 3.6

1/

DMCLK

.7 DV

—DVDD +1 V

DD

(All digital inputs)

Schmitt Trigger Low-level input voltage

V

IL1

-0.3 — 0.25

(All digital inputs)

Hysteresis of Schmitt Trigger Inputs

V

HYS

50 — mV

(All digital inputs)

Low-level output voltage, SDO pin V

Low-level output voltage, DRn

pins V

High-level output voltage, SDO pin V

OL

OH

— — 0.4 V SDO pin only, IOL = 2 mA,

DVDD -

— — V SDO pin only,

0.5

High-level output voltage, DRn

pins

only

Input leakage current I

Output leakage current I

Internal capacitance (all inputs and

V

OH

DVDD -

——VDRn pins only,

0.5

LI

LO

C

INT

— — ±1 µA CS = DVDD, Inputs tied to

—— 7 pFT

outputs)

Note 1: This parameter is periodically sampled and not 100% tested.

—µs2.7 ≤ DV

DD

V

DV

DD

DV

= 3.3V

DD

0.4 V DRn pins only, I

= +1.5 mA, DVDD =3.3V

OL

I

= -2 mA, DVDD = 3.3V

OH

I

= -1.5 mA, DVDD=3.3V

OH

OR DGND

DV

DD

OR DGND

DV

DD

= 25°C, SCK = 1.0 MHz

A

= 3.3V (Note 1)

DV

DD

< 3.6

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

3.3 V.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 28-lead

θ

SSOP

Note 1: The internal junction temperature (T

CS

f

SCK

t

HI

LO

SCK

-40 — +125 °C (Note 1)

A

-65 — +150 °C

A

JA

—71 — °C/W

) must not exceed the absolute maximum specification of +150°C.

J

MCP3903

= 4.5 to 5.5V, DVDD = 2.7 to

DD

t

CSH

Mode 1,1 Mode 0,0

t

DO

SDO

SDI

MSB out

Don’t Care

FIGURE 1-1: Serial Output Timing Diagram.

CS

SCK

SDI

SDO

t

CSS

Mode 1,1 Mode 0,0

t

SU

MSB in

t

HD

f

SCK

t

HI

LO

HI-Z

t

HO

LSB in

t

CSH

t

DIS

LSB out

t

CSD

t

CLE

t

CLD

FIGURE 1-2: Serial Input Timing Diagram.

MCP3903

H

DR

t

DODR

SCK

SDO

FIGURE 1-3: Data Ready Pulse Timing Diagram.

H

1 / DRCLK

t

DRP

Timing Waveform for t

DO

SCK

t

DO

SDO

Timing Waveform for MDAT0/1

Modulator Output

OSC1/CLKI

t

DOMDAT

MDAT0/1

FIGURE 1-4: Specific Timing Diagrams.

OSC1

OSC2

Digital Buffer

Crystal Oscillator

CLKEXT

1

MCLK AMCLK

0

Multiplexer Clock Divider Clock Divider Clock Divider

PRESCALE<1:0>

Prescale

1 /

CS

SDO

1 / 4

Timing Waveform for t

V

IH

90%

t

DIS

10%

OSR<1:0>

f

ADC

S

Sampling Rate

1 / OSR

DMCLK

DIS

HI-Z

ADC

f

D

Output Data Rate

DRCLK

FIGURE 1-5: MCP3903 Clock Detail.

MCP3903

2.0 TYPI CAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, AV

= 1; OSR = 64; GAIN = 1; Dithering OFF; V

.

= 5.0V, DV

DD

FIGURE 2-1: Spectral Response.

= 3.3 V; Internal V

DD

= -0.5 dBFS @ 60 Hz.

IN

; TA = +25°C, MCLK = 4 MHz; PRESCALE

REF

FIGURE 2-4: Spectral Response.

FIGURE 2-2: Spectral Response.

FIGURE 2-3: Spectral Response.

FIGURE 2-5: Spectral Response.

FIGURE 2-6: Spectral Response.

MCP3903

85

Note: Unless otherwise indicated, AV

64; GAIN = 1; Dithering OFF; V

.

IN

= 5.0V, DV

DD

= -0.5 dBFS @ 60 Hz.

FIGURE 2-7: Spectral Response.

120

ic

100

)

ynamic

80

60

ge (dB)

Free Dynamic

40

Range (dB)

ious Free Dynamic

20

Spurious Free Dynamic

0

32 64 128 256

Dithering ON

Dithering OFF

Oversampling Ratio (OSR)

FIGURE 2-8: Spurious Free Dynamic Range vs Oversampling Ratio.

= 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

DD

100

95

95 90

90

)

85

85 80

80

80 75

75

AD (dB)

70

SINAD (dB)

65

65 60

60

60 55

55

55 50

50

OSR = 64

OSR = 32

12481632

OSR = 256

OSR = 128

GAIN (V/V)

FIGURE 2-10: Signal-to-Noise and Distortion vs. Gain (Dithering OFF).

100

95

95 90

90

90 85

85

85 80

80

D (dB)

75

75 70

70

SINAD (dB)

65

65 60

60

60 55

55

55 50

50

OSR = 64

OSR = 32

12481632

OSR = 256

GAIN (V/V)

OSR = 128

FIGURE 2-11: Signal-to-Noise and Distortion vs. Gain (Dithering ON).

120

Dithering ON

100

)

80

60

AD (dB)

40

SINAD (dB)

20

0

Dithering OFF

32 64 128 256

Dithering ON

Oversampling Ratio (OSR)

FIGURE 2-9: Signal-to-Noise and Distortion vs. Oversampling Ratio.

FIGURE 2-12: Total Harmonic Distortion vs. Oversampling Ratio.

MCP3903

Note: Unless otherwise indicated, AV

64; GAIN = 1; Dithering OFF; V

.

-60

n

-70

tortion

-80

-90

Bc)

nic Distortion

(dBc)

-100

armonic Distortion

-110

-110 otal Harmonic Distortion Total Harmonic Distortion

Total Harmonic Distortion

-120

Dithering OFF

Dithering ON

20 50 100 200 500 1000 2000

Input Frequency (Hz)

IN

= 5.0V, DV

DD

= -0.5 dBFS @ 60 Hz.

fs=15.625KHz

fs=15.625KHz OSR=64

OSR=64

FIGURE 2-13: Total Harmonic Distortion vs. Input Signal Frequency.

0

on

-20

istortion

-40

-

-60

dBc)

onic Distortion

(dBc)

-80

fs=15.625KHz

fs=15.625KHz OSR=64

OSR=64

Harmonic Distortion

-100

Total Harmonic Distortion

-

-120

-40 -20 0 25 45 85 105 125

Temperature (°C)

°

FIGURE 2-14: Total Harmonic Distortion vs. Temperature.

= 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

DD

120

100

80

D (dB)

60

40

SINAD (dB)

20

0

-40 -20 0 25 45 85 105 125

Temperature (°C)

fs=15.625KHz

fs=15.625KHz OSR=64

OSR=64

FIGURE 2-16: Signal-to-Noise and Distortion vs. Temperature.

90

90 80

80

80 70

70

70 60

60

B)

50

50 40

40

AD (dB)

30

SINAD (dB)

20

20 10

10

0

-10

0.00001 0.001 0.1 10 1000

0.00001 0.001 0.1 10 1000 Input Signal Amplitude (mV)

FIGURE 2-17: Signal-to-Noise and Distortion vs. Input Signal Amplitude.

100

90

90 80

80

)

70

70 60

60

60 50

50

AD (dB)

40

SINAD (dB)

30

30 20

20

20 10

10

0

Dithering OFF

Dithering ON

=

fs=15.625KHz

fs=15.625KHz OSR=64

OSR=64

20 50 100 200 500 1000 2000

Input Frequency (Hz)

FIGURE 2-15: Signal-to-Noise and Distortion vs. Input Signal Frequency.

FIGURE 2-18: Signal-to-Noise and Distortion vs. Master Clock.

MCP3903

Note: Unless otherwise indicated, AV

64; GAIN = 1; Dithering OFF; V

1.40

1.20

1.00

(mV)

0.80

0.60

Error (mV)

0.40

0.20

ffset Error (mV)

0.00

Offset Error (mV)

-0.20

-

-0.40

G=1

G=4

G=32

-40 -20 0 25 45 85 105 125

Temperature (°C)

IN

= 5.0V, DV

DD

= -0.5 dBFS @ 60 Hz.

G=8

G=16

G=2

°

FIGURE 2-19: Offset Error vs. Temperature (Channel 0).

1.60

1.40

1.20

(mV)

1.00

0.80

Error (mV)

0.60

ffset Error (mV)

0.40

Offset Error (mV)

0.20

0.00

CH2

-40 -20 0 25 45 85 105 125

CH1

CH0

Temperature (°C)

CH3

CH4

CH5

FIGURE 2-20: Channel-to-Channel Offset Match vs. Temperature.

= 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

2.360

V)

2.355

rence (V)

2.350

Reference (V)

ltage Reference (V)

2.345

Int. Voltage Reference (V)

2.340

-40 -20 0 25 45 85 105 125

Temperature (°C)

°

FIGURE 2-22: Internal Voltage Reference vs. Temperature.

2.35473

2.35472

2.35471

ce (V)

2.35470

eference (V)

2.35469

ge Reference (V)

2.35468

2.35467

t. Voltage Reference (V)

2.35466

Int. Voltage Reference (V)

4.5 5 5.5

4.5 5 5.5 Power Supply (V)

FIGURE 2-23: Internal Voltage Reference vs. Supply Voltage.

0.00

G=1

G=16

G=1

-0.05

%)

-0.10

-

G=2

-0.15

Error (%)

-0.20

Gain Error (%)

-0.25

-0.30

G=2

G=32

G=4

-40 -20 0 25 45 85 105 125

G=8

Temperature (°C)

FIGURE 2-21: Gain Error vs. Temperature.

FIGURE 2-24: Noise Histogram.

MCP3903

Note: Unless otherwise indicated, AV

64; GAIN = 1; Dithering OFF; V

50

50 40

40

40 30

30

30 20

20

)

10

0

(ppm)

-10

INL (ppm)

-20

-30

-40

-50

-0.5 -0.25 0 0.25 0.5

CH1

Input Voltage (V)

IN

= 5.0V, DV

DD

= -0.5 dBFS @ 60 Hz.

FIGURE 2-25: Integral Non-Linearity (Dithering OFF).

50

50 40

40

40 30

30

30 20

20

20 10

10

0

ppm)

-10

-20

INL (ppm)

-30

-40

-

-50

-0.5 -0.25 0 0.25 0.5

-0.5 -0.25 0 0.25 0.5 Input Voltage (V)

Input Voltage (V)

CH0

CH1

CH0

= 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR =

DD

FIGURE 2-26: Integral Non-Linearity (Dithering ON).

9

8

7

6

5

(mA)

4

IDD (mA)

3

2

1

0

1234

AIDD Boost OFF

DIDD

MCLK Frequency(MHz)

FIGURE 2-27: Operating Current vs. Master Clock (MCLK).

MCP3903

3.0 PIN DESCRIPTION

TABLE 3-1: PIN FUNCTION TABLE

Pin No. Symbol Function

1AV

2 CH0+ Non-Inverting Analog Input Pin for Channel 0

3 CH0- Inverting Analog Input Pin for Channel 0

4 CH1- Inverting Analog Input Pin for Channel 1

5 CH1+ Non-Inverting Analog Input Pin for Channel 1

6 CH2+ Non-Inverting Analog Input Pin for Channel 2

7 CH2- Inverting Analog Input Pin for Channel 2

8 CH3- Inverting Analog Input Pin for Channel 3

9 CH3+ Non-Inverting Analog Input Pin for Channel 3

10 CH4+ Non-Inverting Analog Input Pin for Channel 4

11 CH4- Inverting Analog Input Pin for Channel 4

12 CH5- Inverting Analog Input Pin for Channel 5

13 CH5+ Non-Inverting Analog Input Pin for Channel 5

14 REFIN+/OUT Non-Inverting Voltage Reference Input and Internal Reference Output Pin

15 REFIN- Inverting Voltage Reference Input Pin

16 A

17 D

18 DR

19 DR

20 DR

21 OSC1 Oscillator Crystal Connection Pin or Clock Input Pin

22 OSC2 Oscillator Crystal Connection Pin

23 CS

24 SCK Serial Interface Clock Pin

25 SDO Serial Interface Data Output Pin

26 SDI Serial Interface Data Input Pin

27 RESET

28 DV

DD

GND

A Data Ready Signal Output for channels pair A

B Data Ready Signal Output for channels pair B

C Data Ready Signal Output for channels pair C

DD

Analog Power Supply Pin

Analog Ground Pin, Return Path for internal analog circuitry

Digital Ground Pin, Return Path for internal digital circuitry

Chip Select for Serial Interface

Master Reset Logic Input Pin

Digital Power Supply Pin

3.1 RESET

This pin is active low and places the entire chip in a reset state when active.

When RESET value, no communication can take place, no clock is distributed inside the part. This state is equivalent to a POR state.

Since the default state of the ADCs is on, the analog power consumption when RESET when RESET is largely reduced because this current consumption is essentially dynamic and is reduced drastically when there is no clock running. All the analog biases are

=0, all registers are reset to their default

= 0 is equivalent to

= 1. Only the digital power consumption

enabled during a reset so that the part is fully operational just after a RESET is Schmitt triggered.

3.2 Digital V

DV

is the power supply pin for the digital circuitry

DD

within the MCP3903. This pin requires appropriate bypass capacitors and should be maintained between

2.7V and 3.6V for specified operation.

DD

(DV

rising edge. This input

)

DD

MCP3903

3.3 Analog V

AV

is the power supply pin for the analog circuitry

DD

within the MCP3903.

This pin requires appropriate bypass capacitors and should be maintained to 5V ±10% for specified operation.

DD

(AV

DD

)

3.4 ADC Differential Analog Inputs(CHn+/CHn-)

CHn- and CHn+, are the two fully-differential analog voltage inputs for the Delta-Sigma ADCs. There are six channels in total grouped in three channel pairs.

The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±500 mV/GAIN with

= 2.4V. The maximum absolute voltage, with

V

REF

respect to AGND, for each CHn+/- input pin is +/-1V with no distortion and ±6V with no breaking after continuous voltage.

3.5 Analog Ground (AGND)

AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). To ensure accuracy and noise cancellation, this pin must be connected to the same ground as DGND, preferably with a star connection. If an analog ground plane is available, it is recommended that this pin be tied to this plane of the PCB. This plane should also reference all other analog circuitry in the system.

3.6 Non-Inverting Reference Input, Internal Reference Output (REFIN+/OUT)

This pin is the non-inverting side of the differential voltage reference input for all ADCs or the internal voltage reference output. When VREFEXT = 1, and an external voltage reference source can be used, the internal voltage reference is disabled. When using an external differential voltage reference, it should be connected to its V

When using an external single-ended reference, it should be connected to this pin.

When VREFEXT = 0, the internal voltage reference is enabled and connected to this pin through a switch. This voltage reference has minimal drive capability and thus needs proper buffering and bypass capacitances (10 μF tantalum in parallel with 0.1 μF ceramic) if used as a voltage source.

For optimal performance, bypass capacitances should be connected between this pin and AGND at all times even when the internal voltage reference is used.

REF+

pin.

3.7 Inverting Reference Input (REFIN-)

This pin is the inverting side of the differential voltage reference input for both ADCs. When using an external differential voltage reference, it should be connected to its V voltage reference, or when VREFEXT = 0 (Default) and using the internal voltage reference, this pin should be directly connected to AGND.

pin. When using an external single-ended

REF-

3.8 Digital Ground Connection (DGND)

DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). To ensure accuracy and noise cancellation, DGND must be connected to the same ground as AGND, preferably with a star connection. If a digital ground plane is available, it is recommended that this pin be tied to this plane of the Printed Circuit Board (PCB). This plane should also reference all other digital circuitry in the system.

3.9 DRn (Data Ready Pins)

The Data Ready pins indicate if a new conversion result is ready to be read on each of the A, B and C pairs of ADCs. The default state of this pin is high when DR_HIZN=1 and is high impedance when DR_HIZN=0 (Default). After each conversion is finished, a low pulse will take place on the data ready pins to indicate the conversion result is ready as an interrupt. This pulse is synchronous with the master clock and has a defined and constant width.

The Data Ready pins are independent of the SPI interface and act like an interrupt output.The Data Ready pins state is not latched and the pulse width (and period) are both determined by the MCLK frequency, over-sampling rate, and internal clock prescale settings. The DR pulse width is equal to one DMCLK period and the frequency of the pulses is equal to DRCLK (see Figure 1-3).

Note: These pins should not be left floating

when DR_HIZ resistor connected to DV mended.

bit is low; a 100kΩ pull-up

is recom-

DD

MCP3903

3.10 Oscillator And Master Clock Input Pins (OSC1/CLKI, OSC2)

OSC1/CLKI and OSC2 provide the master clock for the device. When CLKEXT = 0 (Default), a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 4 MHz. However, the clock frequency can be 1 MHz to 5 MHz without disturbing ADC accuracy. With the current boost circuit enabled, the master clock can be used up to 8.192 MHz without disturbing ADC accuracy. Appropriate load capacitance should be connected to these pins for proper operation.

Note: When CLKEXT = 1, the crystal oscillator

is disabled, as well as the OSC2 input. The OSC1 becomes the master clock input CLKI, direct path for an external clock source, for example a clock source generated by an MCU.

3.11 CS (Chip Select)

This pin is the SPI Chip Select that enables the serial communication. When this pin is high, no communication can take place. A chip select falling edge initiates the serial communication and a chip select rising edge terminates the communication. No communication can take place even when CS and when RESET

This input is Schmitt-triggered.

is low.

is low

3.12 SCK (Serial Data Clock)

This is the serial clock pin for SPI communication. Data is clocked into the device on the RISING edge of SCK. Data is clocked out of the device on the FALLING edge of SCK. The MCP3903 interface is compatible with both SPI 0,0 and 1,1 modes. The maximum clock speed specified is 10 MHz. This input is Schmitt triggered.

3.13 SDO (Serial Data Output)

This is the SPI data output pin. Data is clocked out of the device on the FALLING edge of SCK. This pin stays at high impedance during the control byte. It also stays at high impedance during the whole communication for write commands and when the CS pin is high or when the RESET pin is low. This pin is active only when a read command is processed. Each read is processed by a packet of 24 bits (size of each register), except on the ADC output registers when WIDTH=0.

3.14 SDI (Serial Data Input)

This is the SPI data input pin. Data is clocked into the device on the RISING edge of SCK. When CS is low, this pin is used to communicate with a series of 8-bit commands. The interface is half-duplex (inputs and outputs do not happen at the same time). Each communication starts with a chip select falling edge followed by an 8-bit control byte entered through the SDI pin. Each write is processed by packets of 24 bits (size of each register). Each command is either a Read or a Write command. Toggling SDI during a Read command has no effect. This input is Schmitt-triggered.

MCP3903

4.0 TERMINOLOGY AND FORMULAS

This section defines the terms and formulas used throughout this data sheet. The following terms are defined:

MCLK - Master Clock

AMCLK - Analog Master Clock

DMCLK - Digital Master Clock

DRCLK - Data Rate Clock

OSR - Oversampling Ratio

Offset Error

Gain Error

Integral Non-Linearity Error

Signal-To-Noise Ratio (SNR)

Signal-To-Noise Ratio And Distortion (SINAD)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

MCP3903 Delta-Sigma Architecture

Idle Tones

Dithering

Crosstalk

PSRR

CMRR

ADC Reset Mode

Hard Reset Mode (RESET = 0)

ADC Shutdown Mode

Full Shutdown Mode

4.1 MCLK - Master Clock

4.2 AMCLK - Analog Master Clock

This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG PRESCALE<1:0> register bits. The analog portion includes the PGAs and the two sigma-delta modulators.

EQUATION 4-1:

AMCLK

MCLK

------------------------------ -=

PRESCALE

T ABLE 4-1: MCP3903 OVERSAMPLING

RATIO SETTINGS

Config

PRE<1:0>

00AMCLK = MCLK/ 1 (default) 01 AMCLK = MCLK/ 2 10 AMCLK = MCLK/ 4 11 AMCLK = MCLK/ 8

Analog Master Clock

Prescale

4.3 DMCLK - Digital Master Clock

This is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. This is also the sampling frequency, that is the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output.

EQUATION 4-2:

DMCLK

AMCLK

--------------------4

MCLK

----------------------------------------== 4 PRESCALE×

This is the fastest clock present in the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1.

4.4 DRCLK - Data Rate Clock

This is the output data rate i.e. the rate at which the ADCs output new data. Each new data is signaled by a data ready pulse on the DR pin.

This data rate is depending on the OSR and the prescaler with the following formula:

EQUATION 4-3:

DMCLK

DRCLK

---------------------OSR

AMCLK

--------------------4OSR×

-----------------------------------------------------------=== 4 OSR PRESCALE××

MCLK

MCP3903

Since this is the output data rate, and since the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate.

The following table describes the various combinations of OSR and PRESCALE and their associated AMCLK, DMCLK and DRCLK rates.

TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR, AND PRESCALE

PRE

<1:0>

1 1 1 1 256 MCLK/8 MCLK/32 MCLK/8192 0.4882

1 1 1 0 128 MCLK/8 MCLK/32 MCLK/4096 0.976

1 1 0 1 64 MCLK/8 MCLK/32 MCLK/2048 1.95

1 1 0 0 32 MCLK/8 MCLK/32 MCLK/1024 3.9

1 0 1 1 256 MCLK/4 MCLK/16 MCLK/4096 0.976

1 0 1 0 128 MCLK/4 MCLK/16 MCLK/2048 1.95

1 0 0 1 64 MCLK/4 MCLK/16 MCLK/1024 3.9

1 0 0 0 32 MCLK/4 MCLK/16 MCLK/512 7.8125

0 1 1 1 256 MCLK/2 MCLK/8 MCLK/2048 1.95

0 1 1 0 128 MCLK/2 MCLK/8 MCLK/1024 3.9

0 1 0 1 64 MCLK/2 MCLK/8 MCLK/512 7.8125

0 1 0 0 32 MCLK/2 MCLK/8 MCLK/256 15.625

0 0 1 1 256 MCLK MCLK/4 MCLK/1024 3.9

0 0 1 0 128 MCLK MCLK/4 MCLK/512 7.8125

000164 MCLK MCLK/4 MCLK/256 15.625

0 0 0 0 32 MCLK MCLK/4 MCLK/128 31.25

Note: For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1.

OSR <1:0> OSR AMCLK DMCLK DRCLK

DRCLK

(ksps)

4.5 OSR - Oversampling Ratio

The ratio of the sampling frequency to the output data rate is OSR = DMCLK/DRCLK. The default OSR is 64, or with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 MHz, f in the CONFIG1 register are used to change the oversampling ratio (OSR).

TABLE 4-3: MCP3903 OVERSAMPLING

= 1 MHz, fD = 15.625 ksps. The following bits

S

RATIO SETTINGS

CONFIG OVER SAMPLING RATIO

OSR<1:0>

00 32 01 64 (DEFAULT) 10 128 11 256

(OSR)

4.6 Offset Error

This is the error induced by the ADC when the inputs are shorted together (V incorporates both PGA and ADC offset contributions. This error varies with PGA and OSR settings. The offset is different on each channel and varies from chip to chip. This offset error can easily be calibrated out by a MCU with a subtraction. The offset is specified in mV.

The offset on the MCP3903 has a low temperature

coefficient, see Section 2.0 “Typical Performance

Curves”.

= 0V). The specification

IN

4.7 Gain Error

This is the error induced by the ADC on the slope of the transfer function. It is the deviation expressed in % compared to the ideal transfer function defined by

Equation 5-3. The specification incorporates both PGA

and ADC gain error contributions, but not the V contribution (it is measured with an external V error varies with PGA and OSR settings.

The gain error on the MCP3903 has a low temperature coefficient. See the typical performance curves for more information.

REF

).This

MCP3903

4.8 Integral Non-Linearity Error

Integral non-linearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero.

It is the maximum remaining error after calibration of offset and gain errors for a DC input signal.

4.9 Signal-To-Noise Ratio (SNR)

For the MCP3903 ADC, the signal-to-noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal), when the input is a sinewave at a predetermined frequency. It is measured in dB. Usually, only the maximum signal to noise ratio is specified. The SNR figure depends mainly on the OSR and DITHER settings of the device.

EQUATION 4-4: SIGNAL-TO-NOISE RATIO

SignalPower

SNR dB() 10

⎛⎞

----------------------------------

log=

⎝⎠

NoisePower

4.10 Signal-To-Noi se Ratio And Distortion (SINAD)

The most important figure of merit for the analog performance of the ADCs present on the MCP3903 is the Signal-to-Noise And Distortion (SINAD) specification.

Signal-to-noise and distortion ratio is similar to signalto-noise ratio, with the exception that you must include the harmonics power in the noise power calculation. The SINAD specification depends mainly on the OSR and DITHER settings.

EQUATION 4-5: SINAD EQUATION

4.1 1 Tot al Harmonic Distortion (THD)

The total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sinewave input and is defined by the following equation.

EQUATION 4-7:

HarmonicsPower

THD dB() 10

The THD calculation includes the first 35 harmonics for the MCP3903 specifications. The THD is usually only measured with respect to the 10 first harmonics. THD is sometimes expressed in %. For converting the THD in %, here is the formula:

⎛⎞

---------------------------------------------------- -

log=

⎝⎠

FundamentalPower

EQUATION 4-8:

THD dB()

------------------ ------

THD %() 100 10

This specification depends mainly on the DITHER setting.

20

×=

4.12 Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio between the output power of the fundamental and the highest spur in the frequency spectrum. The spur frequency is not necessarily a harmonic of the fundamental even though it is usually the case. This figure represents the dynamic range of the ADC when a full-scale signal is used at the input. This specification depends mainly on the DITHER setting.

SignalPower

SINAD dB() 10

The calculated combination of SNR and THD per the following formula also yields SINAD:

⎛⎞

--------------------------------------------------------------------

log=

⎝⎠

Noise HarmonicsPower+

EQUATION 4-9:

SFDR dB() 10

FundamentalPower

⎛⎞

---------------------------------------------------- -

log=

⎝⎠

HighestSpurPower

EQUATION 4-6: SINAD, THD, AND SNR

RELATIONSHIP

SNR

⎛⎞

---------- -

⎝⎠

SINAD dB() 10 10

10

⎛⎞ ⎝⎠

10

+log=

THD–

--------------- 10

MCP3903

4.13 MCP3903 Delta-Sigma Architecture

The MCP3903 incorporates six Delta-Sigma ADCs with a multi-bit digital to analog converter as quantizer. A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator which is digitizing the quantity of charge integrated by the modulator loop (see Figure 5-1). The quantizer is the block that is performing the analog-to-digital conversion. The quantizer is typically 1-bit, or a simple comparator which helps to maintain the linearity performance of the ADC (the DAC structure is inherently linear in this case).

Multi-bit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the OSR, which leads to better SNR figures. However, typically, the linearity of such architectures is more difficult to achieve since the DAC is no more simple to realize and its linearity limits the THD of such ADCs.

The MCP3903’s 5-level quantizer is a flash ADC composed of 4 comparators arranged with equally spaced thresholds and a thermometer coding. The MCP3903 also includes proprietary 5-level DAC architecture that is inherently linear for improved THD figures.

4.14 Idle Tones

A Delta-Sigma converter is an integrating converter. It also has a finite quantization step (LSB) which can be detected by its quantizer. A DC input voltage that is below the quantization step should only provide an all zeros result since the input is not large enough to be detected. As an integrating device, any Delta-Sigma will show, in this case, idle tones. This means that the output will have spurs in the frequency content that are depending on the ratio between quantization step voltage and the input voltage. These spurs are the result of the integrated sub-quantization step inputs that will eventually cross the quantization steps after a long enough integration. This will induce an AC frequency at the output of the ADC and can be shown in the ADC output spectrum.

These idle tones are residues that are inherent to the quantization process and the fact that the converter is integrating at all times without being reset. They are residues of the finite resolution of the conversion process. They are very difficult to attenuate and they are heavily signal dependent. They can degrade both SFDR and THD of the converter, even for DC inputs. They can be localized in the baseband of the converter and thus difficult to filter from the actual input signal.

For power metering applications, idle tones can be very disturbing because energy can be detected even at the 50 or 60 Hz frequency, depending on the DC offset of the ADCs, while no power is really present at the inputs. The only practical way to suppress or attenuate idle tones phenomenon is to apply dithering to the ADC. The idle tones amplitudes are a function of the order of the modulator, the OSR and the number of levels in the quantizer of the modulator. A higher order, a higher OSR, or a higher number of levels for the quantizer will attenuate the idle tones amplitude.

4.15 Dithering

In order to suppress or attenuate the idle tones present in any Delta-Sigma ADCs, dithering can be applied to the ADC. Dithering is the process of adding an error to the ADC feedback loop in order to “decorrelate” the outputs and “break” the idle tone’s behavior. Usually a random or pseudo-random generator adds an analog or digital error to the feedback loop of the delta-sigma ADC in order to ensure that no tonal behavior can happen at its outputs. This error is filter by the feedback loop and typically has a zero average value so that the converter static transfer function is not disturbed by the dithering process. However, the dithering process slightly increases the noise floor (it adds noise to the part) while reducing its tonal behavior and thus improving SFDR and THD. The dithering process scrambles the idle tones into baseband white noise and ensures that dynamic specs (SNR, SINAD, THD, SFDR) are less signal dependent. The MCP3903 incorporates a proprietary dithering algorithm on all ADCs in order to remove idle tones and improve THD, which is crucial for power metering applications.

MCP3903

4.16 Crosstalk

The crosstalk is defined as the perturbation caused by one ADC channel on the other ADC channel. It is a measurement of the isolation between the six ADCs present in the chip.

This measurement is a two-step procedure:

1. Measure one ADC input with no perturbation on any other ADC (ADC inputs shorted).

2. Measure the same ADC input with a perturbation sine wave signal on the other ADC at a certain predefined frequency.

The crosstalk is then the ratio between the output power of the ADC when the perturbation is present and when it is not divided by the power of the perturbation signal.

A lower crosstalk value implies more independence and isolation between the six channels.

The measurement of this signal is performed under the following conditions:

•GAIN = 1,

• PRESCALE = 1,

• OSR = 256,

• MCLK = 4 MHz

EQUATION 4-11:

Δ

V

OUT

PSRR dB() 20

Where V output code translates to with the ADC transfer function. In the MCP3903 specification, AVDD varies from 4.5V to 5.5V, and for AC PSRR a 50/60 Hz sinewave is chosen, centered around 5V with a maximum 500 mV amplitude. The PSRR specification is measured with

is the equivalent input voltage that the

OUT

DV

DD

⎛⎞

------------------ -

log=

⎝⎠

Δ

= 3.3V.

AV

DD

4.18 CMRR

This is the ratio between a change in the Common-Mode input voltage and the ADC output codes. It measures the influence of the Common-Mode input voltage on the ADC outputs.

The CMRR specification can be DC (the common-mode input voltage is taking multiple DC values) or AC (the common-mode input voltage is a sinewave at a certain frequency with a certain common mode). In AC, the amplitude of the sinewave is representing the change in the power supply.

It is defined as:

Step 1

• CH0+=CH0-=AGND

• CHn+=CHn-=AGND, n different than 0

Step 2

• CH0+=CH0-=AGND

• CHn+ - CHn-=1V

wave)

The crosstalk is then calculated with the following formula:

@ 50/60 Hz (Full-scale sine

P-P

EQUATION 4-10:

Δ

CH0Power

⎛⎞

---------------------------------

CTalk dB() 10

log=

⎝⎠

Δ

CHnPower

4.17 PSRR

This is the ratio between a change in the power supply voltage and the ADC output codes. It measures the influence of the power supply voltage on the ADC outputs.

The PSRR specification can be DC (the power supply is taking multiple DC values) or AC (the power supply is a sinewave at a certain frequency with a certain common mode). In AC, the amplitude of the sinewave is representing the change in the power supply.

It is defined as:

EQUATION 4-12:

Δ

V

OUT

CMRR dB() 20

Where VCM= (CHn+ + CHn-)/2 is the Common-Mode input voltage and V that the output code translates to with the ADC transfer function. In the MCP3903 specification, VCM varies from -1V to +1V, and for AC specification a 50/60 Hz sinewave is chosen centered around 0V with a 500 mV amplitude.

is the equivalent input voltage

OUT

⎛⎞

-----------------

log=

⎝⎠

Δ

V

CM

4.19 ADC Reset Mode

ADC Reset mode (called also soft reset mode) can only be entered through setting high the RESET<5:0> bits in the configuration register. This mode is defined as the condition where the converters are active but their output is forced to 0.

The registers are not affected in this reset mode and retain their values.

The ADCs can immediately output meaningful codes after leaving reset mode (and after the sinc filter settling time of 3/DRCLK). This mode is both entered and exited through setting of bits in the configuration register.

Each converter can be placed in soft reset mode independently. The configuration registers are not modified by the soft reset mode.

MCP3903

A data ready pulse will not be generated by any ADC while in reset mode.

When an ADC exists ADC reset mode, any phase delay present before reset was entered will still be present. If one ADC was not in reset, the ADC leaving reset mode will automatically resynchronize the phase delay relative to the other ADC channel, per the phase delay register block and give data ready pulses accordingly.

If an ADC is placed in Reset mode while the other is converting, it is not shutting down the internal clock. When going back out of reset, it will be resynchronized automatically with the clock that did not stop during reset.

If all ADCs are in soft reset or shutdown modes, the clock is no longer distributed to the digital core for low power operation. Once the ADC is back to normal operation, the clock is automatically distributed again.

4.20 Hard Reset Mode (RESET = 0)

This mode is only available during a POR or when the

pin is pulled low. The RESET pin low state

RESET places the device in a hard reset mode.

In this mode, all internal registers are reset to their default state.

The DC biases for the analog blocks are still active, i.e. the MCP3903 is ready to convert. However, this pin clears all conversion data in the ADCs. The comparator outputs of all ADCs are forced to their reset state (0011). The SINC filters are all reset, as well as their double output buffers. See serial timing for minimum

pulse low time, in Section 1.0 “Electrical

Characteristics”.

During a hard reset, no communication with the part is possible. The digital interface is maintained in a reset state.

4.21 ADC Shutdown Mode

ADC shutdown mode is defined as a state where the converters and their biases are off, consuming only leakage current. After this is removed, start-up delay time (SINC filter settling time) will occur before outputting meaningful codes. The start-up delay is needed to power-up all DC biases in the channel that was in shutdown. This delay is the same than t any DR discarded.

Each converter can be placed in shutdown mode independently. The CONFIG registers are not modified by the shutdown mode. This mode is only available through programming of the SHUTDOWN<5:0> bits in the CONFIG register.

The output data is flushed to all zeros while in ADC shutdown. No data ready pulses are generated by any ADC while in ADC shutdown mode.

pulse coming within this delay should be

POR

and

When an ADC exits ADC shutdown mode, any phase delay present before shutdown was entered will still be present. If one ADC was not in shutdown, the ADC leaving shutdown mode will automatically resynchronize the phase delay relative to the other ADC channel, per the phase delay register block and give data ready pulses accordingly.

If an ADC is placed in shutdown while others are converting, then the internal clock will not shut down. When going back out of shutdown, it will be automatically resynchronized with the clock that did not stop during reset.

If all ADCs are in ADC reset or ADC shutdown modes, the clock is not distributed to the digital core for low power operation. Once any of the ADC is back to normal operation, the clock is automatically distributed again.

4.22 Full Shutdown Mode

The lowest power consumption can be achieved when SHUTDOWN<5:0>=111111, VREFEXT=CLKEXT= 1. This mode is called “Full shutdown mode”, and no analog circuitry is enabled. In this mode, the POR A monitoring circuit is also disabled. When the clock is idle (OSC1 = high or low continuously), no clock is propagated throughout the chip. All ADCs are in shutdown, the internal voltage reference is disabled and the internal oscillator is disabled.

The only circuit that remains active is the SPI interface but this circuit does not induce any static power consumption. If SCK is idle, the only current consumption comes from the leakage currents induced by the transistors and is less than 1 µA on each power supply, for temperatures lower than 85°C.

This mode can be used to power down the chip completely and avoid power consumption when there is no data to convert at the analog inputs. Any SCK or MCLK edge coming while in this mode will induce dynamic power consumption.

Once any of the SHUTDOWN, CLKEXT and VREFEXT bits returns to 0, the POR AV back to operation and AV

DD

monitoring block is

DD

monitoring can take place.

VDD

MCP3903

5.0 DEVICE OVERVIEW

5.1 Analog Inputs (CHn+/-)

The MCP3903 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or Rogowski coils). Each input pin is protected by specialized ESD structures that are certified to pass 5 kV HBM and 500V MM contact charge. These structures allow bipolar ±6V continuous voltage with respect to AGND, to be present at their inputs without the risk of permanent damage.

All channels have fully differential voltage inputs for better noise performance. The absolute voltage at each pin relative to AGND should be maintained in the ±1V range during operation in order to ensure the specified ADC accuracy. The Common-Mode signals should be adapted to respect both the previous conditions and the differential input voltage range. For best performance, the Common-Mode signals should be maintained to AGND.

5.2 Programmable Gain Amplifiers

(PGA)

The six Programmable Gain Amplifiers (PGAs) reside at the front-end of each Delta-Sigma ADC. They have two functions: translate the common-mode of the input from AGND to an internal level between AGND and

, and amplify the input differential signal. The

A

VDD

translation of the common mode does not change the differential signal but recenters the common-mode so that the input signal can be properly amplified.

The PGA block can be used to amplify very low signals, but the differential input range of the delta-sigma modulator must not be exceeded. The PGA is controlled by the PGA_CHn<2:0> bits in the GAIN register. The following table represents the gain settings for the PGA:

TABLE 5-1: PGA CONFIGURATION

SETTING

Gain

PGA_CHn<2:0>

000 10±0.5 001 26±0.25 010 412±0.125 011 8 18 ±0.0625 10016 24 ±0.03125 10132 30 ±0.015625

Gain (V/V)

Gain

(dB)

VIN Range

(V)

5.3 Delta-Sigma Modulator

5.3.1 ARCHITECTURE

All ADCs are identical in the MCP3903 and they include a second-order modulator with a multi-bit DAC architecture (see Figure 5-1). The quantizer is a flash ADC composed of 4 comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing linearity or inducing additional distortion. The sampling frequency is DMCLK (typically 1 MHz with MCLK=4 MHz) so the modulator outputs are refreshed at a DMCLK rate. The modulator outputs are available in the MOD register.

Each modulator also includes a dithering algorithm that can be enabled through the DITHER<5:0> bits in the configuration register. This dithering process improves THD and SFDR (for high OSR settings) while increasing slightly the noise floor of the ADCs. For power metering applications and applications that are distortion-sensitive, it is recommended to keep DITHER enabled for all ADCs. In the case of power metering applications, THD and SFDR are critical specifications to optimize SNR (noise floor). This is not really problematic due to large averaging factor at the output of the ADCs, therefore even for low OSR settings, the dithering algorithm will show a positive impact on the performance of the application.

Figure 5-1 represents a simplified block diagram of the

Delta-Sigma ADC present on MCP3903.

Loop

Filter

Differential Voltage Input

Second-

Order

Integrator

MCP3903 Sigma-Delta Modulator

FIGURE 5-1: Simplified Delta-Sigma ADC Block Diagram.

Quantizer

5-level

Flash ADC

DAC

Output

Bitstream

MCP3903

5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT

For a specified voltage reference value of 2.4V, the modulator specified differential input range is ±500 mV. The input range is proportional to V according to the V stability of the modulator over amplitude and frequency. Outside of this range, the modulator is still functional, however its stability is no longer guaranteed and therefore it is not recommended to exceed this limit. The saturation point for the modulator is V the transfer function of the ADC includes a gain of 3 by default (independent from the PGA setting. See

Section 5.5 “ADC OUTPUT CODING”).

voltage. This range ensures the

REF

5.3.3 BOOST MODE

The Delta-Sigma modulators also include an independent BOOST mode for each channel. If the corresponding BOOST<1:0> bit is enabled, the power consumption of the modulator is multiplied by 2 and its bandwidth is increased to be able to sustain AMCLK clock frequencies up to 8.192 MHz while keeping the ADC accuracy. When disabled, the power consumption returns back to normal and the AMCLK clock frequencies can only reach up to 5 MHz without affecting ADC accuracy.

and scales

REF

/3 since

MCP3903

5.4 SINC3 Filter

All ADCs present in the MCP3903 include a decimation filter that is a third-order sinc (or notch) filter. This filter processes the multi-bit bitstream into 16 or 24 bits words (depending on the WIDTH configuration bit). The settling time of the filter is 3 DMCLK periods. It is recommended to discard unsettled data to avoid data corruption which can be done easily by setting the DR_LTY bit high in the STATUS/COM register.

The resolution achievable at the output of the sinc filter (the output of the ADC) is dependant on the OSR and is summarized in the following table:

TABLE 5-2: ADC RESOLUTION VS. OSR

ADC

Resolution

OSR<1:0> OSR

00 32 17 01 64 20 10 128 23 11 256 24

For 24 -bit output mode (WIDTH = 1), the output of the sinc filter is padded with least significant zeros for any resolution less than 24 bits.

For 16-bit output modes, the output of the sinc filter is rounded to the closest 16-bit number in order to conserve only 16-bit words and to minimize truncation error.

The gain of the transfer function of this filter is 1 at each multiple of DMCLK (typically 1 MHz) so a proper anti-aliasing filter must be placed at the inputs to attenuate the frequency content around DMCLK, and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple first-order RC network, with a sufficiently low time constant to generate high rejection at DMCLK frequency.

(bits)

No Missing

Codes

The Normal-Mode Rejection Ratio (NMRR), or gain of the transfer function, is shown in the following equation:

EQUATION 5-2: MAGNITUDE OF

FREQUENCY RESPONSE H(f)

π

--------------------⋅ DRCLK

π

----------------------⋅ DMCLK

f

NMRR f()

⎛⎞

c

sin

=

⎝⎠

----------------------------------------------

⎛⎞

sin

c

⎝⎠

3

or:

3

f

⎛⎞

c π

-----⋅

⎝⎠

f

D

f

⎛⎞

--- -⋅

c π

⎝⎠

f

S

NMRR f()

sin

=

----------------------------sin

where:

cx()sin

x()sin

---------------=

x

Figure 5-2 shows the sinc filter frequency response:

20

0

-20

-40

-60

-80

Magnitude (dB)

-100

-120

1 10 100 1000 10000 100000 1000000

Input Frequency (Hz)

FIGURE 5-2: SINC Filter Response with MCLK = 4 MHz, OSR = 64, PRESCALE = 1.

EQUATION 5-1: SINC FILTER TRANSFER

FUNCTION H(Z)

3

Hz()

⎛⎞

=

⎜⎟ ⎝⎠

Where:

z

exp=

OSR–

–

1z

--------------------------------OSR 1 z

⎛⎞

----------------------

⎝⎠

DMCLK

1–

–()

2πfj

MCP3903

5.5 ADC OUTPUT CODING

The second order modulator, SINC3 filter, PGA, V and analog input structure all work together to produce the device transfer function for the analog to digital conversion, shown in Equation 5-3.

The channel data is either a 16-bit or 24-bit word, presented in 23-bit or 15-bit plus sign, two’s complement format and is MSB (left) justified.

The ADC data is two or three bytes wide depending on the WIDTH bit of the associated channel. The 16-bit mode includes a round to the closest 16-bit word (instead of truncation) in order to improve the accuracy of the ADC data.

EQUATION 5-3:

DATA_CHn

CH

⎛⎞

-------------------------------------

⎝⎠

V

REF+

CH

⎛⎞

-------------------------------------

⎝⎠

V

REF+VREF-

CH

–()

n+

V

–

CH

–()

n+

–

5.5.1 ADC RESOLUTION AS A FUNCTION OF OSR

The ADC resolution is a function of the OSR

(Section 5.4 “SINC3 Filter”). The resolution is the

same for both channels. No matter what the resolution is, the ADC output data is always presented in 24-bit words, with added zeros at the end if the OSR is not large enough to produce 24-bit resolution (left justification).

REF

n-

REF-

n-

In case of positive saturation (CHn+ - CHn- > V the output is locked to 7FFFFF for 24 bit mode (7FFF for 16 bit mode). In case of negative saturation (CHn+

- CHn- <-V for 24-bit mode (8000 for 16 bit mode).

Equation 5-3 is only true for DC inputs. For AC inputs,

this transfer function needs to be multiplied by the transfer function of the SINC and Equation 5-2).

8,388,608 G 3×××=

32 768,G3×××=

/3), the output code is locked to 800000

REF

3

filter (see Equation 5-1

(For 24-bit Mode Or WIDTH_CHn = 1)

(For 16-bit Mode Or WIDTH_CHn = 0)

REF

/3),

TABLE 5-3: OSR = 256 OUTPUT CODE EXAMPLES

ADC Output Code (MSB First) Hexadecimal Decimal

0111 1111 1111 1111 1111 1111 0x7FFFFF + 8,388,607 0111 1111 1111 1111 1111 1110 0x7FFFFE + 8,388,606 0000 0000 0000 0000 0000 0000 0x000000 0 1111 1111 1111 1111 1111 1111 0xFFFFFF -1 1000 0000 0000 0000 0000 0001 0x800001 - 8,388,607 1000 0000 0000 0000 0000 0000 0x800000 - 8,388,608

TABLE 5-4: OSR = 128 OUTPUT CODE EXAMPLES

ADC Output Code (MSB First) Hexadecimal

0111 1111 1111 1111 1111 111 0111 1111 1111 1110 1111 110 0000 0000 0000 0000 0000 000 1111 1111 1111 1111 1111 1110 0xFFFFFE -1 1000 0000 0000 0000 0000 001 1000 0000 0000 0000 0000 000

0 0x7FFFFE + 4,194,303 0 0x7FFFFC + 4,194,302 0 0x000000 0

0 0x800002 - 4,194,303 0 0x800000 - 4,194,304

Decimal

23-bit Resolution

MCP3903

TABLE 5-5: OSR = 64 OUTPUT CODE EXAMPLES

ADC Output code (MSB First) Hexadecimal

0111 1111 1111 1111 1111 0111 1111 1111 1111 1110 0 0 0 0 0x7FFFE0 + 524, 286 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 0 0 0 0 0xFFFFF0 -1 1000 0000 0000 0000 0001 0 0 0 0 0x800010 - 524,287 1000 0000 0000 0000 0000

0 0 0 0 0x7FFFF0 + 524, 287

0 0 0 0 0x000000 0

0 0 0 0 0x800000 - 524, 288

TABLE 5-6: OSR = 32 OUTPUT CODE EXAMPLES

ADC Output code (MSB First) Hexadecimal

0111 1111 1111 1111 1 0111 1111 1111 1111 00 0 0 0 0 0 0 0x7FFF00 + 65, 534 0000 0000 0000 0000 00 0 0 0 0 0 0 0x000000 0 1111 1111 1111 1111 1 1000 0000 0000 0000 10 0 0 0 0 0 0 0x800080 - 65,535 1000 0000 0000 0000 00 0 0 0 0 0 0 0x800000 - 65, 536

0 0 0 0 0 0 0 0x7FFF80 + 65, 535

0 0 0 0 0 0 0 0xFFFF80 -1

Decimal

20-bit resolution

Decimal

17-bit resolution

5.6 Voltage Reference

5.6.1 INTERNAL VOLTAGE REFERENCE

The MCP3903 contains an internal voltage reference source specially designed to minimize drift over temperature. In order to enable the internal voltage reference, the VREFEXT bit in the configuration register must be set to 0 (default mode). This internal

supplies reference voltage to both channels. The

V

REF

typical value of this voltage reference is 2.35V ±2%. The internal reference has a very low typical temperature coefficient of ±5 ppm/°C, allowing the output codes to have minimal variation with respect to temperature since they are proportional to (1/V

The noise of the internal voltage reference is low enough not to significantly degrade the SNR of the ADC if compared to a precision external low-noise voltage reference.

The output pin for the internal voltage reference is REFIN+/OUT.

When the internal voltage reference is enabled, REFIN- pin should always be connected to AGND.

For optimal ADC accuracy, appropriate bypass capacitors should be placed between REFIN+/OUT and AGND. De-coupling at the sampling frequency, around 1 MHz, is important for any noise around this frequency will be aliased back into the conversion data.

0.1 µF ceramic and 10 µF tantalum capacitors are recommended.

REF

).

These bypass capacitors are not mandatory for correct ADC operation, but removing these capacitors may degrade accuracy of the ADC. The bypass capacitors also help for applications where the voltage reference output is connected to other circuits. In this case, additional buffering may be needed as the output drive capability of this output is low.

5.6.2 DIFFERENTIAL EXTERNAL VOLTAGE INPUTS

When the VREFEXT bit is high, the two reference pins (REFIN+/OUT, REFIN-) become a differential voltage reference input. The voltage at the REFIN+/OUT is noted V V

REF

the following equation:

+ and the voltage at the REFIN- pin is noted

REF

-. The differential voltage input value is shown in

EQUATION 5-4:

V

REF=VREF

The specified V REFIN- pin voltage (V Typically, for single-ended reference applications, the REFIN- pin should be directly connected to AGND.

range is from 2.2V to 2.6V. The

REF

+ - V

-) should be limited to ±0.3V.

REF

-

MCP3903

5.7 Power-on Reset

The MCP3903 contains an internal POR circuit that monitors analog supply voltage AV The typical threshold for a power-up event detection is

4.2V ±5%. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µF ceramic and 10 µF tantalum) should be mounted as close as possible to the AV

DD

transient immunity.

Figure 5-3 illustrates the different conditions at

power-up and a power-down event, in typical conditions. All internal DC biases are not settled until at least 50 µs after system POR. Any data ready pulses during this time after system reset should be ignored. After POR, data ready pulses are present at the pin with all the default conditions in the configuration registers.

Both AV Since AV

and DVDD power supplies are independent.

DD

is the only power supply that is monitored,

DD

it is highly recommended to power up DV power-up sequence. If AV

is powered up first, it is

DD

highly recommended to keep the RESET the whole power-up sequence.

AV

DD

5V

4.2V 4V

50 µs

t

POR

0V

DEVICE

MODE

RESET

PROPER

OPERATION

during operation.

DD

pin, providing additional

first as a

DD

pin low during

Time

RESET

5.8 RESET Effect On Delta Sigma Modulator/SINC Filter

When the RESET pin is low, both ADCs will be in Reset and output code 0x0000h. The RESET

pin performs a hard reset (DC biases still on, part ready to convert) and clears all charges contained in the sigma delta modulators. The comparator outputs are 0011 for each ADC.

The SINC filters are all reset, as well as their double output buffers. This pin is independent of the serial interface. It brings the CONFIG registers to the default state. When RESET

is low, any write with the SPI interface will be disabled and will have no effect. All output pins (SDO, DR, MDAT0/1) are high impedance, and no clock is propagated through the chip.

5.9 Phase Delay Block

The MCP3903 incorporates a phase delay generator which ensures that the six ADCs are converting the inputs with a fixed delay between them. The six ADCs are synchronously sampling but the averaging of modulator outputs is delayed so that the SINC filter outputs (thus the ADC outputs) show a fixed phase delay, as determined by the PHASE register setting. The phase register is composed of three bytes: PHASEC<7:0>, PHASEB<7:0>, PHASEA<7:0>. Each byte is a 7 bit + sign MSB first, two's complement code that represents the amount of delay between each pair of ADCs. The PHASEC byte represents the delay between Channel 4 and channel 5 (pair C). The PHASEB byte represents the delay between Channel 2 and channel 3 (pair B). The PHASEA byte represents the delay between Channel 0 and channel 1 (pair A). The reference channel is the odd channel (channel 1/ 3/5). When PHASEn<7:0> is positive, Channel 0/2/4 is lagging versus channel 1/3/5 otherwise it is leading. The amount of delay between two ADC conversions is given by the following formula:

FIGURE 5-3: Power-on Reset Operation.

EQUATION 5-5:

Delay

Phase Register Code

--------------------------------------------------= DMCLK

The timing resolution of the phase delay is 1/DMCLK or 1 µs in the default configuration with MCLK = 4 MHz.

The data ready signals are affected by the phase delay settings. Typically, the time difference between the data ready pulses of channel 0 and channel 1 is equal to the phase delay setting.

Note: A detailed explanation of the Data Ready

pins (DRn

) with phase delay is present in

Section 6.10 “Data Ready Pulses (DRn)”.

MCP3903

5.9.1 PHASE DELAY LIMITS

The Phase delay can only go from -OSR/2 to +OSR/2 - 1. This sets the fine phase resolution. The phase register is coded with 2's complement.

If larger delays between the two channels from the same pair are needed, they can be implemented externally to the chip with an MCU. A FIFO in the MCU can save incoming data from the leading channel for a number N of DRCLK clocks. In this case, DRCLK would represent the coarse timing resolution, and DMCLK the fine timing resolution. The total delay will then be equal to:

Delay = N/DRCLK + PHASE/DMCLK

The Phase Delay register can be programmed once with the OSR=256 setting and will adjust to the OSR automatically afterward without the need to change the value of the PHASE register.

• OSR=256: the delay can go from -128 to +127.

PHASEn<7> is the sign bit. PHASEn<6> is the MSB and PHASEn<0> the LSB.

• OSR=128: the delay can go from -64 to +63.

PHASEn<6> is the sign bit. PHASEn<5> is the MSB and PHASEn<0> the LSB.

• OSR=64: the delay can go from -32 to +31.

PHASEn<5> is the sign bit. PHASEn<4> is the MSB and PHASEn<0> the LSB.

• OSR=32: the delay can go from -16 to +15.

PHASEn<4> is the sign bit. PHASEn<3> is the MSB and PHASEn<0> the LSB.

TABLE 5-7: PHASE VALUES WITH

MCLK = 4 MHZ, OSR = 256

Phase Register

Value

01111111 0x7F + 127 µs 01111110 0x7E + 126 µs 00000001 0x01 + 1 µs 00000000 0x00 0 µs 11111111 0xFF - 1 µs 10000001 0x81 - 127 µs 10000000 0x80 -128 µs

Hex Delay

(CH0/2/4 relative

to CH1/3/5)

5.10 Crystal Oscillator

The MCP3903 includes a Pierce-type crystal oscillator with very high stability and ensures very low tempco and jitter for the clock generation. This oscillator can handle up to 16.384 MHz crystal frequencies, provided that proper load capacitances and quartz quality factor are used.

For keeping specified ADC accuracy, AMCLK should be kept between 1 and 5 MHz with BOOST off or 1 and

8.192 MHz with BOOST on. Larger MCLK frequencies can be used, provided the prescaler clock settings allow the AMCLK to respect these ranges.

For a proper start-up, the load capacitors of the crystal should be connected between OSC1 and DGND and between OSC2 and DGND. They should also respect the following equation:

EQUATION 5-6:

2

1

RM1.6 106×

<

Where:

f = crystal frequency in MHz

C

LOAD

R

When CLKEXT=1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock.

= load capacitance in pF including

parasitics from the PCB

= motional resistance in ohms of

M

the quartz

⎛⎞

---------------------------- -

×

⎝⎠

C

f

×

LOAD

MCP3903

6.0 SERIAL INTERFACE DESCRIPTION

6.1 OVERVIEW

The MCP3903 device is compatible with SPI modes

0,0 and 1,1. Data is clocked out of the MCP3903 on the falling edge of SCK, and data is clocked into the MCP3903 on the rising edge of SCK. In these modes,

SCK can idle either high or low. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is high, SDO is in high impedance, and transitions on SCK and SDI have no effect. Additional controls: RESET provided on separate pins for advanced communication. The MCP3903 interface has a simple command structure. The first byte transmitted is always the CONTROL byte that is 8 bits wide and is followed by data bytes that are 24 bits wide. Both ADCs are continuously converting data by default and can be reset or shutdown through a CONFIG register setting.

Since each ADC data is either 16 or 24 bits (depending on the WIDTH bits), the internal registers can be grouped together with various configurations (through the READ bits) in order to allow easy data retrieval within only one communication. For device reads, the internal address counter can be automatically incremented in order to loop through groups of data within the register map. The SDO will then output the data located at the ADDRESS (A<4:0>) defined in the control byte and then ADDRESS+1 depending on the READ<1:0> bits which select the groups of registers.

These groups are defined in Section 7.1 “ADC Chan- nel Data Output Registe rs” (Register Map). The Data

Ready pins (DRn) can be used as an interrupt for an MCU and outputs pulses when new ADC channel data is available. The RESET can reset the part to its default power-up configuration.

pin acts like a hard reset and

, DR are also

The default device address bits are 01. A read on undefined addresses will give an all zeros output on the first and all subsequent transmitted bytes. A write on an undefined address will have no effect and will not increment the address counter either.

The register map is defined in Section 7.1 “ADC

Channel Data Output Registers”.

6.3 Reading from the Device

The first data byte read is the one defined by the address given in the CONTROL byte. After this first byte is transmitted, if CS communication continues and the address of the next transmitted byte is determined by the status of the READ bits in the STATUS/COM register. Multiple looping configurations can be defined through the

READ<1:0> bits for the address increment (see 6.6

“SPI MODE 1,1 - Clock Idle High, Read/Write Examples””).

pin is maintained low, the

6.4 Writing to the Device

The first data byte written is the one defined by the address given in the control byte. The write communication automatically increments the address for subsequent bytes. The address of the next transmitted byte within the same communication (CS stays low) is the next address defined on the register map. At the end of the register map, the address loops to the beginning of the register map. Writing a non-writable register has no effect. SDO pin stays high impedance during a write communication.

6.5 SPI MODE 0,0 - Clock Idle Low, Read/Write Examples

In this SPI mode, the clock idles low. For the MCP3903, this means that there will be a rising edge before there is a falling edge.

6.2 CONTROL BYTE

The control byte of the MCP3903 contains two device address bits A<6:5>, 5 register address bits A<4:0>, and a read/write bit (R/W). The first byte transmitted to the MCP3903 is always the control byte.

A5

A6 (0)

Device

Address Bits

FIGURE 6-1: Control Byte.

(1)

A4 A3

A2

A1

Register

Address Bits

A0

R/W

Read

Write Bit

MCP3903

CS

DATA TRANSITIONS ON

THE FALLING EDGE

MCU AND MCP3901 LATCH BITS ON THE RISING EDG E

SCK

1 32

SDI

SDO

A6

A5

HI-Z

A1

A4

A0

A3

HI-Z

R/W

A2

16

222120

19

18

D15 060504

17

D23

(ADDRESS) 24 BIT DATA

Note:

FIGURE 6-2: Device Read (SPI MODE 0,0 - Clock Idles Low).

CS

DATA TRANSITIONS ON

THE FALLING EDGE

MCU AND MCP3901 LATCH

BITS ON THE RISING EDGE

SCK

SDI

HI-Z

SDO

1

R/W

A6

A5

A1

A0

A2

A4

A3

D23

222120

19

18

17

16

D15

(ADDRESS) DATA

HI-Z

FIGURE 6-3: Device Write (SPI Mode 0,0 - Clock Idles Low).

6.6 SPI MODE 1,1 - Clock Idle High, Read/Write Examples

HI-Z

D6D5D4

03

D3

D07

D7

02

01

00

D2

D1

D23 (OF ADDRESS + 1 DATA)

32

D23 OF (ADDRESS + 1) DATA

D0

In this SPI mode, the clock idles High. For the MCP3903, this means that there will be a falling edge before there is a rising edge.

CS

DATA TRANSITIONS ON

THE FALLING EDGE

MCU AND MCP3901 LATCH BITS ON THE RISING EDGE

SCK

SDI

SDO

HI-Z

1

A6

A5

A1

A0

A4

A3

HI-Z

R/W

A2

23

222120

19

18

17

D8

D16

D7

D6D5D4

D3

32

D2

D1

D0

HI-Z

(ADDRESS) DATA

FIGURE 6-4: Device Read (SPI Mode 1,1 - Clock Idles High).

MCP3903

CS

DATA TRANSITIONS ON

THE FALLING EDGE

MCU AND MCP3901 LATCH

BITS ON THE RISING E DGE

SCK

1

32

SDI

SDO

R/W

A0

A6

A5

HI-Z

A1

A4

A3

A2

23 2 22120

(ADDRESS) DATA

19

18

17

D16

HI-Z

FIGURE 6-5: Device Write (SPI Mode 1,1 - Clock Idles High).

6.7 Read Continuously Channel Data, LOOPING ON ADDRESS SETS

If the user wishes to read back any of the ADC channels continuously, or all channels continuously, the internal address counter of the MCP3903 can be set to loop on specific register sets. In this case, there is only one control byte on SDI to start the communication. The part stays within the same loop until CS

This internal address counter allows the following functionality:

• Read one ADC channel data continuously

• Read all ADC channel data continuously (all ADC

• Read continuously the entire register map

• Read continuously each separate register

• Read continuously all configuration registers

• Write all configuration registers in one

returns high.

data can be independent or linked with DRn_MODE settings)

communication (see Figure 6-6)

The STATUS/COM register contains the loop settings for the internal address counter (READ<1:0>). The internal address counter can either stay constant (READ<1:0>=00) and continuously read the same byte, or it can auto-increment and loop through the register groups defined below (READ<1:0>=01), register types (READ<1:0>=10) or the entire register map (READ<1:0>=11).

Each channel is configured independently as either a 16-bit or 24-bit data word, depending on the setting of the corresponding WIDTH bit in the CONFIG register.

For continuous reading, in the case of WIDTH=0 (16-bit), the lower byte of the ADC data is not accessed and the part jumps automatically to the following address (the user does not have to clock out the lower byte since it becomes undefined for WIDTH=0).

The following figure represents a typical continuous read communication with the default settings (DRMODE<1:0>=00, READ<1:0>=10) for both WIDTH settings. This configuration is typically used for power metering applications.

D5D4D3

D6

D7

D08

D2

D1

D0

HI-Z

CH5

CH55

5CH5

FIGURE 6-6: Typical Continuous Read Communication.

MCP3903

6.7.1 CONTINUOUS READ

All ADCs are powered up with their default configurations, and begin to output data ready pulses immediately (RESET<5:0> and SHUTDOWN<5:0> bits are off by default). The default output codes for both ADCs are all zeros.The default modulator output for both ADCs is 0011 (corresponding to a theoretical zero voltage at the inputs). The default phase is zero between the two channels. It is recommended to enter into ADC reset mode for both ADCs just after power-up because the desired MCP3903 register configuration may not be the default one and in this case, the ADC would output undesired data. Within the ADC reset mode (RESET<5:0>=111111) , t h e u ser can confi g u r e the whole part with a single communication. The write commands automatically increment the address so the user can start writing the PHASE register and finish with the CONFIG register in only one communication (see Figure 6-6). The RESET<5:0> bits are in the CONFIG register to allow it to exit soft reset mode and have the whole part configured and ready to run in only one command.

TABLE 6-1: REGISTER GROUPS

GROUP ADDRESSES

Pair A, CHANNEL 0/1 0x00 - 0x01

Pair B, CHANNEL 2/3 0x02 - 0x03

Pair C, CHANNEL 4/5 0x04 - 0x05

MOD, PHASE, GAIN 0x06 - 0x08

STATUS, CONFIG 0x09 - 0x0A

The following internal registers are defined as types:

TABLE 6-2: REGISTER TYPES

TYPE ADDRESSES

ADC DATA 0x00 - 0x05

CONTROL 0x06 - 0x0A

After these temporary resets, the ADCs go back to normal operation with no need for an additional command. These are also the settings where the DR position is affected. The phase register can be used to soft reset the ADC without using the RESET bits in the configuration register.

6.9 Line Cycle Sampling Options

Since the AMCLK range can go up to 5 MHz, the MCP3903 is able to accommodate 256 output samples per line cycles with line frequencies up to 76.2Hz at OSR=64.

.

TABLE 6-1: MCLK FREQUENCIES FOR

LINE SAMPLING

OUTPUT

SAMPLES

/ LINE

CYCLE

64 2.8 ksps 737.28 kHz 4.2 ksps 1.075 MHz

128 5.76 ksps 1.475 MHz 8.4 ksps 2.15 MHz

256 11.5 ksps 2.949 MHz 16.7 ksps 4.3 MHz

Figure 6-7 illustrates operating the part in this manner (timings not to scale, functional description only).

All channels are continuously converting during normal operation of the device except when it is in Sleep Mode by using the RESET bit, or if RESET following figure represents the clocking scheme and how the CONFIG PRESCALE<1:0> bits and OSR<1:0> bits registers is used to modify the clock prescale and oversampling ratio.

For example, if a data ready pulse occurs while ADC data (a) is being transmitted on SPI, this data will not be corrupt in any way. After CS another transmission, the next data (b) would be present in the output buffer ready for transmission.

F

LINE

OSR = 64

F

D

= 45 HZ

MCLK

F

= 65 HZ

LINE

OSR = 64

F

MCLK

D

is low. The

is toggled low to begin

6.8 Situations that Reset ADC Data

Immediately after the following actions, the ADCs are reset and automatically restarted in order to provide proper operations:

1: Change in phase register 2: Change in the OSR setting 3: Change in the PRESCALER setting 4: Overwrite of identical PHASE register

value

5: Change in EXTCLK bit in the CONFIG

register modifying internal oscillator state.

MCP3903

OSC1/MCLKI

DRn

CS

1 / f

LINE

DATA

• DRn_MODE<1:0> = 1 1: Both Data Ready pulses

from ADC Channel 0/2/4 and ADC Channel 1/3/5 are output on DR pin.

• DRn_MODE<1:0> = 10: Data Ready pulses from

ADC Channel 1/3/5 are output on the corresponding DRn pin. Data Ready pulses from ADC Channel 0/2/4 are not present on the pin.

• DRn_MODE<1:0> = 01: Data Ready pulses from

ADC Channel 0/2/4 are output on the corresponding DRn pin. Data Ready pulses from ADC Channel 1/3/5 are not present on the pin.

• DRn_MODE<1:0> = 00: (Recommended, and

Default Mode). Data Ready pulses from the lagging ADC between the two are output on DR pin. The lagging ADC depends on the phase register and on the OSR. In this mode the two ADCs are linked together so their data is latched together when the lagging ADC output is ready.

SCK

SPI

SDI

SDO

FIGURE 6-7: Standard Device Operation.

6.10 Data Ready Pulses (DRn)

To ensure that all channel ADC data are present at the same time for SPI read, regardless of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the ‘read start’ triggers.

The first set of latches holds each output when data is ready and latches both outputs together when DRMODE<1:0>=00. When this mode is on, both ADCs work together and produce one set of available data after each data ready pulse (that corresponds to the lagging ADC data ready). The second set of latches ensures that when reading starts on an ADC output, the corresponding data is latched so that no data corruption can occur.

If an ADC read has started, in order to read the following ADC output, the current reading needs to be completed (all bits must be read from the ADC output data registers).

6.10.2 DR PULSES WITH SHUTDOWN OR RESET CONDITIONS

There will be no data ready pulses if DRn_MODE<1:0>=00 when either one or both of the ADCs of the corresponding pair are in reset or shutdown. In Mode 00, a data ready pulse only happens when both ADCs of the corresponding pair are ready. Any data ready pulse will correspond to one data on both ADCs. The two ADCs are linked together and act as if there was only one channel with the combined data of both ADCs. This mode is very practical when both ADC channel data retrieval and processing need to be synchronized, as in power metering applications.

Figure 6-8 represents the behavior of the data ready

pin with the different DRn_MODE and DR_LTY configurations, while shutdown or resets are applied.

Note: If DRn_MODE<1:0>=11, the user will still

be able to retrieve the data ready pulse for the ADC not in shutdown or reset, i.e. only 1 ADC channel needs to be awake.

6.10.1 DATA READY PINS (DRn) CONTROL USING DRn_MODE BITS

There are four modes that control the data ready pulses, and these modes are set with the DRn_MODE<1:0> bits in the STATUS/COM register. For power metering applications, DRn_MODE<1:0>=00 is recommended (default mode).

The position of data ready pulses vary with respect to this mode, to the OSR and to the PHASE settings:

MCP3903

PHASE < 0 PHASE = 0 PHASE > 0

DRMODE=00 : Select the lagging Data Ready

DRMODE=01 : Select the Data Ready on channel 0

DRMODE=10 : Select the Data Ready on channel 1

DRMODE=11 : Select both Data ready

D1 D3 D5 D6 D7 D8 D11 D13D0 D2 D4 D10 D12 D14 D15

Data Ready pulse that appears only when DR_LTY=0

D9 D20

DRMODE=10; DR

DRMODE=11; DR

D0 D1 D2 D3 D4 D5 D6 D7 D8

DRMODE=00; DR

DRMODE=01; DR

D0 D1 D2 D3 D4 D5

D0 D1 D2 D3 D4 D5 D12D11 D13 D15 D16 D17D8 D9 D10

DRMODE=10; DR

DRMODE=11; DR

D0 D1 D2 D3 D4 D5 D6 D 7 D8 D9 D11D10 D12 D13 D14 D15

D0 D1 D2 D3 D4 D5 D6 D 7 D8 D9 D10 D11 D12 D13 D1 4 D15 D16 D17 D18

D0 D1 D2 D4 D5D3 D7 D8 D 9 D10 D11 D12 D13D6 D15 D16

DRMODE=00; DR

DRMODE=01; DR

D0 D1 D2 D6 D10 D11 D12

DRMODE=10; DR

DRMODE=11; DR

D0 D1 D2 D3 D4 D5 D6 D7 D8

D1 D3 D5 D6 D7 D8 D10 D12D0 D2 D4 D9 D11 D13 D14

DRMODE=00; DR

DRMODE=01; DR

D0 D1 D2 D3 D4 D5

D0 D1 D2

D3 D4 D5

SHUTDOWN<1>

SHUTDOWN<0>

RESET<1> o r

RESET<0> o r

RESET

DRCLK period DRCLK period

D6

D6 D7

D9 D13

D17 D18 D21 D24D16 D19 D22 D25 D2 6

D10 D11 D12

D23

D28 D2 9 D 31 D33D27 D30 D32 D34

D14 D15 D16

D7

D8D7

D9D4 D5D3

D10D8 D9

D11 D12 D13 D14

D14

D16 D17 D18 D19 D21 D24D15 D20 D22 D25 D26

D23

D28 D2 9 D 31 D33D27 D30 D32 D34

D6 D12

D9 D13

D10 D11 D12

D14

D15 D16 D17

D6

D7 D8 D9 D10 D11

D10D7 D8 D9

D13 D14 D15 D16

D11

D12 D13 D14

DRCLK period1 DMCLK perio d

Internal reset synchronisation

(1 DMCLK period)

3*DRCLK period3*DRCLK period

D19

D16

D13

FIGURE 6-8: Data Ready Behavior.

MCP3903

6.11 DATA READY PULSE WITH

PHASE DELAY

To ensure that both channel ADC data from the same pair are present at the same time for SPI read, regardless of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the reading start triggers. The first latch is set on whichever channel is the lagging channel (relative to the other channel, in a single channel pair). The second latch is set when an ADC output read command is issued, ensuring synchronized data ready pulses.

CHn ADC

FIGURE 6-9: Internal Latches Synchronizing Data Ready Pulses with Phase Delay Present (Single Channel Pair Shown).

LATCH

SPI Serial Interface

LATCH

Synchronized

data ready pulses

6.11.1 DATA READY LINK

When DRLINK=0, the three pairs of ADCs are independent from each other. The data readys and the latches for the output data only depend on both ADCs in the pair. When another ADC (not in the pair) is put in SHUTDOWN or RESET, it has no effect.

When DRLINK=1, all ADCs are linked together. The DRn_MODE<1:0> are all set internally to 00. All DRn_MODE<1:0> bits are not taken into account.

All six channel ADC data are latched synchronously with the most lagging ADC channel of the six.

All three DRA giving the same output that is synchronized with the most lagging ADC of the six channels. Only one pin can be connected to the MCU in this mode, which saves two connection ports on the MCU.

In this mode, if any channel is in SHUTDOWN or RESET mode, no data ready is present on any of the

DRB/DRC pins. The part acts as if there was only

DRA/ one ADC channel with 6x24 bits.

Depending on the read modes, the ADC data can be retrieved by pair (Read by GROUP) or all together (Read by TYPE). Any time a new read command is performed, the ADC outputs are re-latched. In order to avoid loss of data or bad synchronization, the read mode by TYPES is recommended (READ<1:0>=10) so that all data can be latched once at the beginning of the read. In the read mode by GROUP (READ<1:0>=01) mode, the data will be relatched every time the part accesses to each group or pair of ADCs.

, DRB and DRC data ready pins are

MCP3903

7.0 INTERNAL REGISTERS

The addresses associated with the internal registers are listed below. All registers are 24 bits long and can

be addressed separately. A detailed description of the

registers follows.

TABLE 7-1: INTERNAL REGISTER SUMMARY

Address Name Bits R/W Description

0x00 CHANNEL 0 24 R Channel 0 ADC Data <23:0>, MSB first, left justified

0x01 CHANNEL 1 24 R Channel 1 ADC Data <23:0>, MSB first, left justified

0x02 CHANNEL 2 24 R Channel 2 ADC Data <23:0>, MSB first, left justified

0x03 CHANNEL 3 24 R Channel 3 ADC Data <23:0>, MSB first, left justified

0x04 CHANNEL 4 24 R Channel 4 ADC Data <23:0>, MSB first, left justified

0x05 CHANNEL 5 24 R Channel 5 ADC Data <23:0>, MSB first, left justified

0x06 MOD 24 R/W Delta Sigma Modulators Output Value

0x07 PHASE 24 R/W Phase Delay Configuration Register

0x08 GAIN 24 R/W Gain Configuration Register

0x09 STATUS/COM 24 R/W Status/Communication Register

0x0A CONFIG 24 R/W Configuration Register

.

The following table shows how the internal address counter will loop on specific register groups and types.

TABLE 7-2: CONTINUOUS READ

OPTIONS, LOOPING ON INTERNAL ADDRESSES

READ<1:0>

Function Address

CHANNEL 0 0x00

CHANNEL 1 0x01

CHANNEL 2 0x02

CHANNEL 3 0x03

CHANNEL 4 0x04

CHANNEL 5 0x05

MOD 0x06

PHASE 0x07

GAIN 0x08

STATUS/

COM

CONFIG 0x0A

0x09

= “01” = “10” =“11”

GROUP

TYPE

GROUP

TYPE

LOOP ENTIRE REGISTER MAP

GROUP

7.1 Channel Output Registers

TABLE 7-3: ADC OUTPUT REGISTERS

Name Bits Address Cof

CHANNEL 0 24

CHANNEL 1 24

CHANNEL 2 24

CHANNEL 3 24

CHANNEL 4 24

CHANNEL 5 24

The ADC Channel data output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with READ<1:0> bits). These registers are latched when an ADC read communication occurs. When a data ready event occurs during a read communication, the most current ADC data is also latched to avoid data corruption issues. The three bytes of each channel are updated synchronously at a DRCLK rate. The three bytes can be accessed separately if needed, but are refreshed synchronously. The coding is 23-bit + sign two’s complement (see Section 5.5).

0x00

0x01

0x02

0x03

0x04

0x05

R

MCP3903

REGISTER 7-1: CHANNEL REGISTER

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

D23 (MSB) D22 D21 D20 D19 D18 D17 D16

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

D15 D14 D13 D12 D11 D10 D9 D8

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

D7 D6 D5 D4 D3 D2 D1 D0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23:0 24-bit ADC output data of the corresponding channel

MCP3903

7.2 Mod Register

TABLE 7-4: MODULATOR OUTPUT

REGISTER

Name Bits Address Cof

MOD 24

0x06

R/W

The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input of 0V on each ADC. Each bit in this register corresponds to one comparator output on one of the channels.

This register should be used as a read-only register.

(Note 1). This register is updated at the refresh rate of

DMCLK (typically 1 MHz with MCLK = 4 MHz). The default state for this register is

001100110011001100110011.

REGISTER 7-2: MOD REGISTER

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1

COMP3_CH5 COMP2_CH5 COMP1_CH5 COMP0_CH5 COMP3_CH4 COMP2_CH4 COMP1_CH4 COMP0_CH4

bit 23 bit 16

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1

COMP3_CH3 COMP2_CH3 COMP1_CH3 COMP0_CH3 COMP3_CH2 COMP2_CH2 COMP1_CH2 COMP0_CH2

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1

COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH1 COMP2_CH0 COMP1_CH0 COMP0_CH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23:20 COMPn_CH5: Comparator Outputs from ADC Channel 5 bit 19:16 COMPn_CH4: Comparator Outputs from ADC Channel 4 bit 15:12 COMPn_CH3: Comparator Outputs from ADC Channel 3 bit 11:8 COMPn_CH2: Comparator Outputs from ADC Channel 2 bit 7:4 COMPn_CH1: Comparator Outputs from ADC Channel 1 bit 3:0 COMPn_CH0: Comparator Outputs from ADC Channel 0

MCP3903

7.3 Phase Register

TABLE 7-5: PHASE REGISTER

Name Bits Address Cof

PHASE 24

The phase register is composed of three bytes: PHASEC<7:0>, PHASEB<7:0>, PHASEA<7:0>. Each byte is a 7 bit + sign MSB first, two's complement code that represents the amount of delay between each pair of ADCs. The PHASEC byte represents the delay between Channel 4 and Channel 5 (pair C). The PHASEB byte represents the delay between Channel 2 and Channel 3 (pair B). The PHASEA byte represents the delay between Channel 0 and Channel 1 (pair A).

0x07

R/W

The reference channel is the odd channel (Channel 1/ 3/5). When PHASEn<7:0> is positive, Channel 0/2/4 is lagging versus channel 1/3/5 otherwise it is leading.

The delay is calculated by the following formula:

Delay = PHASE Register Code / DMCLK.

REGISTER 7-3: PHASE REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHASEC7 PHASEC6 PHASEC5 PHASEC4 PHASEC3 PHASEC2 PHASEC1 PHASEC0

bit 23 bit 16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHASEB7 PHASEB6 PHASEB5 PHASEB4 PHASEB3 PHASEB2 PHASEB1 PHASEB0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHASEA7 PHASEA6 PHASEA5 PHASEA4 PHASEA3 PHASEA2 PHASEA1 PHASEA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23:16 PHASECn: CH4 relative to CH5 phase delay bit 15:8 PHASEBn: CH2 relative to CH3 phase delay bit 7:0 PHASEAn: CH0 relative to CH1 phase delay

MCP3903

7.4 Gain Configuration Register

TABLE 7-6: GAIN REGISTER

Name Bits Address Cof

GAIN 24

This register contains the gain register

0x08

REGISTER 7-4: GAIN REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PGA2_CH5 PGA1_CH5 PGA0_CH5 BOOST_ CH5 BOOST_ CH4 PGA2_CH4 PGA1_CH4 PGA0_CH4

bit 23 bit 16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PGA2_CH3 PGA1_CH3 PGA0_CH3 BOOST_ CH3 BOOST_ CH2 PGA2_CH2 PGA1_CH2 PGA0_CH2

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PGA2_CH1 PGA1_CH1 PGA0_CH1 BOOST_ CH1 BOOST_ CH0 PGA2_CH0 PGA1_CH0 PGA0_CH0

bit 7 bit 0

R/W

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit PGA_CHn: PGA Setting for Channel n

111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1

bit BOOST_CHn Current Scaling for high speed operation for channel n

1 = Channel has current x 2 0 = Channel has normal current

MCP3903

7.5 STATUS/COM Register - Status

and Communication Register

TABLE 7-7: STATUS/COM Register

Name Bits Address Cof

STATUS/COM 24

0x09

7.5.1 DATA READY LATENCY - DR_LTY

This bit determines if the data ready pulses correspond to settled data or unsettled data from each SINC Unsettled data will provide data ready pulses every DRCLK period. Settled data will wait for 3 DRCLK periods before giving data ready pulses and will then give data ready pulses every DRCLK period.

7.5.2 DATA READY HIGH Z MODE DR_HIZ

Using this bit, the user can connect multiple chips with the same data ready pin with a pull up resistor (DR_HIZ nent (DR_HIZ

=0) or a single chip with no external compo-

=1)

7.5.3 DATA READY MODE - DRN_MODE

These bits control which ADC data ready is present on the data ready pin. When the bits are set to 00, the output of the two ADCs are latched synchronously at the moment of the data ready event. This prevents bad synchronization between the two ADCs. The output is also latched at the beginning of a reading, in order not to be updated during a read, and not to give erroneous data.

REGISTER 7-5: STATUS/COM REGISTER

R/W

3

filter.

If one of the channels is in reset or shutdown, only one of the data ready pulses is present and the situation is similar to DRn_MODE<1:0> = 01 or 10. In the 01,10 and 11 modes, the data is latched at the beginning of a reading, in order to prevent the case of erroneous data when a data ready pulse happens when reading.

7.5.4 DATA READY STATUS FLAG DRSTATUS_CHN

These bits indicate the data ready status of each channel. These flags are set to logic high after being the STATUS/COM register has been read. These bits are cleared when a data ready event has happened on its respective ADC. Writing these bits has no effect.

Note: These bits are useful if multiple devices

share the same DRn (DR_HIZ device the data ready event occured from. In case the DRn_MODE=00 (Linked ADCs), these data ready status bits will be updated synchronously upon the same event (lagging ADC is ready). These bits are also useful in systems where the DRn pins are not used to save MCU I/O.

=0) in order to understand which

output pin

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

READ1 READ0 WMODE WIDTH_CH5 WIDTH_CH4 WIDTH_CH3 WIDTH_CH2 WIDTH_CH1

bit 23 bit 16

R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WIDTH_CH0 DR_LTY DR_HIZ

bit 15 bit 8

R/W-0 R/W-0 R-1 R-1 R-1 R-1 R-1 R-1

DRA_MODE1 DRA_MODE0 DRSTATUS_CH5 DRSTATUS_CH4 DRSTATUS_CH3 DRSTATUS_CH2 DRSTATUS_CH1 DRSTATUS_CH0

bit 7 bit 0

bit 23:22 READ[1:0]: Address Loop Setting

11 = Address counter incremented, cycle through entire register map 10 = Address counter loops on register TYPES (DEFAULT) 01 = Address counter loops on register GROUPS 00 = Address not incremented, continually read single register

bit 21 WMODE: Write Mode Bit (internal use only)

1 = Static addressing Write Mode 0 = Incremental addressing Write Mode (DEFAULT)

DR_LINK DRC_MODE1 DRC_MODE0 DRB_MODE1 DRB_MODE0

REGISTER 7-5: STATUS/COM REGISTER (CONTINUED)

bit 20:15 WIDTH_CHn ADC Channels output data word width control

1 = 24-bit mode for the corresponding channel 0 = 16-bit mode for the corresponding channel (default)

bit 14 DR_LTY: Data Ready Latency Control for DRA

1 = True “No Latency” Conversion, 0 = Unsettled Data is available after every DRCLK period

bit 13 DR_HIZ

1 = The Default state is a logic high when data is NOT ready 0 = The Default state is high impedance when data is NOT ready (DEFAULT)

bit 12 DR_LINK Data Ready Link Control

1 = Data Ready Link turned ON, all channels linked and data ready pulses from the most lagging ADC

0 = Data Ready Link tunred OFF (DEFAULT)

bit 11:10 DRC_MODE[1:0]

11 = Both Data Ready pulses from CH4 and CH5 are output on DRC 10 = Data Ready pulses from CH5 are output on DRC

01 = Data Ready pulses from CH4 are output on DRC pin. Data Ready pulses from CH5 are not present

00 = Data Ready pulses from the lagging ADC channel between the two are output on DRC

bit 9:8 DRB_MODE[1:0]

11 = Both Data Ready pulses from CH2 and CH3 are output on DRB 10 = Data Ready pulses from CH3 are output on DRB

01 = Data Ready pulses from CH2 are output on DRB pin. Data Ready pulses from CH3 are not present

00 = Data Ready pulses from the lagging ADC channel between the two are output on DRB

bit 7:6 DRA_MODE[1:0]

11 = Both Data Ready pulses from CH0 and CH1 are output on DRA 10 = Data Ready pulses from CH1 are output on DRA

01 = Data Ready pulses from CH0 are output on DRA pin. Data Ready pulses from CH1 are not present

00 = Data Ready pulses from the lagging ADC channel between the two are output on DRA

bit 5:0 DRSTATUS_CHn: Data Ready Status

1 = Data Not Ready (default) 0 = Data Ready

: Data Ready Pin Inactive State Control for DRA, DRB, and DRC pins

are present on each DRn

ent on the pin.

on the pin.

lagging ADC channel depends on the phase register and on the OSR. (DEFAULT)

on the pin.

lagging ADC channel depends on the phase register and on the OSR. (DEFAULT)

on the pin.

lagging ADC channel depends on the phase register and on the OSR. (DEFAULT)

data ready pulses after 3 DRCLK periods (DEFAULT)

, DRB, and DRC pins

pin. Data Ready pulses R from CH4 are not pres-

pin. Data Ready pulses from CH2 are not present

pin. Data Ready pulses from CH0 are not present

MCP3903

pin.

pin. The

pin.

pin. The

pin.

pin. The

MCP3903

7.6 Config Register - Configuration Register

TABLE 7-8: CONFIG Register

Name Bits Address Cof

CONFIG 24

REGISTER 7-6: CONFIG REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RESET_CH5 RESET_CH4 RESET_CH3 RESET_CH2 RESET_CH1 RESET_CH0 SHUTDOWN_CH5 SHUTDOWN_CH4

bit 23 bit 16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1

SHUTDOWN_

CH3

bit 15 bit 8

R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

DITHER_CH1 DITHER_CH0 OSR1 OSR0 PRESCALE1 PRESCALE0 EXTVREF EXTCLK

bit 7 bit 0

bit 23:18 RESET_CHn: Reset mode setting for ADCs

bit 17:12 SHUTDOWN_CHn: Shutdown mode setting for ADCs

bit 11:6 DITHER_CHn: Control for dithering circuit for idle tones cancellation

bit 5:4 OSR[1:0] Oversampling Ratio for Delta Sigma A/D Conversion (ALL CHANNELS, f

bit 3:2 PRESCALE[1:0] Internal Master Clock (AMCLK) Prescaler Value

bit 1 EXTVREF Internal Voltage Reference Shutdown Control

bit 0 EXTCLK Clock Mode

SHUTDOWN_

1 = Reset mode for the corresponding ADC channel ON 0 = Reset mode for the corresponding ADC chnnel OFF (default)

1 = Shutdown mode for the corresponding ADC channel ON 0 = Shutdown mode for the corresponding ADC channel OFF(default)

1 = Dithering circuit for the corresponding ADC channel ON (default) 0 = Dithering circuit for the corresponding ADC channel OFF

11 = 256 10 = 128 01 = 64 (default) 00 = 32

11 = AMCLK = MCLK/ 8 10 = AMCLK = MCLK/ 4 01 = AMCLK = MCLK/ 2 00 = AMCLK = MCLK (DEFAULT)

1 = Internal Voltage Reference Disabled 0 = Internal Voltage Reference Enabled (default)

1 = CLOCK Mode (Internal Oscillator Disabled - Lower Power) 0 = XT Mode - A crystal must be placed between OSC1/OSC2 (default)

CH2

0x0A

SHUTDOWN_CH1 SHUTDOWN_CH0 DITHER_CH5 DITHER_CH4 DITHER_CH3 DITHER_CH2

R/W

/ f

)

d

S

8.0 PACKAGING INFORMATION

8.1 Package Marking Information

28-Lead SSOP (5.30 mm) Example

MCP3903

E/SS

1124256

3

e

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code

3

e

Pb-free JEDEC designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

MCP3903

I/SS

e

1124 256

3

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available characters for customer-specific information.

MCP3903

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L

MCP3903

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP3903

APPENDIX A: REVISION HISTORY

Revision B (July 2011)

• Added Section 2.0, Typical Performance

Curves, with characterization graphs.

Revision A (June 201 1)

• Original data sheet for the MCP3903 device.

MCP3903

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X

Device

Device: MCP3903: Six Channel ΔΣ A/D Converter

* Default option. Contact Microchip factory for other address options

Tape and Reel: T = Tape and Reel

Temperature Range: I = -40°C to +85°C

E = -40°C to +125°C

Package: SS = Small Shrink Output Package (SSOP-28)

X

Tape and

Reel

Temperature

Range

/XX

Package

Examples:

a) MCP3903T-E/SS: Tape and Reel,

b) MCP3903T-I/SS: Tape and Reel,

MCP3903

Six Channel ΔΣ A/D Converter,

SSOP-28 package

Six Channel ΔΣ A/D Converter,

SSOP-28 package

MCP3903

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

logo, rfPIC and UNI/O are registered trademarks of

PIC Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-402-6

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

Worldwide Sales and Service

AMERICAS

Corporate Office

2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support:

http://www.microchip.com/ support

Web Address:

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Tel: 44-118-921-5869 Fax: 44-118-921-5820

05/02/11

Datasheet MCP3903 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 RELIABILITY TARGETS

1.2 SERIAL INTERFACE CHARACTERISTICS

FIGURE 1-1: Serial Output Timing Diagram.

FIGURE 1-2: Serial Input Timing Diagram.

FIGURE 1-3: Data Ready Pulse Timing Diagram.

FIGURE 1-4: Specific Timing Diagrams.

FIGURE 1-5: MCP3903 Clock Detail.

2.0 TYPI CAL PERFORMANCE CURVES

FIGURE 2-1: Spectral Response.

FIGURE 2-4: Spectral Response.

FIGURE 2-2: Spectral Response.

FIGURE 2-3: Spectral Response.

FIGURE 2-5: Spectral Response.

FIGURE 2-6: Spectral Response.

FIGURE 2-7: Spectral Response.

FIGURE 2-8: Spurious Free Dynamic Range vs Oversampling Ratio.

FIGURE 2-10: Signal-to-Noise and Distortion vs. Gain (Dithering OFF).

FIGURE 2-11: Signal-to-Noise and Distortion vs. Gain (Dithering ON).

FIGURE 2-9: Signal-to-Noise and Distortion vs. Oversampling Ratio.

FIGURE 2-12: Total Harmonic Distortion vs. Oversampling Ratio.

FIGURE 2-13: Total Harmonic Distortion vs. Input Signal Frequency.

FIGURE 2-14: Total Harmonic Distortion vs. Temperature.

FIGURE 2-16: Signal-to-Noise and Distortion vs. Temperature.

FIGURE 2-17: Signal-to-Noise and Distortion vs. Input Signal Amplitude.

FIGURE 2-15: Signal-to-Noise and Distortion vs. Input Signal Frequency.

FIGURE 2-18: Signal-to-Noise and Distortion vs. Master Clock.

FIGURE 2-19: Offset Error vs. Temperature (Channel 0).

FIGURE 2-20: Channel-to-Channel Offset Match vs. Temperature.

FIGURE 2-22: Internal Voltage Reference vs. Temperature.

FIGURE 2-23: Internal Voltage Reference vs. Supply Voltage.

FIGURE 2-21: Gain Error vs. Temperature.

FIGURE 2-24: Noise Histogram.

FIGURE 2-25: Integral Non-Linearity (Dithering OFF).

FIGURE 2-26: Integral Non-Linearity (Dithering ON).

FIGURE 2-27: Operating Current vs. Master Clock (MCLK).

3.0 PIN DESCRIPTION

TABLE 3-1: PIN FUNCTION TABLE

3.1 RESET

3.4 ADC Differential Analog Inputs(CHn+/CHn-)

3.5 Analog Ground (AGND)

3.6 Non-Inverting Reference Input, Internal Reference Output (REFIN+/OUT)

3.7 Inverting Reference Input (REFIN-)

3.8 Digital Ground Connection (DGND)

3.9 DRn (Data Ready Pins)

3.10 Oscillator And Master Clock Input Pins (OSC1/CLKI, OSC2)

3.11 CS (Chip Select)

3.12 SCK (Serial Data Clock)

3.13 SDO (Serial Data Output)

3.14 SDI (Serial Data Input)

4.0 TERMINOLOGY AND FORMULAS

4.1 MCLK - Master Clock

4.2 AMCLK - Analog Master Clock

4.3 DMCLK - Digital Master Clock

4.4 DRCLK - Data Rate Clock

TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR, AND PRESCALE

4.5 OSR - Oversampling Ratio

4.6 Offset Error

4.7 Gain Error

4.8 Integral Non-Linearity Error

4.9 Signal-To-Noise Ratio (SNR)

4.10 Signal-To-Noi se Ratio And Distortion (SINAD)

4.1 1 Tot al Harmonic Distortion (THD)

4.12 Spurious-Free Dynamic Range (SFDR)

4.13 MCP3903 Delta-Sigma Architecture

4.14 Idle Tones

4.15 Dithering

4.16 Crosstalk

4.18 CMRR

4.17 PSRR

4.19 ADC Reset Mode

4.20 Hard Reset Mode (RESET = 0)

4.21 ADC Shutdown Mode

4.22 Full Shutdown Mode

5.0 DEVICE OVERVIEW

5.1 Analog Inputs (CHn+/-)

5.3 Delta-Sigma Modulator