Datasheet MCP3421 Datasheet

MCP3421

1 2

VIN+

SCL

SDA

MCP3421

SOT-23-6

VIN+

VIN-

SCL

SDA

Voltage Reference

Clock

(2.048V)

C Interface

Gain = 1, 2, 4, or 8

REF

ΔΣ ADC

Converter

PGA

Oscillator

18-Bit Analog-to-Digital Converter

with I2C Interface and On-Board Reference

Features

• 18-bit ΔΣ ADC in a SOT-23-6 package

• Differential Input Operation

• Self Calibration of Internal Offset and Gain Per Each Conversion

• On-Board Voltage Reference:

- Accuracy: 2.048V ± 0.05%

- Drift: 15 ppm/°C

• On-Board Programmable Gain Amplifier (PGA):

- Gains of 1,2, 4 or 8

• On-Board Oscillator

• INL: 10 ppm of FSR (FSR = 4. 09 6 V /PG A )

• Programmable Data Rate Options:

- 3.75 SPS (18 bits)

- 15 SPS (16 bits)

- 60 SPS (14 bits)

- 240 SPS (12 bits)

• One-Shot or Continuous Conversion Options

• Low Current Consumption:

- 145 µA typical

= 3V, Continuous Conversion)

- 39 µA typical

= 3V, One-Shot Conversion with 1 SPS)

• Supports I2C Serial Interface:

- Standard, Fast and High Speed Modes

• Single Supply Operation: 2.7V to 5.5V

• Extended Temperature Range: -40°C to +125°C

Description

The MCP3421 is a single channel low-noise, high accuracy ΔΣ A/D converter with differential inputs and up to 18 bits of resolution in a small SOT-23-6 package. The on-board precision 2.048V reference voltage enables an input range of ±2.048V differentially (Δ voltage = 4.096V). The device uses a two-wire I compatible serial interface and operates from a single

2.7V to 5.5V power supply. The MCP3421 device performs conversion at rates of

3.75, 15, 60, or 240 samples per second (SPS) depending on the user controllable configuration bit settings using the two-wire I device has an on-board programmable gain amplifier (PGA). The user can select the PGA gain of x1, x2, x4, or x8 before the analog-to-digital conversion takes place. This allows the MCP3421 device to convert a smaller input signal with high resolution. The device has two conversion modes: (a) Continuous mode and (b) One-Shot mode. In One-Shot mode, the device enters a low current standby mode automatically after one conversion. This reduces current consumption greatly during idle periods.

The MCP3421 device can be used for various high accuracy analog-to-digital data conversion applications where design simplicity, low power, and small footprint are major considerations.

C serial interface. This

Block Diagram

Typical Applications

• Portable Instrumentation

• Weigh Scales and Fuel Gauges

• Temperature Sensing with RTD, Thermistor, and Thermocouple

• Bridge Sensing for Pressure, Strain, and Force.

Package Types

MCP3421

NOTES:

MCP3421

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Absolute Maximum Ratings†

VDD...................................................................................7.0V

All inputs and outputs w.r.t V

Differential Input Voltage ...................................... |V

Output Short Circuit Current ................................Continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±10 mA

Storage Temperature ....................................-65°C to +150°C

Ambient Temp. with power applied ...............-55°C to +125°C

ESD protection on all pins ................ ≥ 6kVHBM, ≥ 400V MM

Maximum Junction Temperature (T

............... –0.3V to VDD+0.3V

)..........................+150°C

- VSS|

†Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability

1.2 Electrical Specifications

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,

+ = VIN- = V

Parameters Sym Min Typ Max Units Conditions

Analog Inputs

Differential Input Range — ±2.048/PGA — V V Common-Mode Voltage Range

(absolute) (Note 1) Differential Input Impedance

(Note 2)

Common Mode input Impedance

System Performance

Resolution and No Missing Codes (Note 8)

Data Rate (Note 3) DR 176 240 328 SPS S1,S0 = ‘00’, (12 bits mode)

Output Noise — 1.5 — µV

Integral Nonlinearity (Note 4) INL — 10 35

Internal Reference Voltage V

Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

2: This input impedance is due to 3.2 pF internal input sampling capacitor. 3: The total conversion speed includes auto-calibration of offset and gain. 4: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 5: Includes all errors from on-board PGA and V 6: Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA. 7: This parameter is ensured by characterization and not 100% tested. 8: This parameter is ensured by design and not 100% tested.

/2. All ppm units use 2*V

REF

IND

INC

REF

This parameter is ensured by characterization and not 100% tested.

as full scale range.

REF

-0.3 — VDD+0.3 V

(f) — 2.25/PGA — MΩ During normal mode operation

(f) — 25 — MΩ PGA = 1, 2, 4, 8

12 — — Bits DR = 240 SPS 14 — — Bits DR = 60 SPS 16 — — Bits DR = 15 SPS 18 — — Bits DR = 3.75 SPS

44 60 82 SPS S1,S0 = ‘01’, (14 bits mode) 11 15 20.5 SPS S1,S0 = ‘10’, (16 bits mode)

2.75 3.75 5.1 SPS S1,S0 = ‘11’, (18 bits mode)

— 2.048 — V

REF

RMSTA

ppm of

FSR

= VIN+ - VIN-

= +25°C, DR = 3.75 SPS,

PGA = 1, V DR = 3.75 SPS

(Note 6)

= 0

MCP3421

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,

+ = VIN- = V

Parameters Sym Min Typ Max Units Conditions

Gain Error (Note 5) — 0.05 0.35 % PGA = 1, DR = 3.75 SPS PGA Gain Error Match (Note 5) — 0.1 — % Between any 2 PGA gains Gain Error Drift (Note 5) — 15 — ppm/°C PGA=1, DR=3.75 SPS Offset Error V

Offset Drift vs. Temperature — 50 — nV/°C V Common-Mode Rejection — 105 — dB at DC and PGA =1,

Gain vs. V

Power Supply Rejection at DC — 100 — dB T

Power Requirements

Voltage Range V Supply Current during

Conversion Supply Current during Standby

Mode

C Digital Inputs and Digital Outputs

High level input voltage V Low level input voltage V Low level output voltage V Hysteresis of Schmitt Trigger

for inputs (Note 7) Supply Current when I

line is active Input Leakage Current I

Pin Capacitance and I

Pin capacitance C

C Bus Capacitance C

Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

/2. All ppm units use 2*V

REF

as full scale range.

REF

— 15 40 µV Tested at PGA = 1

— 110 — dB at DC and PGA =8,

— 5 — ppm/V TA = +25°C, VDD = 2.7V to 5.5V,

2.7 — 5.5 V — 155 190 µA V

DDA

— 145 — µA V

DDS

IH IL

HYST

C bus

C Bus Capacitance

DDB

ILH

ILL

—0.1 0.5µA

0.7 V

—VDDV — — 0.3V —— 0.4VI

0.05V

——Vf

—— 10µA

—— 1 µAV

-1 — — µA VIL = GND

— — 10 pF — — 400 pF

This parameter is ensured by characterization and not 100% tested.

REF

= 5.0V and DR = 3.75 SPS

= 5.0V

= +25°C

PGA = 1

= +25°C, VDD = 2.7V to 5.5V,

PGA = 1

= 5.0V

= 3.0V

= 3 mA, VDD = +5.0V

= 100 kHz

SCL

= 5.5V

MCP3421

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range T Operating Temperature Range T Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 6L SOT-23 θ

A A A

-40 — +85 °C

-40 — +125 °C

-65 — +150 °C

—190.5—°C/W

MCP3421

NOTES:

MCP3421

.000

.001

.002

.003

.004

.005

2.533.544.555.5 V

(V)

PGA = 1

PGA = 2

PGA = 8

PGA = 4

Integral Nonlinearity (% of FSR)

0.001

0.002

0.003

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (oC)

Integral Nonlinearity

VDD = 5 V

VDD = 2.7V

PGA = 1

-20

-15

-10

-5

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Offset Error (µV)

VDD = 5V

PGA = 1

PGA = 4

0.0

2.5

5.0

7.5

10.0

-100 -75 -50 -25 0 25 50 75 100

Input Voltage (% of Full Scale)

Noise (µV, rms)

PGA = 1

PGA = 4

TA = +25°C V

= 5V

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

-100 -75 -50 -25 0 2 5 50 75 100

Input Voltage (% of Full Scale)

Total Error (mV)

PGA = 1

PGA = 4

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Gain Error (% of FSR)

VDD = 5.0V

PGA = 1

PGA = 2

PGA = 8

PGA = 4

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = V

PGA = 8

FIGURE 2-1: INL vs. Supply Voltage (V

(% of FSR)

FIGURE 2-4: Output Noise vs. Input Voltage.

PGA = 2

PGA = 8

/2.

REF

PGA = 2

FIGURE 2-2: INL vs. Temperature.

PGA = 2

FIGURE 2-3: Offset Error vs. Temperature.

FIGURE 2-5: Total Error vs. Input Voltage.

PGA = 8

FIGURE 2-6: Gain Error vs. Temperature.

MCP3421

100

120

140

160

180

200

220

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (

DDA

(µA)

VDD = 5V

VDD = 2.7V

100

200

300

400

500

600

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (

DDS

(nA)

VDD = 5V

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (

DDB

(

VDD = 5V

VDD = 4.5V

VDD = 3.3V

VDD = 2.7V

-1

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Oscillator Drift (%)

VDD = 5.0V

VDD = 2.7V

Data Rate = 3.75 SPS

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.1 1 10 100 1000 10000

Input Signal Frequency (Hz)

Magnitude (dB)

0.1 1 10 100 1k 10k

Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = V

FIGURE 2-7: I

vs. Temperature.

DDA

= 2.7

FIGURE 2-10: OSC Drift vs. Temperature.

REF

/2.

FIGURE 2-8: I

DDS

FIGURE 2-9: I

DDB

vs. Temperature.

FIGURE 2-11: Frequency Response.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP3421 Symbol Description

1V 2V 3SCL

4SDA 5V

+ Positive Differential Analog Input Pin

Ground Pin Serial Clock Input Pin of the I2C Interface Bidirectional Serial Data Pin of the I

- Negative Differential Analog Input Pin

Positive Supply Voltage Pin

C Interface

MCP3421

3.1 Analog Inputs (V

+, VIN-)

VIN+ and VIN- are differential signal input pins. The MCP3421 device accepts a fully differential analog input signal which is connected on the V

+ and VIN-

input pins. The differential voltage that is converted is defined by VIN = (VIN+ - VIN-) where VIN+ is the voltage applied at the V at the VIN- pin. The user can also connect V

+ pin and VIN- is the voltage applied

pin to VSS for a single-ended operation. See Figure 6-4 for differential and single-ended connection examples.

The input signal level is amplified by the programmable gain amplifier (PGA) before the conversion. The differential input voltage should not exceed an absolute of (V

/PGA) for accurate measurement, where V

REF

is the internal reference voltage (2.048V) and PGA is the PGA gain setting. The converter output code will saturate if the input range exceeds (V

REF

/PGA).

The absolute voltage range on each of the differential input pins is from V

-0.3V to VDD+0.3V. Any voltage

above or below this range will cause leakage currents through the Electrostatic Discharge (ESD) diodes at the input pins. This ESD current can cause unexpected performance of the device. The common mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in Section 1.0 “Electrical

Characteristics” and Section 4.0 “Description of Device Operation”.

See Section 4.5 “Input Voltage Range” for more details of the input voltage range.

Figure 3-1 shows the input structure of the device. The

device uses a switched capacitor input stage at the front end. C typically about 4 pF. D C

SAMPLE

is the package pin capacitance and

and D2 are the ESD diodes.

is the differential input sampling capacitor.

3.2 Supply Voltage (V

, VSS)

VDD is the power supply pin for the device. This pin requires an appropriate bypass capacitor of about

0.1 µF (ceramic) to ground. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in some application boards. The supply voltage (V

must be maintained in the 2.7V to 5.5V range for specified operation.

is the ground pin and the current return path of the

device. The user must connect the V

pin to a ground

plane through a low impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that the V

pin be tied to the analog ground path or

isolated within an analog ground plane of the circuit board.

3.3 Serial Clock Pin (SCL)

SCL is the serial clock pin of the I2C interface. The MCP3421 acts only as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the MCP3421 occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the V to the SCL pin. Refer to Section 5.3 “I Communications” for more details of I Interface communication.

line

C Serial

)

MCP3421

VIN+,VIN-

4pF

VT = 0.6V

= 0.6V

LEAKAGE

Sampling Switch

SAMPLE

(3.2 pF)

(~ ±1 nA)

Legend:

V = Signal Source I

LEAKAGE

= Leakage Current at Analog Pin

= Source Impedance SS = Sampling Switch

+, VIN- = Analog Input Pin RS= Sampling Switch Resistor

= Input Pin Capacitance C

SAMPLE

= Sample Capacitance

= Threshold Voltage D1, D2 = ESD Protection Diode

3.4 Serial Data Pin (SDA)

SDA is the serial data pin of the I2C interface. The SDA pin is used for input and output data. In read mode, the conversion result is read from the SDA pin (output). In write mode, the device configuration bits are written (input) though the SDA pin. The SDA pin is an opendrain N-channel driver. Therefore, it needs a pull-up resistor from the V start and stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 5.3

C Serial Communications” for more details of I2C

“I

Serial Interface communication.

line to the SDA pin. Except for

Typical range of the pull-up resistor value for SCL and SDA is from 5 kΩ to 10 kΩ fo r standard (100 kHz) and fast (400 kHz) modes, and less than 1 kΩ for high speed mode (3.4 MHz). The High-Speed mode is not recommended for V

less than 2.7V.

FIGURE 3-1: Equivalent Analog Input Circuit.

MCP3421

2.2V

2.0V

300 µS

Reset

Start-up

Normal Operation

Reset

Time

4.0 DESCRIPTION OF DEVICE

OPERATION

4.1 General Overview

The MCP3421 is a low-power, 18-Bit Delta-Sigma A/D converter with an I2C serial interface. The device contains an on-board voltage reference (2.048V), programmable gain amplifier (PGA), and internal oscillator. When the device powers up (POR is set), it automatically resets the configuration bits to default settings.

Device default settings are:

• Conversion bit resolution: 12 bits (240 sps)

• PGA gain setting: x1

• Continuous conversion Once the device is powered-up, the user can

reprogram the configuration bits using I interface any time. The configuration bits are stored in volatile memory.

User selectable options are:

• Conversion bit resolution: 12, 14, 16, or 18 bits

• PGA Gain selection: x1, x2, x4, or x8

• Continuous or one-shot conversion In the Continuous Conversion mode, the device

converts the inputs continuously . While in the One-Shot Conversion mode, the device converts the input one time and stays in the low-power standby mode until it receives another command for a new conversion. During the standby mode, the device consumes less than 1 µA maximum.

C serial

The POR circuit is shut-down during the low-power standby mode. Once a power-up event has occurred, the device requires additional delay time (approximately 300 µs) before a conversion can take place. During this time, all internal analog circuitries are settled before the first conversion occurs. Figure 4-1 illustrates the conditions for power-up and power-down events under typical start-up conditions.

When the device powers up, it automatically resets and sets the configuration bits to default settings. The default configuration bit conditions are a PGA gain of 1 V/V and a conversion speed of 240 SPS in Continuous Conversion mode. When the device receives an I performs an internal reset similar to a Power-On-Reset event.

C General Call Reset command, it

FIGURE 4-1: POR Operation.

4.3 Internal Voltage Reference

The device contains an on-board 2.048V voltage reference. This reference voltage is for internal use only and not directly measurable. The specifications of the reference voltage are part of the device’s gain and drift specifications. Therefore, there is no separate specification for the on-board reference.

4.2 Power-On-Reset (POR)

The device contains an internal Power-On-Reset (POR) circuit that monitors power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. The POR has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. A 0.1 µF decoupling capacitor should be mounted as close as possible to the V for additional transient immunity.

The threshold voltage is set at 2.2V with a tolerance of approximately ±5%. If the supply voltage falls below this threshold, the device will be held in a reset condition. The typical hysteresis value is approximately 200 mV.

4.4 Analog Input Channel

The differential analog input channel has a switched capacitor structure. The internal sampling capacitor (3.2 pF for PGA = 1) is charged and discharged to process a conversion. The charging and discharging of the input sampling capacitor creates dynamic input currents at each input pin. The current is a function of the differential input voltages, and inversely proportional to the internal sampling capacitance, sampling frequency, and PGA setting.

MCP3421

VIN+VIN-–=

INCOM

VIN+VIN-+

-------------------------------=

Where:

=VIN+ - VIN-

REF

= 2.048V

REF

– VINPGA

•

()V

REF

1LSB–()

≤≤

ZIN(f) = 2.25 MΩ/PGA

4.5 Input Voltage Range

The differential (VIN) and common mode voltage (V setting are defined by:

The input signal levels are amplified by the internal programmable gain amplifier (PGA) at the front end of the ΔΣ modulator.

The user needs to consider two conditions for the input voltage range: (a) Differential input voltage range and (b) Absolute maximum input voltage range.

4.5.1 DIFFERENTIAL INPUT VOLTAGE

The device performs conversions using its internal reference voltage (V absolute value of the differential input voltage (VIN), with PGA setting is included, needs to be less than the internal reference voltage. The device will output saturated output codes (all 0s or all 1s except sign bit) if the absolute value of the input voltage (V PGA setting is included, is greater than the internal reference voltage (V voltage range is given by:

) at the input pins without considering PGA

INCOM

RANGE

= 2.048V). Therefore, the

REF

= 2.048V). The input ful l-scale

REF

), with

4.6 Input Impedance

The device uses a switched-capacitor input stage using a 3.2 pF sampling capacitor. This capacitor is switched (charged and discharged) at a rate of the sampling frequency that is generated by on-board clock. The differential input impedance varies with the PGA settings. The typical differential input impedance during a normal mode operation is given by:

Since the sampling capacitor is only switching to the input pins during a conversion process, the above input impedance is only valid during conversion periods. In a low power standby mode, the above impedance is not presented at the input pins. Therefore, only a leakage current due to ESD diode is presented at the input pins.

The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can degrade the system performance, such as offset, gain, and Integral Non-Linearity (INL) errors. Ideally, the input source impedance should be zero. This can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms.

EQUATION 4-1:

If the input voltage level is greater than the above limit, the user can use a voltage divider and bring down the input level within the full-scale range. See Figure 6-7 for more details of the input voltage divider circuit.

4.5.2 ABSOLUTE MAXIMUM INPUT VOLTAGE RANGE

The input voltage at each input pin must be less than the following absolute maximum input voltage limits:

• Input voltage < V

• Input voltage > VSS-0.3V

Any input voltage outside this range can turn on the input ESD protection diodes, and result in input leakage current, causing conversion errors, or permanently damage the device.

Care must be taken in setting the input voltage ranges so that the input voltage does not exceed the absolute maximum input voltage range.

+0.3V

4.7 Aliasing and Anti-aliasing Filter

Aliasing occurs when the input signal contains timevarying signal components with frequency greater than half the sample rate. In the aliasing conditions, the device can output unexpected output codes. For applications that are operating in electrical noise environments, the time-varying signal noise or high frequency interference components can be easily added to the input signals and cause aliasing. Although the device has an internal first order sinc filter, the filter response (Figure 2-11) may not give enough attenuation to all aliasing signal components. To avoid the aliasing, an external anti-aliasing filter, which can be accomplished with a simple RC low-pass filter, is typically used at the input pins. The low-pass filter cuts off the high frequency noise components and provides a band-limited input signal to the input pins.

4.8 Self-Calibration

The device performs a self-calibration of offset and gain for each conversion. This provides reliable conversion results from conversion-to-conversion over variations in temperature as well as power supply fluctuations.

MCP3421

Number of Output Code

Maximum Code 1+()PGA

+VIN-–()

2.048V

---------------------------------- -

××

Where:

See Table 4-3 for Maximum Code.

LSB

REF

--------------------- -

2 2.048V

--------------------------==

Where:

N = User programmable bit resolution:

12,14,16, or 18

4.9 Digital Output Codes and Conversion to Real Values

4.9.1 DIGITAL OUTPUT CODE FROM

DEVICE

The digital output code is proportional to the input voltage and PGA settings. The output data format is a binary two’s complement. With this code scheme, the MSB can be considered a sign indicator. When the MSB is a logic ‘0’, the input is positive. When the MSB is a logic ‘1’, the input is negative. The following is an example of the output code:

a. for a negative full scale input voltage:

100...000

Example: (V

b. for a zero differential input voltage: 000...000

Example: (V

c. for a positive full scale input voltage:

011...111

Example: (V

The MSB (sign bit) is always transmitted first through

C serial data line. The resolution for each

the I conversion is 18, 16, 14, or 12 bits depending on the conversion rate selection bit settings by the user.

The output codes will not roll-over even if the input voltage exceeds the maximum input range. In this case, the code will be locked at 0111...11 for all voltages greater than (V voltages less than -V example of output codes of various input levels for 18 bit conversion mode. Table 4-3 shows an ex ample of minimum and maximum output codes for each conversion rate option.

The number of output code is given by:

EQUATION 4-2:

The LSB of the data conversion is given by:

EQUATION 4-3:

+-VIN-) •PGA = -2.048V

+-VIN-) = 0

+-VIN-) • PGA = 2.048V

- 1 LSB)/PGA and 1000...00 for

REF

/PGA. Table 4-2 shows an

REF

Table 4-1 shows the LSB size of each conversion rate

setting. The measured unknown input voltage is obtained by multiplying the output codes with LSB. See the following section for the input voltage calculation using the output codes.

TABLE 4-1: RESOLUTION SETTINGS VS.

LSB

Resolution Setting LSB

12 bits 1 mV 14 bits 250 µV 16 bits 62.5 µV 18 bits 15.625 µV

TABLE 4-2: EXAMPLE OF OUTPUT CODE

FOR 18 BITS (NOTE 1,NOTE 2)

Input Voltage:

+-VIN-] • PGA

≥ V

REF

- 1 LSB 011111111111111111

REF

2LSB 000000000000000010 1LSB 000000000000000001

0 000000000000000000

-1 LSB 111111111111111111

-2 LSB 111111111111111110

- V

REF

< -V

REF

Note 1: MSB is a sign indicator:

0: Positive input (V 1: Negative input (V

2: Output data format is binary two’s

complement.

Digital Output Code

011111111111111111

100000000000000000 100000000000000000

+>VIN-)

+<VIN-)

TABLE 4-3: MINIMUM AND MAXIMUM

OUTPUT CODES (NOTE)

Resolution

Setting

Data Rate

12 240 SPS -2048 2047 14 60SPS -8192 8191 16 15SPS -32768 32767 18 3.75 SPS -131072 131071

Note: Maximum n-bit code = 2

Minimum n-bit code = -1 x 2

Minimum

Code

N-1

Maximum

Code

- 1

N-1

+ 29 hidden pages

Datasheet MCP3421 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Absolute Maximum Ratings†

1.2 Electrical Specifications

ELECTRICAL CHARACTERISTICS

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-4: Output Noise vs. Input Voltage.

FIGURE 2-2: INL vs. Temperature.

FIGURE 2-3: Offset Error vs. Temperature.

FIGURE 2-5: Total Error vs. Input Voltage.

FIGURE 2-6: Gain Error vs. Temperature.

FIGURE 2-10: OSC Drift vs. Temperature.

FIGURE 2-11: Frequency Response.

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN FUNCTION TABLE

3.3 Serial Clock Pin (SCL)

3.4 Serial Data Pin (SDA)

FIGURE 3-1: Equivalent Analog Input Circuit.

4.1 General Overview

FIGURE 4-1: POR Operation.

4.3 Internal Voltage Reference

4.2 Power-On-Reset (POR)

4.4 Analog Input Channel

4.5 Input Voltage Range

4.6 Input Impedance

4.7 Aliasing and Anti-aliasing Filter

4.8 Self-Calibration

4.9 Digital Output Codes and Conversion to Real Values