Datasheet MCP3001 Datasheet

MCP3001

2.7V 10-Bit A/D Converter with SPI™ Serial Interface

Features

• 10-bit resolution

• ±1 LSB max DNL

• ±1 LSB max INL

• On-chip sample and hold

• SPI™ serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 200 ksps sampling rate at 5V

• 75 ksps sampling rate at 2.7V

• Low power CMOS technology

- 5 nA typical standby current, 2 µA max

- 500 µA max active current at 5V

• Industrial temp range: -40°C to +85°C

• 8-pin PDIP, SOIC, MSOP and TSSOP packages

Applications

• Sensor Interface

• Process Control

• Data Acquisition

• Battery Op erated Systems

Description

The Microchip Technology Inc. MCP3001 is a succes­sive approximation 10-bit A/D converter (ADC) with on­board sample and hold circuitry. T he dev ic e p rov id es a
single pseudo-differential input. Differential Nonlinear­ity (DNL) and Integral N onlin earity (INL) are bo th spe c­ified at ±1 LSB max. Communication with the device is
done using a simple serial interface compa tible with the
SPI protocol. The de vi ce is capable of sample rates u p
to 200 ksps at a clock rat e of 2.8 MHz. The MCP3001
operates over a broad voltage range (2.7V - 5.5V).
Low current design permits operation with a typical
standby current of only 5 nA and a typical active c urrent
of 400 µA. The device is offered in 8-pin PDIP, MSOP,
TSSOP and 150 mil SOIC packages.

Package Types

PDIP, MSOP, SOIC, TSSOP

V

REF

IN+
IN–
V

SS

Illustration not to scale

MCP3001

1
2

3
4

Functional Block Diagram

V

REF

DAC

Comparator

IN+

Sample

and
Hold

IN-

Control Logic

CS/SHDN

8
7

6
5

CLK

V

DD

CLK
D

OUT

CS/SHDN

V

10-Bit SAR

Shift

Register

D

V

SS

DD

OUT

SPI™ is a trademark of Motorola Inc.

© 2007 Microchip Technology Inc. DS21293C-page 1

MCP3001

1.0 ELECTRICAL

PIN FUNCTION TABLE

CHARACTERISTICS

1.1 Maximum Ratings*

VDD.........................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature ..........................-65°C to +150°C

Ambient temp. with power applied.....-65°C to +125°C

ESD protection on all pins (HBM)........................> 4kV

*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or
any other conditions above those indicated in the operational
listings of this specification is not implied. Exposure to maxi­mum rating conditions for extended periods may affect device
reliability.

...... -0.6V to VDD +0.6V

SS

Name Function

V

DD

V

SS

+2.7V to 5.5V Power Supply

Ground
IN+ Positive A nalog Input
IN- Negative Analog Input
CLK Serial Clock
D

OUT

Serial Data Out
CS/SHDN Chip Select/Shutdown Input
V

REF

Reference V oltage Input

ELECTRICAL CHARACTERISTICS

All parameters ap ply at VDD = 5V , VSS = 0V , V
unless otherwise noted. Typical values apply for V

Parameter Sym Min Typ Max Units Conditions

Conversion Rate:

Conversion Time t

Analog Input Sample Time t

Throughput Rate f

CONV

SAMPLE

SAMPLE

DC Accuracy:

Resolution 10 bits
Integral Nonlinearity INL — ±0.5 ±1 LSB
Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes over tem-

Offset Error — — ±1.5 LSB
Gain Error — — ±1 LSB

Dynamic Performance:

Total Harmonic Distortion THD — -76 — dB V
Signal to Noise and Distortion

SINAD — 61 — dB V

(SINAD)
Spurious Free Dynamic Range SFDR — 80 — dB V

Reference Input:

Voltage Range V
Current Drain I

REF

REF

Note 1: This parameter is guaranteed by characterization and not 100% tested.

2: See graph that relates linearity performance to V
3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity perfor-

mance, especially at elevated temperatures.

REF

= 5V, T

DD

= -40°C to +85°C, f

AMB

= 5V, T

=25°C, unless otherwise noted.

AMB

SAMPLE

— — 10 clock

cycles

1.5 clock
cycles

— — 200

75

ksps
ksps

0.25 — VDD VNote 2
—90

0.001

level.

REF

150

3

µA
µA CS

= 200 ksps and f

V

= V
= V

REF
REF

= 5V

= 2.7V

DD

V

DD

perature

= 0.1V to 4.9V@1 kHz

IN

= 0.1V to 4.9V@1 kHz

IN

= 0.1V to 4.9V@1 kHz

IN

= VDD = 5V

CLK

= 14*f

SAMPLE

,

DS21293C-page 2 © 2007 Microchip Technology Inc.

MCP3001

All parameters ap ply at VDD = 5V , VSS = 0V , V
unless otherwise noted. Typical values apply for V

REF

= 5V, T

= 5V, T

DD

= -40°C to +85°C, f

AMB

=25°C, unless otherwise noted.

AMB

= 200 ksps and f

SAMPLE

Parameter Sym Min Typ Max Units Conditions

Temperature Ranges:

Specified Temperature Range T
Operating Temperature Range T
Storage Temperature Range T

A
A
A

-40 — +85 °C

-40 — +85 °C

-65 — +150 °C

Thermal Package Resistance:

Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC θ
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-TSSOP θ

θ

JA
JA

θ

JA
JA

—85—°C/W
—163—°C/W
—206—°C/W
——°C/W

Analog Inputs:

Input Voltage Range (IN+) IN+ IN- — V
Input Vo ltage Range (IN-) IN- V

-100 — VSS+100 mV

SS

+IN- V

REF

Leakage Current — 0.001 ±1 µA
Switch Resistance R
Sample Capac itor C

SS

SAMPLE

—1K— Ω See Figure 4-1
— 20 — pF See Figure 4-1

Digital Input/Output:

Data Coding Format Straight Binary
High Level Input Voltage V
Low Level Input Voltage V
High Level Output Voltage V
Low Level Output Voltage V
Input Leakage Current I
Output Leakage Current I
Pin Capacitance

CIN, C

(all inputs/outpu t s)

OUT

0.7 V
——0.3 VDDV

4.1 — — V IOH = -1 mA, VDD = 4.5V
——0.4VI

-10 — 10 µA VIN = VSS or V

-10 — 10 µA V
— — 10 pF VDD = 5.0V (Note 1)

IH

IL
OH
OL
LI

LO

——V

DD

= 1 mA, VDD = 4.5V

OL

= VSS or V

OUT

= 25°C, f = 1 MHz

T

AMB

Timing Parameters:

Clock Frequency f

Clock High Time t
Clock Low Time t
CS

Fall To First Rising CLK Edge t

CLK Fall To Output Data Valid t

CLK Fall To Output Enable t

CS Rise To Output Disable t

CLK

HI

LO

SUCS

DO

EN

DIS

——2.8

1.05
160 — — ns
160 — — ns
100 — — ns

— — 125

200

— — 125

200

— — 100 ns See test circuits, Figure 1-2

MHz

VDD = 5V (Note 3)

MHz

= 2.7V (Note 3)

V

DD

nsnsVDD = 5V, See Figure 1-2

= 2.7, See Figure 1-2

V

DD

nsnsVDD = 5V, See Figure 1-2

V

= 2.7, See Figure 1-2

DD

(Note 1)

Disable Time t

CS
D

Rise Time t

OUT

CSH

R

350 — — ns

— — 100 ns See test circuits, Figure 1-2

(Note 1)

Fall Time t

D

OUT

F

— — 100 ns See test circuits, Figure 1-2

(Note 1)

Note 1: This parameter is guaranteed by characterization and not 100% tested.

2: See graph that relates linearity performance to V

REF

level.

3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity perfor-

mance, especially at elevated temperatures.

CLK

DD

= 14*f

DD

SAMPLE

,

© 2007 Microchip Technology Inc. DS21293C-page 3

MCP3001

All parameters ap ply at V
unless otherwise noted. Typical values apply for V

= 5V , VSS = 0V , V

DD

REF

= 5V, T

= 5V, T

DD

= -40°C to +85°C, f

AMB

=25°C, unless otherwise noted.

AMB

= 200 ksps and f

SAMPLE

Parameter Sym Min Typ Max Units Conditions

Power Requirements:

Operating Voltage V
Operating Current I

Standby Current I

DD

DD

DDS

2.7 — 5.5 V
—400

210

500 µ AµAVDD = 5.0V, D

= 2.7V, D

V

DD

—0.005 2 µACS = VDD = 5.0V

Note 1: This parameter is guaranteed by characterization and not 100% tested.

2: See graph that relates linearity performance to V

REF

level.

3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity perfor-

mance, especially at elevated temperatures.

CS

CLK

D

OUT

t

SUCS

HI-Z

t

t

HI

LO

t

EN

t

DO

Null BIT

MSB OUT

t

t

R

t

F

DIS

LSB

= 14*f

CLK

unloaded

OUT

unloaded

OUT

t

CSH

HI-Z

SAMPLE

,

FIGURE 1-1: Serial Timing.

DS21293C-page 4 © 2007 Microchip Technology Inc.

MCP3001

Load circuit for tR, tF, t

1.4V

D

OUT

Voltage Waveforms for tR, t

D

OUT

t

R

Voltage Waveforms for t

CLK

D

OUT

DO

3kΩ

Test Point

CL = 30 pF

t

DO

Load circuit for t

DIS

and t

EN

Test Point

V

DD

3kΩ

D

OUT

30 pF

V

F

V

OH

V

OL

t

F

CS

Voltage Waveforms for t

CLK
D

OUT

DO

Voltage Waveforms for t

CS

D

OUT

t

DIS

VDD/2

t

SS

12

V

IH

Waveform 2

tEN Waveform

Waveform 1

DIS

EN

3

4

B9

t

EN

DIS

90%

Waveform 1*

t

DIS

D

OUT

10%

Waveform 2†

* Waveform 1 is for an output with internal condi-

tions such that the output is high, unless disabled
by the output control.

† Waveform 2 is for an output with internal condi-

tions such that the output is low, unless disabled
by the output control.

FIGURE 1-2: T est Circuits.

© 2007 Microchip Technology Inc. DS21293C-page 5

MCP3001

V

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, VDD = V

REF

= 5V, f

SAMPLE

= 200 ksps, f

= 14*Sample Rate, TA = 25°C

CLK

0.4

0.3

0.2

Positive INL

0.1

0.0

-0.1

INL (LSB)

-0.2

Negative INL

-0.3

-0.4
0 25 50 75 100 125 150 175 200 225 250

Sample Rate (ksps)

FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate.

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

INL (LSB)

-0.4

-0.6

-0.8

-1.0
0123456

Positive INL

Negati ve INL

V

(V)

REF

0.4
= V

0.3

0.2

DD

REF

= 2.7V

Positive INL

0.1

0.0

-0.1

INL (LSB)

-0.2

Negative INL

-0.3

-0.4
0 25 50 75 100

Sample Rate (ksps)

FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate (V

= 2.7V).

DD

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

INL (LSB)

-0.4

-0.6

-0.8

-1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Positive INL

Negative INL

V

REF

(V)

VDD = V
f

SAMPLE

= 2. 7V

REF

= 75 ksps

FIGURE 2-2: Integral Nonlinearity (INL) vs. V

REF

.

FIGURE 2-5: Integral Nonlinearity (INL) vs. V

REF

(VDD = 2.7V).

0.5
VDD = V

0.4
f

0.3

0.2

0.1

0.0

-0.1

INL (LSB)

-0.2

-0.3

-0.4

-0.5
0 128 256 384 512 640 768 896 1024

SAMPLE

= 5V

REF

= 200 ksps

Digi tal Code

FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).

DS21293C-page 6 © 2007 Microchip Technology Inc.

0.50
VDD = V

0.40
f

SAMPLE

0.30

0.20

0.10

0.00

-0.10

INL (LSB)

-0.20

-0.30

-0.40

-0.50
0 128 256 384 512 640 768 896 1024

= 2.7V

REF

= 75 ksps

Digi tal Code

FIGURE 2-6: Integral Nonlinearity (INL) vs. Code
(Representative Part, V

= 2.7V).

DD

MCP3001

Note: Unless otherwise indicated, VDD = V

0.4

0.3

0.2

0.1

0.0

-0.1

INL (LSB)

-0.2

-0.3

-0.4

-50 -25 0 25 50 75 100

Positive INL

Negative INL

REF

= 5V, f

SAMPLE

Temperature ( ° C)

FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature.

0.4

0.3

0.2

0.1

0.0

-0.1

DNL (LSB)

-0.2

-0.3

-0.4
0 25 50 75 100 125 150 175 200 225 250

Positive DNL

Negati ve DNL

Sample Rate (ksps)

= 200 ksps, f

= 14*Sample Rate,TA = 25°C

CLK

0.4
VDD = V

0.3
f

SAMPLE

0.2

0.1

0.0

-0.1

INL (LSB)

-0.2

-0.3

-0.4

-50-25 0 255075100

= 2.7V

REF

= 75 ksps

Positive INL

Negative INL

Temperat ure (°C)

FIGURE 2-10: Integral Nonlinearity (INL) vs.

VDD = V

= 2.7V).

DD

= 2.7V

REF

Positive DNL

Negative DNL

Sample Rate (ksps)

Temperature (V

0.4

0.3

0.2

0.1

0.0

-0.1

DNL (LSB)

-0.2

-0.3

-0.4

0 25 50 75 100

FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

DNL (LSB)

-0.6

-0.8

-1.0
012345

Positive DNL

Negative DNL

V

(V)

REF

FIGURE 2-9: Differential Nonlinearity (DNL) vs.

.

V

REF

FIGURE 2-11: Differential Nonlinearity (DNL) vs.
Sample Rate (V

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

DNL (LSB)

-0.4

-0.6

-0.8

-1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

FIGURE 2-12: Differe ntia l Nonl in eari t y (DN L) vs. V

= 2.7V).

DD

Pos i t i ve DNL

Negati ve DNL

V

REF

(V)

VDD = V
f

SAMPLE

= 2.7V

REF

= 75 ks ps

REF

(VDD = 2.7V).

© 2007 Microchip Technology Inc. DS21293C-page 7

MCP3001

Note: Unless otherwise indicated, VDD = V

0.5
VDD = V

0.4
f

0.3

0.2

0.1

0.0

-0.1

DNL (LSB)

-0.2

-0.3

-0.4

-0.5
0 128 256 384 512 640 768 896 1024

SAMPLE

= 5V

REF

= 200 ksps

REF

= 5V, f

SAMPLE

Digit al Code

FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).

0.3

0.2

0.1

0.0

-0.1

DNL (LSB)

-0.2

-0.3

-50 -25 0 25 50 75 100

Positive DNL

Negative DNL

= 200 ksps, f

= 14*Sample Rate,TA = 25°C

CLK

0.5
VDD = V

0.4
f

SAMPLE

0.3

0.2

0.1

0.0

-0.1

DNL (LSB)

-0.2

-0.3

-0.4

-0.5
0 128 256 384 512 640 768 896 1024

= 2.7V

REF

= 75 ksps

Digi t al Code

FIGURE 2-16: Differential Nonlinearity (DNL) vs.
Code (Representative Part, V

0.3
VDD = V

0.2

f

SAMPLE

0.1

0.0

-0.1

DNL (LSB)

-0.2

-0.3

-50 -25 0 25 50 75 100

= 2. 7V

REF

= 75 ks ps

= 2.7V).

DD

Pos i tive DNL

Negative DNL

Tempe r at ure (°C)

FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

Gain Error (LSB)

-0.6

-0.8

-1.0
012345

FIGURE 2-15: Gain Error vs. V

VDD = 5V
f

SAMPLE

VDD = 2.7V
f

SAMPLE

= 200 ksps

V

= 75 ksps

(V)

REF

REF

.

Temperatur e (° C)

FIGURE 2-17: Differential Nonlinearity (DNL) vs.
Temperature (V

8
7
6
5
4
3
2

Offset Error (LSB)

1
0

0.0 1.0 2.0 3.0 4.0 5.0

FIGURE 2-18: Offset Error vs. V

= 2.7V).

DD

VDD = 5V
f

SAMPLE

= 200 k sps

VDD = 2.7V
f

SAMPLE

V

= 75 k sps

(V)

REF

REF

.

DS21293C-page 8 © 2007 Microchip Technology Inc.

MCP3001

SAMPLE

Input Signal Level (dB)

Note: Unless otherwise indicated, VDD = V

0.1
VDD = V

f

0.0

-0.1

-0.2

Gain Error (LSB)

-0.3

-0.4

-50 -25 0 25 50 75 100

SAMPLE

= 2.7V

REF

= 75 ks ps

VDD = V
f

SAMPLE

= 5V

REF

= 200 k sps

Temperature (°C)

FIGURE 2-19: Gain Error vs. Temperature.

70
60
50

SNR (dB)

40
30
20

VDD = V
f

SAMPLE

= 2. 7V

REF

= 75 ksps

10

0

1 10 100

Input Fr equency ( kHz)

VDD = V
f

SAMPLE

REF

= 200 k sps

REF

= 5V

= 5V, f

SAMPLE

= 200 ksps, f

= 14*Sample Rate,TA = 25°C

CLK

1.0
VDD = V

0.9
f

0.8

0.7

0.6

0.5

0.4

0.3

0.2

Offset Error (LSB)

0.1

0.0

-50 -25 0 25 50 75 100

= 5V

REF

= 200 k sps

VDD = V

= 75 k sps

f

SAMPLE

REF

= 2.7V

Temperat ur e (°C)

FIGURE 2-22: Offset Error vs. Temperature.

70
60
50
40
30

SINAD (dB)

20

VDD = V
f

SAMPLE

10

0

1 10 100

= 2.7V

REF

= 75 ksps

Input Fr equ ency ( k Hz)

VDD = V
f

SAMPLE

= 5V

REF

= 200 ksps

FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input Frequency.

0

-10

-20

THD (dB)

-30

-40

-50

-60

-70

VDD = V
f

SAMPLE

= 2.7V

REF

= 75 ksps

VDD = V
f

SAMPLE

= 5V

REF

= 200 ksps

-80

-90

-100
110100

Input Frequency (kHz)

FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.

FIGURE 2-23: Signal to Noise Ratio and Distortion (SINAD) vs. Input Frequency.

80
70

VDD = V

60

f

50
40
30

SINAD (dB)

20
10

0

-40 -35 -30 -25 -20 -15 -10 -5 0

SAMPLE

= 5V

REF

= 200 ksps

VDD = V
f

SAMPLE

= 2.7V

REF

= 75 ksps

FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level.

© 2007 Microchip Technology Inc. DS21293C-page 9

MCP3001

Note: Unless otherwise indicated, VDD = V

10.0

9.9

9.8

9.7

9.6

9.5

9.4

ENOB (rms)

9.3

9.2

9.1

9.0

0.0 1.0 2.0 3.0 4.0 5.0

VDD = V
f

SAMPLE

= 2.7V

REF

= 75 ksps

V

REF

(V)

VDD = V
f

SAMPLE

= 5V, f

REF

= 5V

REF

= 200 ksps

SAMPLE

FIGURE 2-25: Effective Number of Bits (ENOB) vs.
V

.

REF

100

90
80
70
60

SFDR (dB)

50
40
30

VDD = V
f

SAMPLE

= 2.7V

REF

= 75 k sps

20
10

0

110100

Input Frequency (kHz)

VDD = V
f

SAMPLE

= 5V

REF

= 200 k sps

= 200 ksps, f

= 14*Sample Rate,TA = 25°C

CLK

10.0

9.8

9.6

9.4

9.2

9.0

VDD = V
f

SAMPLE

= 5V

REF

= 200 k s ps

8.8

8.6

ENOB (rms)

8.4

VDD = V
f

SAMPLE

= 2.7V

REF

= 75 ksps

8.2

8.0
1 10 100

Input Frequency (kHz)

FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.

0

VDD = V

-10

f

SAMPLE

-20

-30

-40

-50

-60

-70

-80

Power Supply Rejection (dB)

1 10 100 1000 10000

= 5V

REF

= 200 ksps

Ripple Frequency (kHz)

FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

Amplitude (dB)

-100

-110

-120

-130
0 20000 40000 60000 80000 100000

Frequency (Hz)

VDD = V

REF

f

= 200 k sps

SAMPLE

f

= 10.0097 kHz

INPUT

4096 poin ts

= 5V

FIGURE 2-27: Frequency Spectrum of 10 kHz Input
(Representative Part).

FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

Amplitude (dB)

-100

-110

-120

-130
0 5000 10000 15000 20000 25000 30000 35000

Frequency (Hz)

VDD = V

= 75 ksps

f

SAMPLE

= 1. 00708 k Hz

f

INPUT

4096 points

REF

= 2. 7V

FIGURE 2-30: Frequency Spectrum of 1 kHz Input
(Representative Part, V

= 2.7V).

DD

DS21293C-page 10 © 2007 Microchip Technology Inc.

MCP3001

=1.05 M Hz

= 1. 05 M Hz

Note: Unless otherwise indicated, VDD = V

500
450
400
350
300
250

(µA)

DD

I

200
150

V

= V

REF

100

50

0

2.02.53.03.54.04.55.05.56.0

FIGURE 2-31: I

500
450
400
350
300
250

(µA)

200

DD

I

150
100

50

DD

All poi nt s at f
at V

REF

= 2.8 M Hz ex cept

CLK

= VDD = 2.5V , f

CLK

VDD (V)

vs. VDD.

DD

VDD = V

= 5V

REF

VDD = V

= 2.7V

REF

0

10 100 1000 10000

Clock Frequency (kHz)

REF

= 5V, f

SAMPLE

= 200 ksps, f

120
110
100

(µA)

REF

I

FIGURE 2-34: I

(µA)

REF

I

= 14*Sample Rate,TA = 25°C

CLK

90
80
70
60
50
40

V

REF = VDD

30
20

All points at f

10

at V

REF

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

= 2.8 M Hz ex c e pt

CLK

= VDD = 2.5V , f

CLK

VDD (V)

vs. VDD.

REF

120
110
100

90
80
70
60
50
40
30
20
10

0

10 100 1000 10000

VDD = V

= 5V

REF

VDD = V

REF

= 2.7V

Clock Frequency (kHz)

FIGURE 2-32: IDD vs. Clock Frequency.

600
550
500

VDD = V

= 5V

450
400
350
300

(µA)

DD

250

I

200
150
100

50

0

-50 -25 0 25 50 75 100

FIGURE 2-33: I

REF

f

= 2.8 M Hz

CLK

VDD = V

= 2. 7V

REF

f

= 1.05 M Hz

CLK

Temperature (°C)

vs. Temperature.

DD

FIGURE 2-35: I

120
110
100

90
80
70
60

(µA)

50

REF

I

40
30
20
10

0

-50-250 255075100

FIGURE 2-36: I

vs. Clock Frequency.

REF

VDD = V

REF

= 2. 8 M Hz

f

CLK

VDD = V

= 2.7V

REF

= 1. 05 M Hz

f

CLK

Temper a ture (°C)

vs. Temperature.

REF

= 5V

© 2007 Microchip Technology Inc. DS21293C- page 11

MCP3001

Note: Unless otherwise indicated, VDD = V

60

V

= CS = V

REF

50

40

30

(pA)

DDS

I

20

10

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

FIGURE 2-37: I

100.00

10.00

1.00

(nA)

DDS

I

VDD = V

DD

vs. VDD.

DDS

= CS = 5V

REF

VDD (V)

REF

= 5V, f

SAMPLE

= 200 ksps, f

= 14*Sample Rate,TA = 25°C

CLK

2.0

1.8

VDD = V

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Analog Input Leakage (nA)

0.0

-50-250 255075100

REF

= 5V

Temperature (°C)

FIGURE 2-39: Analog Input Leakage Current vs. Temperature.

0.10

0.01

-50 -25 0 2 5 50 75 100

FIGURE 2-38: I

Temperature (°C)

vs. Temperature.

DDS

DS21293C-page 12 © 2007 Microchip Technology Inc.

MCP3001

3.0 PIN DESCRIPTIONS

3.1 IN+

Positive analog input. This input can vary from IN- to

+ IN-.

V

REF

3.2 IN-

Negative analog input. This input can vary ±100 mV
from V

3.3 CS/SHDN(Chip Select/Shutdown)

The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conver­sion and put the device in low power standby when
pulled high. The CS
between conversion s.

3.4 CLK (Serial Clock)

The SPI clock pin is used to initi ate a co nversion an d to
clock out each bit of the conversion as it takes place.
See Section 6.2 for co nstraints on clock speed.

3.5 DOUT (Serial Data output)

The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.

.

SS

/SHDN pin must be pulled high

In this diagram, it is shown that the source impedance

) adds to the internal sampling swi tch , (RSS) imped-

(R

S

ance, directly affecting the time that is required to
charge the capacitor, C

. Consequently, a larger

SAMPLE

source impedance increases the offset, gain, and inte­gral linearity errors of the conversion.

Ideally, the impedance of the signal source should be
near zero. This is achie vable with an operat ional ampli­fier such as the MCP601 , w hic h h as a clo se d lo op ou t­put impedance of tens of ohms. The adverse affe cts of
higher source impedances are shown in Figure 4-2.

If the voltage le vel of IN+ is equal to or less than IN-, the
resultant cod e will be 000h. If the voltag e at IN+ is e qual
to or greater than {[V

+ (IN-)] - 1 LSB}, then the out-

REF

put code will be 3FFh. If the volt ag e lev el at IN- is more
than 1 LSB below V
input will have to go below V

, then the voltage l evel at the IN+

SS

to see the 000h output

SS

code. Conversely, if IN- is more than 1 LSB a bove Vss,
then the 3FFh code will not be seen unless the IN+
input level goes above V

REF

level.

4.2 Reference Input

The reference input (V
voltage range and the LSB size, as shown below.

) determines the analog inp ut

REF

V

LSB Size

REF

-------------=

1024

4.0 DEVICE OPERATION

The MCP3001 A /D converter employs a conv entional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the first rising edge of the
serial clock after CS has been pu lled low . Followin g this
sample time, the input switch of the converter opens
and the device uses the collected charge on the inter­nal sample and hold capacitor to produce a serial 10-bit
digital out put code. Con version rate s of 200 ksps are
possible on the MCP300 1. See Section 6.2 for informa­tion on minimum clock rates. Communication with the
device is done using a 3 -wire SPI-c ompati ble inter face.

4.1 Analog Inputs

The MCP3001 provides a single pseudo-differential
input. The IN+ input can range from IN- to (V
The IN- in put is limited to ±100 mV from th e V
The IN- input can be used to cancel small signal com­mon-mode noise which is present on both the IN+ and
IN- inputs.

For the A/D Converter to meet specifi cation, the charg e
holding capa citor, C

must be given enough time

SAMPLE

to acquire a 10-bit accurate voltage level during the

1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.

REF

+IN-).

rail.

SS

As the reference input is reduced, the LSB size is
reduced accordingly. The theoretical digi tal output cod e
produced by the A/D Converter is a function of the ana­log input signal and the reference input as shown
below.

1024*V

IN

Digital Output Code

----------------------- -=

V

REF

where:

= analog input voltage = V(IN+) - V(IN-)

V

IN

= reference voltage

V

REF

When using an external voltage reference device, the
system designe r should always refer to the manufac­turer’s recommendations fo r circuit layout. Any inst abil­ity in the operation of the reference device will have a
direct effect on the operation of the ADC.

© 2007 Microchip Technology Inc. DS21293C- page 13

MCP3001

CHx

R

SS

VA

Legend

VA = signal source

R

= source impedance

SS

CHx = input channel pad

C

= input pin capacitance

PIN

V

= threshold voltage

T

I

LEAKAGE

C

SAMPLE

= leakage current at the pin

due to various junctions

SS = sampling switch

R

= sampling switch resistor

S

= sample/hold capacitance

C

PIN

7pF

V

DD

V

= 0.6V

T

V

= 0.6V

T

I

LEAKAGE

±1 nA

Sampling
Switch

R

SS

= 1 kΩ

S

C

SAMPLE

= DAC capacitance
= 20 pF

V

SS

FIGURE 4-1: Analog Input Model.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Clock Frequency (MHz)

0.0

VDD = V
f

SAMPLE

100 1000 10000

= 2.7V

REF

= 75 ksps

Input Resistance (Ohms)

VDD = V
f

SAMPLE

= 5V

REF

= 200 ksps

FIGURE 4-2: Maximum Clock Frequency vs. Input
Resistance (R

) to maintain less than a 0.1LSB

S

deviation in INL from nominal con di tion s.

DS21293C-page 14 © 2007 Microchip Technology Inc.

MCP3001

5.0 SERIAL COMMUNICATIONS

Communication with the device is done using a stan­dard SPI compatible serial interface. Initiating commu­nication with the MCP3001 begins with the CS going
low. If the device was powered up with the CS
it must be broug ht high a nd back low to initiate commu­nication. The device will begin to sample the analog
input on the first rising edge after CS
sample period wil l end i n the fa lling e dge of the secon d
clock, at which time th e devic e wi ll outpu t a low nul l bit.
The next 10 clocks will output the result of the conver­sion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 10 data bits have been transmitted and the

CS

t

SUCS

CLK

t

SAMPLE

D

OUT

HI-Z

NULL

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

BIT

pin low,

goes low. The

t

CYC

t

CONV

device continues to rec eive cl ocks while the CS

is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are pro­vided to th e device while CS

is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.

If it is desired, the CS

can be raised to end the conv er­sion period at any time during the transmission. Faster
conversion rates can be obtained by using this tech­nique if not all the bits are captured before starting a
new cycle. Some syst em designers use t his met hod by
capturing only the highest order 8 bits and ‘throwing
away’ the l ower 2 bits.

t

CSH

Power
Down

t

**

DATA

HI-Z

NULL

B9 B8 B7 B6

BIT

* After completing the data transfer, if further clocks are applied with CS
followed by zeros indefinitely. See Figure below.

: during this time, the bias current and the comparator powers down and the reference input becomes a

** t

DATA

high impedance node.

FIGURE 5-1: Communication with MCP3001 (MSB first Format).

t

CYC

CS

t

SUCS

CLK

t

SAMPLE

D

OUT

HI-Z

NULL

BIT

t

CONV

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

* After completing the data transfer, if further clocks are applied with CS
nitely.

: during this time, the bias current and the comparator powers down and the reference input becomes a

** t

DATA

high impedance node leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-2: Communication with MCP3001 (LSB first Format).

low, the A DC will output LSB first data,

t

CSH

Power Down

t

**

DATA

B4

B1 B2 B3

B5 B6 B7 B8 B9

low, the ADC will output zeros indefi-

HI-Z

© 2007 Microchip Technology Inc. DS21293C- page 15

MCP3001

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3001 with Microcontroller SPI Ports

With most microcontroller SPI ports, it is required to
clock out eight b its at a time. If this is the ca se, i t will b e
necessary to provide more clocks than are required for
the MCP3001. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3001 can be interfaced
to a microcontrolle r w ith a st a nda rd SPI port. Since the
MCP3001 always cl ocks dat a o ut on t he fall ing ed ge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3001. Figure 6-1 depicts the opera tion shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the ADC on the fall­ing edge of the third clock pulse. After the first eight
clocks have been sent to the device, the microcontrol-

CS

CLK 910111213141516

D

OUT

12345678

HI-Z

NULL

B9 B8 B7 B6

BIT

B4 B3 B2 B1 B0 B1 B2

B5

B5 B4 B3 B2 B1 B0 B1 B2B9 B8 B7 B6??0

ler’s receive buffer will contain two unknown bits (the
output is at high imped ance for the first two clocks ), the
null bit and the h ighest or der five bit s of the convers ion.
After the second eight clocks have been sent to the
device, the MCU re ceive regist er will cont ain the lowes t
order five bits and the B1-B4 bi ts repeated as the ADC
has begun to shift out LSB first data with the extra
clocks. Typical procedure would then call for the lower
order byte of data to be shifted right by three bits to
remove the extra B1-B4 bits. The B9-B5 bits are then
rotated 3 bits to the right with B7-B5 rotating from the
high order byte t o th e low e r ord er byt e. Easier manipu­lation of the converted data can be obtained by using
this method.

Figure 6-2 shows SPI Mode 1,1 communication which
requires that the clock idles in the high state. As with
mode 0,0, the ADC outputs data on the falling edge of
the clock and the MCU latc hes data from the ADC in on
the rising edge of the clock.

MCU latches data from ADC
on rising edges of SCLK

Data is clocked out of
ADC on falling edges

HI-Z

B3

B4

LSB first data begins
to come out

B3

Data stored into MCU receive register
after transmission of first 8 bits

Data stored into MCU receive register
after transmission of second 8 bits

FIGURE 6-1: SPI Communication with the MCP3001 using 8-bit segments (Mode 0,0: SCLK idles low).

CLK

D

CS

OUT

1234567

HI-Z

NULL

B9 B8 B7 B6

BIT

B9 B8 B7 B6??0

Data stored into MCU receive register
after transmission of first 8 bits

8

9101112131415 16

B4 B3 B2 B1 B0 B1 B2

B5

B4 B3 B2 B1 B0 B1 B2

B5

Data stored into MCU receive register
after transmission of second 8 bits

B3

B3

MCU latches data from ADC
on rising edges of SCLK

Data is clocked out of
ADC on falling edges

HI-Z

LSB first data begins
to come out

FIGURE 6-2: SPI Communication with the MCP3001 using 8-bit segments (Mode 1,1: SCLK idles high).

DS21293C-page 16 © 2007 Microchip Technology Inc.

MCP3001

6.2 Maintaining Minimum Clock Speed

When the MCP3001 i nitiates the sample period , charge
is stored on the sample capacitor. When the sample
period is complete, the dev ice convert s one bit for each
clock that is receiv ed. It is im portan t for the u ser to no te
that a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. At
85°C (worst case condition), the part will maintain
proper charge on the sample cap for 700 µs at

= 2.7V and 1.5 ms at VDD= 5V. This means that at

V

DD

= 2.7V, the time it takes to transmit the first 14

V

DD

clocks must not exceed 700 µs. Failure to mee t this c ri­terion may induce linearity errors into the conversion
outside the rated specifications.

6.3 Buffering/Filtering the Analog Inputs

If the signal so urce for th e ADC i s not a low imped ance
source, it will have t o be bu ffe red or inac curate conv er­sion results may occur. See Figure 4-2. It is also rec­ommended that a filter b e used to elim inate a ny sig nals
that may be aliased back into the conversion results.
This is illustrated in Figure 6-3 where an op amp is
used to drive, filter and gain the analog input of the
MCP3001. This amplifier provides a low impedance
source for the converter input and a low pass filter,
which eliminates unwanted high frequency noise.

Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistor values, as well as
determine the numbe r of po les th at are require d for th e
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog

Filters for Data Acquisition Systems.”

6.4 Layout Considerations

When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be us ed w ith thi s de vic e and shou ld be p lac ed
as close as possi ble to the device p in. A byp ass cap ac­itor value of 1 µF is recommended.

Digital and an alog t races sh ould be separa ted as m uch
as possible on the board and no traces should run
underneath the devic e or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (s uch as clock lines) as far as possi­ble from analog traces.

Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing V
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using ADC, refer to AN-688 “Layout Tips for
12-Bit A/D Converter Applications”.

V

DD

Connection

Device 1

connections to

DD

Device 4

V

DD

4.096V

Reference

0.1 µF

C

R

1

V

IN

R

MCP1541

1

MCP601

2

C

2

+

-

R

4

R

3

10 µF

C

L

V

IN+

MCP3001

IN-

REF

10 µF

1µF

FIGURE 6-4: V
configuration in order to reduce errors caused by
current return paths.

Device 2

traces arranged in a ‘Star’

DD

Device 3

FIGURE 6-3: The MCP601 operational amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3001.

© 2007 Microchip Technology Inc. DS21293C- page 17

MCP3001

ll

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

8-Lead PDIP (300 mil)

XXXXXXXX
XXXXXNNN

YYWW

8-Lead SOIC (150 mil)

XXXXXXXX

XXXXYYWW

NNN

8-Lead MSOP

XXXXXX

YWWNNN

8-Lead TSSOP

Example:

MCP3001
I/PNNN

0736

Example:

MCP3001

3

e

ISN

Example:

Example:

3

e

0736

NNN

3001I

725NNN

3

e

XXXX

YYWW

NNN

3001

0716
NNN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

3

e

Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )

3

e

can be found on the outer packaging for this package.

Note: In the event the full Microchip par t number cannot be marked on one li ne, it wi

be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

3

e

DS21293C-page 18 © 2007 Microchip Technology Inc.

MCP3001

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

N

1
2
3
4

B

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

otes:

. Pin 1 visual index feature may vary, but must be located with the hatched area.
. § Significant Characteristic.
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

NOTE 1

12

D

A

A1

b1

b

Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430

E1

3

E

A2

L

e

eB

Units INCHES

Microchip Technology Drawing C04-018

c

© 2007 Microchip Technology Inc. DS21293C- page 19

MCP3001

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

N

1
2
3
4

B

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

e

N

E

E1

NOTE 1

12 3

b

h

h

α

φ

A

A1

A2

L

L1

β

c

Units MILLMETERS

Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff

§

A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.
. § Significant Characteristic.
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimen sion, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-057

DS21293C-page 20 © 2007 Microchip Technology Inc.

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

N

1
2
3

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

B

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

2

1

e

MCP3001

b

A

A1

Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A – – 1.10
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 – 0.15
Overall Width E 4.90 BSC
Molded Package Width E1 3.00 BSC
Overall Length D 3.00 BSC
Foot Length L 0.40 0.60 0. 80
Footprint L1 0.95 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.08 – 0.23
Lead Width b 0.22 – 0.40

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimen sion, usually without tolerance, for information purposes only.

A2

Dimension Limits MIN NOM MAX

c

L1

Units MILLIMETERS

Microchip Technology Drawing C04-111

φ

L

© 2007 Microchip Technology Inc. DS21293C- page 21

MCP3001

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

N

1
2
3

B

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

12

b

e

c

A

A1

Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 – 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 2.90 3.00 3.10
Foot Length L 0.45 0.60 0. 75
Footprint L1 1.00 REF
Foot Angle φ 0° – 8°
Lead Thickness c 0.09 – 0.20
Lead Width b 0.19 – 0.30

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimen sion, usually without tolerance, for information purposes only.

A2

L1

Units MILLIMETERS

Dimension Limits MIN NOM MAX

L

φ

Microchip Technology Drawing C04-086

DS21293C-page 22 © 2007 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision C (January 2007)

This revision includes updates to the packaging
diagrams.

MCP3001

© 2007 Microchip Technology Inc. DS21293C-page 23

NOTES:

DS21293C-page 24 © 2007 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX

Device

Range

Device: MCP3001: 10-Bit Serial A/D Converter

MCP3001T: 10-Bit Serial A/D Converter

Temperature Range: I = -40°C to +85°C

PackageTemperature

(Tape and Reel) (SOIC and TSSOP only)

Examples:

a) MCP3001-I/P: Industrial Temperature,

PDIP package.

b) MCP3001 -I/SN: Industrial Temperature,

SOIC package.

c) MCP3001-I/ST: Industrial Temperature,

TSSOP package.

d) MCP3001 -I/MS: Industrial Temperature,

MSOP package.

MCP3001

Package: P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead

© 2007 Microchip Technology Inc. DS21293C-page25

MCP3001

NOTES:

DS21293C-page26 © 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protect ion f eatures of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Mill ennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and t he lik e is provided only for your convenience
and may be su perseded by upda t es . It is y our responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE

. Microchip disclaims all liability

arising from this information and its use. Use of Microchip
devices in life supp ort and/or safety ap plications is entir ely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless M icrochip from any and all dama ges, claims,
suits, or expenses re sulting from such use. No licens es are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, Pow e rTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartT el, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology I ncorporated in the U.S.A. and other
countries.

SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC
MCUs and dsPIC DSCs, KEELOQ
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

®

code hopping devices, Serial

© 2007 Microchip Technology Inc. DS21293C-page 27

®

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12/08/06

DS21293C-page 28 © 2007 Microchip Technology Inc.