Datasheet MCP23017, MCP23S17 Datasheet

MCP23017/MCP23S17

QFN

2
3
4
5
6

1

7

V

SS

NC

15

16

17

18

19

20

21

GPA4
GPA3
GPA2
GPA1
GPA0

V

DD

INTB

SCL

SDA

NC

A0A1A2

RESET

232425262728 22

GPB3

GPB2

GPB1

GPB0

GPA7

GPA6

GPA5

10118 9 121314

MCP23017

GPB5

GPB6
GPB7

GPB4

INTA

GPB0
GPB1
GPB2
GPB3

INTA

GPB4

NC

NC

GPB5
GPB6
GPB7

SCL

GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0

V

DD

VSS

A2
A1
A0

SDA

• 1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

PDIP,

MCP23017

INTB

RESET

SSOP

SOIC,

GPB0
GPB1
GPB2
GPB3

INTA

GPB4

SO

CS

GPB5
GPB6
GPB7

SCK

GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0

V

DD

VSS

A2
A1
A0

SI

• 1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

MCP23S17

INTB
RESET

MCP23S17

MCP23017

QFN

2
3
4
5
6

1

7

V

SS

CS

15

16

17

18

19

20

21 GPA4

GPA3
GPA2
GPA1
GPA0

V

DD

INTB

SI

SO

A0A1A2

RESET

232425262728 22

GPB3

GPB2

GPB1

GPB0

GPA7

GPA6

GPA5

10118 9 121314

MCP23S17

GPB5

GPB6
GPB7

GPB4

INTA

SCK

PDIP,

SSOP

SOIC,

16-Bit I/O Expander with Serial Interface

Features

• 16-bit remote bidirectional I/O port

- I/O pins default to input

• High-speed I

- 100 kHz

- 400 kHz

-1.7MHz

• High-speed SPI interface (MCP23S17)

- 10 MHz (max.)

• Three hardware address pins to allow up to eight
devices on the bus

• Configurable interrupt output pins

- Configurable as active-high, active-low or

open-drain

• INTA and INTB can be configured to operate
independently or together

• Configurable interrupt source

- Interrupt-on-change from configured register

defaults or pin changes

• Polarity Inversion register to configure the polarity
of the input port data

• External Reset input

• Low standby current: 1 µA (max.)

• Operating voltage:

- 1.8V to 5.5V @ -40°C to +85°C

- 2.7V to 5.5V @ -40°C to +85°C

- 4.5V to 5.5V @ -40°C to +125°C

2

C™ interface (MCP23017)

Package Types

Packages

• 28-pin PDIP (300 mil)

• 28-pin SOIC (300 mil)

• 28-pin SSOP

• 28-pin QFN

© 2007 Microchip Technology Inc. DS21952B-page 1

MCP23017/MCP23S17

GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0

I2C™

Control

GPIO

SCL

SDA

RESET

INTA

16

Configuration/

8

A2:A0

3

Control

Registers

SPI

SI

SO

SCK

CS

MCP23S17

MCP23017

GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0

INTB

Interrupt

GPIO

Serializer/
Deserializer

Logic

Decode

Functional Block Diagram

DS21952B-page 2 © 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.0 DEVICE OVERVIEW

The MCP23017/MCP23S17 (MCP23X17) device
family provides 16-bit, general purpose parallel I/O
expansion for I
devices differ only in the serial interface.

• MCP23017 – I

• MCP23S17 – SPI interface

The MCP23X17 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits (IODIRA/B).
The data for each input or output is kept in the
corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity
Inversion register. All registers can be read by the
system master.

The 16-bit I/O port functionally consists of two 8-bit
ports (PORTA and PORTB). The MCP23X17 can be
configured to operate in the 8-bit or 16-bit modes via
IOCON.BANK.

2

C bus or SPI applications. The two

2

C interface

There are two interrupt pins, INTA and INTB, that can
be associated with their respective ports, or can be
logically OR’ed together so that both pins will activate if
either port causes an interrupt.

The interrupt output can be configured to activate
under two conditions (mutually exclusive):

1. When any input state differs from its
corresponding Input Port register state. This is
used to indicate to the system master that an
input state has changed.

2. When an input state differs from a preconfigured
register value (DEFVAL register).

The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.

The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.

The hardware address pins are used to determine the
device address.

© 2007 Microchip Technology Inc. DS21952B-page 3

MCP23017/MCP23S17

1.1 Pin Descriptions

TABLE 1-1: PINOUT DESCRIPTION

Pin

Name

GPB0 1 25 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPB1 2 26 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPB2 3 27 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPB3 4 28 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPB4 5 1 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPB5 6 2 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPB6 7 3 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPB7 8 4 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

V

DD

V

SS

NC/CS
SCL/SCK 12 8 I Serial clock input
SDA/SI 13 9 I/O Serial data I/O (MCP23017), Serial data input (MCP23S17)
NC/SO 14 10 O NC (MCP23017), Serial data out (MCP23S17)
A0 15 11 I Hardware address pin. Must be externally biased.
A1 16 12 I Hardware address pin. Must be externally biased.
A2 17 13 I Hardware address pin. Must be externally biased.
RESET
INTB 19 15 O Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
INTA 20 16 O Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.
GPA0 21 17 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPA1 22 18 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPA2 23 19 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPA3 24 20 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPA4 25 21 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPA5 26 22 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPA6 27 23 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

GPA7 28 24 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up

PDIP/
SOIC/
SSOP

QFN

95PPower
10 6 P Ground
11 7 I NC (MCP23017), Chip Select (MCP23S17)

18 14 I Hardware reset. Must be externally biased.

Pin

Typ e

Function

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

resistor.

DS21952B-page 4 © 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.2 Power-on Reset (POR)

The on-chip POR circuit holds the device in reset until

DD has reached a high enough voltage to deactivate

V
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in Section 2.0
“Electrical Characteristics”.

When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.

1.3 Serial Interface

This block handles the functionality of the I2C
(MCP23017) or SPI (MCP23S17) interface protocol.
The MCP23X17 contains 22 individual registers (11
register pairs) that can be addressed through the Serial
Interface block, as shown in Table 1-2.

TABLE 1-2: REGISTER ADDRESSES

Address

IOCON.BANK = 1

00h 00h IODIRA
10h 01h IODIRB
01h 02h IPOLA
11h 03h IPOLB
02h 04h GPINTENA
12h 05h GPINTENB
03h 06h DEFVALA
13h 07h DEFVALB
04h 08h INTCONA
14h 09h INTCONB
05h 0Ah IOCON
15h 0Bh IOCON
06h 0Ch GPPUA
16h 0Dh GPPUB
07h 0Eh INTFA
17h 0Fh INTFB
08h 10h INTCAPA
18h 11h INTCAPB
09h 12h GPIOA
19h 13h GPIOB
0Ah 14h OLATA
1Ah 15h OLATB

Address

IOCON.BANK = 0

Access to:

1.3.1 BYTE MODE AND SEQUENTIAL
MODE

The MCP23X17 family has the ability to operate in Byte
mode or Sequential mode (IOCON.SEQOP).

Byte Mode disables automatic Address Pointer
incrementing. When operating in Byte mode, the
MCP23X17 family does not increment its internal
address counter after each byte during the data
transfer. This gives the ability to continually access the
same address by providing extra clocks (without
additional control bytes). This is useful for polling the
GPIO register for data changes or for continually
writing to the output latches.

A special mode (Byte mode with IOCON.BANK = 0)
causes the address pointer to toggle between
associated A/B register pairs. For example, if the BANK
bit is cleared and the Address Pointer is initially set to
address 12h (GPIOA) or 13h (GPIOB), the pointer will
toggle between GPIOA and GPIOB. Note that the
Address Pointer can initially point to either address in
the register pair.

Sequential mode enables automatic address pointer
incrementing. When operating in Sequential mode, the
MCP23X17 family increments its address counter after
each byte during the data transfer. The Address Pointer
automatically rolls over to address 00h after accessing
the last register.

These two modes are not to be confused with single
writes/reads and continuous writes/reads that are
serial protocol sequences. For example, the device
may be configured for Byte mode and the master may
perform a continuous read. In this case, the
MCP23X17 would not increment the Address Pointer
and would repeatedly drive data from the same
location.

1.3.2 I2C INTERFACE

1.3.2.1 I

The I2C write operation includes the control byte and
register address sequence, as shown in the bottom of

Figure 1-1. This sequence is followed by eight bits of

data from the master and an Acknowledge (ACK) from
the MCP23017. The operation is ended with a Stop (P)
or Restart (SR) condition being generated by the
master.

Data is written to the MCP23017 after every byte
transfer. If a Stop or Restart condition is generated
during a data transfer, the data will not be written to the
MCP23017.

Both “byte writes” and “sequential writes” are
supported by the MCP23017. If Sequential mode is
enabled (IOCON, SEQOP = 0) (default), the
MCP23017 increments its address counter after each
ACK during the data transfer.

2

C Write Operation

© 2007 Microchip Technology Inc. DS21952B-page 5

MCP23017/MCP23S17

1.3.2.2 I2C Read Operation

I2C Read operations include the control byte sequence,
as shown in the bottom of Figure 1-1. This sequence is
followed by another control byte (including the Start
condition and ACK) with the R/W bit set (R/W = 1). The
MCP23017 then transmits the data contained in the
addressed register. The sequence is ended with the
master generating a Stop or Restart condition.

1.3.2.3 I2C Sequential Write/Read

For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 1.3.1 “Byte Mode
and Sequential Mode” for details regarding sequential
operation control).

The sequence ends with the master sending a Stop or
Restart condition.

The MCP23017 Address Pointer will roll over to
address zero after reaching the last register address.

Refer to Figure 1-1.

1.3.3 SPI INTERFACE

1.3.3.1 SPI Write Operation

The SPI write operation is started by lowering CS. The
Write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.

1.3.3.2 SPI Read Operation

The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.

1.3.3.3 SPI Sequential Write/Read

For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the Address Pointer. (see Section 1.3.1
“Byte Mode and Sequential Mode” for details
regarding sequential operation control).

The sequence ends by the raising of CS
The MCP23S17 Address Pointer will roll over to

address zero after reaching the last register address.

.

DS21952B-page 6 © 2007 Microchip Technology Inc.

MCP23017/MCP23S17

S

P

SR

w

R

OP

ADDR

DOUT

DIN

- Start

- Restart

- Stop

- Write

- Read

- Device opcode

- Device register address

- Data out from MCP23017

- Data in to MCP23017

S

P

SR

W

R

OP ADDR

DIN DIN

....

S

P

W

R

OP

ADDR

D

OUT

DOUT

....

P

SR WOP

D

IN

DIN

....

P

P

SR R

DOUT DOUT

....

P

OP

D

OUT

DOUT

....

P

SR OP

DIN

....

P

OP

D

IN

S PWOP ADDR

DIN

DIN

....

Byte and Sequential Write

S

W

OP SR R

OP

D

OUT

DOUT

....

P

Byte and Sequential Read

S WOP ADDR

DIN

P

S

W

OP SR ROP

D

OUT

P

Byte

Sequential

Byte

Sequential

FIGURE 1-1: MCP23017 I2C™ DEVICE PROTOCOL

© 2007 Microchip Technology Inc. DS21952B-page 7

MCP23017/MCP23S17

S 0 1 0 0 A2A1A0R/WACK

Start
bit

Slave Address

R/W bit
ACK bit

Control Byte

R/W = 0 = write
R/W = 1 = read

0 1 0 0 A2 A1 A0 R/W

Slave Address

R/W bit

Control Byte

R/W = 0 = write
R/W = 1 = read

CS

S0100A2A1A00ACK* A7 A6 A5 A4 A3 A2 A1 A0 ACK*

Device Opcode

Register Address

R/W = 0

*The ACKs are provided by the MCP23017.

0100A2*A1*A0*R/WA7A6A5A4A3A2A1A0

Device Opcode

Register Address

CS

* Address pins are enabled/disabled via IOCON.HAEN.

1.4 Hardware Address Decoder

The hardware address pins are used to determine the
device address. To address a device, the correspond­ing address bits in the control byte must match the pin
state. The pins must be biased externally.

1.4.1 ADDRESSING I2C DEVICES
(MCP23017)

The MCP23017 is a slave I2C interface device that
supports 7-bit slave addressing, with the read/write bit
filling out the control byte. The slave address contains
four fixed bits and three user-defined hardware
address bits (pins A2, A1 and A0). Figure 1-2 shows
the control byte format.

1.4.2 ADDRESSING SPI DEVICES
(MCP23S17)

The MCP23S17 is a slave SPI device. The slave
address contains four fixed bits and three user-defined
hardware address bits (if enabled via IOCON.HAEN)
(pins A2, A1 and A0) with the read/write bit filling out
the control byte. Figure 1-3 shows the control byte
format. The address pins should be externally biased
even if disabled (IOCON.HAEN = 0).

FIGURE 1-2: I2C™ CONTROL BYTE

FORMAT

FIGURE 1-3: SPI CONTROL BYTE

FORMAT

FIGURE 1-4: I

2

C™ ADDRESSING REGISTERS

FIGURE 1-5: SPI ADDRESSING REGISTERS

DS21952B-page 8 © 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.5 GPIO Port

The GPIO module is a general purpose, 16-bit wide,
bidirectional port that is functionally split into two 8-bit
wide ports.

The GPIO module contains the data ports (GPIOn),
internal pull-up resistors and the output latches
(OLATn).

Reading the GPIOn register reads the value on the
port. Reading the OLATn register only reads the
latches, not the actual value on the port.

Writing to the GPIOn register actually causes a write to
the latches (OLATn). Writing to the OLATn register
forces the associated output drivers to drive to the level
in OLATn. Pins configured as inputs turn off the
associated output driver and put it in high-impedance.

TABLE 1-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1)

Register

Name

IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
IODIRB 10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLB 11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENB 12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPPUB 16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPIOB 19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATB 1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

Address

(hex)

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

POR/RST

value

TABLE 1-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK =

Register

Name

IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IODIRB 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 02 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
IPOLB 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPINTENB 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPPUA 0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPPUB 0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPIOA 12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
GPIOB 13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
OLATB 15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

Address

(hex)

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0)

POR/RST

value

© 2007 Microchip Technology Inc. DS21952B-page 9

MCP23017/MCP23S17

1.6 Configuration and Control

Registers

There are 21 registers associated with the MCP23X17,
as shown in Ta bl e 1 -5 and Ta bl e 1 -6 . The two tables
show the register mapping with the two BANK bit

are associated with PortB. One register (IOCON) is
shared between the two ports. The PortA registers are
identical to the PortB registers, therefore, they will be
referred to without differentiating between the port
designation (i.e., they will not have the “A” or “B”
designator assigned) in the register tables.

values. Ten registers are associated with PortA and ten

TABLE 1-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 1)

Register

Name

IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVALA 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCONA 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 05 BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL
GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTFA 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAPA 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
IODIRB 10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLB 11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENB 12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVALB 13 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCONB 14 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 15 BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL — 0000 0000
GPPUB 16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTFB 17 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAPB 18 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIOB 19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATB 1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

Address

(hex)

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

— 0000 0000

POR/RST

value

DS21952B-page 10 © 2007 Microchip Technology Inc.

MCP23017/MCP23S17

TABLE 1-6: CONTROL REGISTER SUMMARY (IOCON.BANK = 0)

Register

Name

IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IODIRB 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 02 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
IPOLB 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
GPINTENB 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVALA 06 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
DEFVALB 07 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCONA 08 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
INTCONB 09 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 0A BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL
IOCON 0B BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL — 0000 0000
GPPUA 0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
GPPUB 0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTFA 0E INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTFB 0F INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAPA 10 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
INTCAPB 11 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIOA 12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
GPIOB 13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
OLATB 15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000

Address

(hex)

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

— 0000 0000

POR/RST

value

© 2007 Microchip Technology Inc. DS21952B-page 11

MCP23017/MCP23S17

1.6.1 I/O DIRECTION REGISTER

Controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an

input. When a bit is clear, the corresponding pin
becomes an output.

REGISTER 1-1: IODIR – I/O DIRECTION REGISTER (ADDR 0x00)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 IO7:IO0: These bits control the direction of data I/O <7:0>

1 = Pin is configured as an input.
0 = Pin is configured as an output.

DS21952B-page 12 © 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.6.2 INPUT POLARITY REGISTER

This register allows the user to configure the polarity on
the corresponding GPIO port bits.

If a bit is set, the corresponding GPIO register bit will
reflect the inverted value on the pin.

REGISTER 1-2: IPOL – INPUT POLARITY PORT REGISTER (ADDR 0x01)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 IP7:IP0: These bits control the polarity inversion of the input pins <7:0>

1 = GPIO register bit will reflect the opposite logic state of the input pin.
0 = GPIO register bit will reflect the same logic state of the input pin.

© 2007 Microchip Technology Inc. DS21952B-page 13

MCP23017/MCP23S17

1.6.3 INTERRUPT-ON-CHANGE
CONTROL REGISTER

The GPINTEN register controls the interrupt-on­change feature for each pin.

If a bit is set, the corresponding pin is enabled for
interrupt-on-change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for interrupt-on-change.

REGISTER 1-3: GPINTEN – INTERRUPT-ON-CHANGE PINS (ADDR 0x02)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 GPINT7:GPINT0: General purpose I/O interrupt-on-change bits <7:0>

1 = Enable GPIO input pin for interrupt-on-change event.
0 = Disable GPIO input pin for interrupt-on-change event.

Refer to INTCON and GPINTEN.

DS21952B-page 14 © 2007 Microchip Technology Inc.

MCP23017/MCP23S17

1.6.4 DEFAULT COMPARE REGISTER
FOR INTERRUPT-ON-CHANGE

The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
interrupt to occur.

REGISTER 1-4: DEFVAL – DEFAULT VALUE REGISTER (ADDR 0x03)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from

defaults <7:0>. Refer to INTCON.
If the associated pin level is the opposite from the register bit, an interrupt occurs.

Refer to INTCON and GPINTEN.

© 2007 Microchip Technology Inc. DS21952B-page 15