Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1995
10/95
! !
! "
High–Performance Silicon–Gate CMOS
The MC54/74HC158 is identical in pinout to the LS158. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These devices route 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in inverted
form for the HC158. A high level on the Output Enable input sets all four Y
outputs to a high level for the HC158.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V
• Low Input Current: 1µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 74 FETs or 18.5 Equivalent Gates
LOGIC DIAGRAM
Select
Nibble
A Inputs
Pin 16 = VCC
Pin 8 = GND
1
A3
14
A2
11
A1
5
A0
2
Y3
12
Y2
9
Y1
7
Y0
4
Output
Enable
15
Data
Outputs
Nibble
B Inputs
B3
13
B2
10
B1
6
B0
3
1516 14 13 12 11 10
21 3 4 5 6 7
V
CC
9
8
Output
Enable
A3 B3 Y3 A2 B2 Y2
Select A0 B0 Y0 A1 B1 Y1 GND
Pinout: 16–Lead Plastic Package (Top View)
X = Don’t Care
A0–A3, B0–B3 = the levels of the respec-
tive Data–Word inputs.
H
L
L
X
L
H
FUNCTION TABLE
Inputs Outputs
Output
Enable
Select
H
A0
–A3
B0–B3
Y0–Y3
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
Page 2
MC54/74HC158
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 2) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol Parameter Condition
V
CC
V
–55 to 25°C ≤85°C ≤125°C Unit
V
IH
Minimum High–Level Input Voltage V
out
= 0.1V or VCC –0.1V
|I
out
| ≤ 20µA
2.0
4.5
6.0
1.50
3.15
4.20
1.50
3.15
4.20
1.50
3.15
4.20
V
V
IL
Maximum Low–Level Input Voltage V
out
= 0.1V or VCC – 0.1V
|I
out
| ≤ 20µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| ≤ 20µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or VIL|I
out
| ≤ 4.0mA
|I
out
| ≤ 5.2mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
OL
Maximum Low–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| ≤ 20µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| ≤ 4.0mA
|I
out
| ≤ 5.2mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0µA
6.0 8 80 160 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Page 3
MC54/74HC158
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
AC CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol Parameter
V
CC
V
–55 to 25°C ≤85°C ≤125°C Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Select to Output Y
(Figures 3 and 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 5)
2.0
4.5
6.0
115
23
20
145
29
25
175
35
30
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 2 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
35
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
Figure 1. Figure 2. Y versus Select, Inverted
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3. Figure 4. Test Circuit
V
CC
GND
Output Enable
Output Y
t
PLH
t
PHL
90%
50%
10%
t
r
t
TLH
t
f
t
THL
90%
50%
10%
V
CC
GND
Input Aor B
Output Y
t
PHL
t
PLH
90%
50%
10%
t
r
t
THL
t
f
t
TLH
90%
50%
10%
V
CC
GND
Select
Output Y
t
PHL
t
PLH
90%
50%
10%
t
r
t
THL
t
f
t
TLH
90%
50%
10%
Page 4
MC54/74HC158
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
PIN DESCRIPTIONS
INPUTS
A0–A3 (Pins 2,5,11,14)
Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158.
B0–B3 (Pins 3,6,10,13)
Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158.
OUTPUTS
Y0–Y3 (Pins 4,7,9,12)
Data outputs. The selected input nibble is presented at
these outputs when the Output Enable input is at a low level.
The data present on these pins is in its inverted form for the
HC158. For the Output Enable input at a high level, the outputs
are at a high level for the HC158.
CONTROL INPUTS
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects the
A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on thisinput allows the
selected data to be presented at the outputs. A high level on
this input sets all of the outputs to a high level for the HC158.
Figure 5. Expanded Logic Diagram
2
A0
4
Y0
7
Y1
9
Y2
12
Y3
3
B0
5
A1
6
B1
11
A2
10
B2
14
A3
13
B3
15
Output Enable
1
Select
Data
Outputs
Nibble
Inputs
Page 5
MC54/74HC158
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
19.05
6.10
—
0.39
1.40
0.21
3.18
19.93
7.49
5.08
0.50
1.65
0.38
4.31
0
°
0.51
15
°
1.01
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
0.750
0.240
—
0.015
0.055
0.008
0.125
0.785
0.295
0.200
0.020
0.065
0.015
0.170
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
0
°
0.020
15
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
1 8
916
-A-
-B-
C
KN
G
E
F
D 16 PL
-T-
SEATING
PLANE
M
L
J
16 PL
0.25 (0.010) T A
M
S
0.25 (0.010) T B
M
S
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
-A-
B
1 8
916
F
H
G
D
16 PL
S
C
-T-
SEATING
PLANE
K
J
M
L
T A0.25 (0.010)
M M
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
916
-A-
-B-
D
16 PL
K
C
G
-T-
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
Page 6
MC54/74HC158
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
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MC54/74HC158/D
*MC54/74HC158/D*
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