Datasheet MC74HC154DW, MC74HC154N Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

 

High–Performance Silicon–Gate CMOS

The MC54/74HC154 is identical in pinout to the LS154. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.

This device, when enabled, selects one of 16 active–low outputs. Two
active–low Chip Selects are provided to facilitate the chip–select, demulti­plexing, a nd cascading f unctions. When either Chip Select is h igh, all
outputs are high. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output. Then, while holding one
chip select input low, data can be applied to the other chip select input (see
Application Note).

The HC154 is primarily used for memory address decoding and data
routing applications.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 192 FETs or 48 Equivalent Gates

LOGIC DIAGRAM

Y0
Y1

Y2
Y3
Y4

Y5
Y6
Y7
Y8
Y9
Y10

Y11
Y12
Y13

Y14
Y15

A0
A1
A2
A3

CS1
CS2

18
19

23
22

21
20

1
2
3
4
5
6
7
8
9

10

13
14
15
16
17

BINARY

ADDRESS

INPUTS

CHIP

SELECT

INPUTS

ACTIVE–LOW
OUTPUTS

PIN 24 = V

CC

PIN 12 = GND

11



PIN ASSIGNMENT

Y5

Y3

Y2

Y1

Y0

Y7

Y6

Y4 A3

A2

A1

A0

V

CC

Y13

Y14

Y15

Y11

Y12

CS1

CS2

Y10

GND

Y9

Y8

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

13

11
12

21

22

23

24

ORDERING INFORMATION

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW

Ceramic
Plastic
SOIC

N SUFFIX

PLASTIC PACKAGE

CASE 724–03

J SUFFIX

CERAMIC PACKAGE

CASE 758–02

DW SUFFIX

SOIC PACKAGE

CASE 751E–04

1

24

1

24

1

24

MC54/74HC154

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP)

(Ceramic DIP or SOIC Package)

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 2) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_C

v

125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

V

OH

V

OL

Minimum High–Level Output
Voltage

Maximum Low–Level Output
Voltage

V

V

MC54/74HC154

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_C

v

125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 3)

2.0

4.5

6.0

190

38
32

240

48
41

285

57
48

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, CS to Output Y

(Figures 2 and 3)

2.0

4.5

6.0

175

35
30

220

44
37

265

53
45

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 2 and 3)

2.0

4.5

6.0

75
15
13

95
19
16

110

22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

80

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

PIN DESCRIPTIONS

INPUTS
A0, A1, A2, A3 (Pins 23, 22, 21, 20)

Address inputs. These inputs, when the 1–of–16 decoder
is enabled, determine which of its sixteen active–low outputs
is selected.

OUTPUTS
Y0 – Y15 (Pins 1 – 11, 13 – 17)

Active–low outputs. These outputs assume a low level

when addressed and both chip–select inputs are active.
These outputs remain high when not addressed or a chip–
select input is high.

CONTROL INPUTS
CS1, CS2 (Pins 18, 19)

Active–low chip–select inputs. With low levels on both of
these inputs, the outputs of the decoder follow the Address
inputs. A high level on either input forces all outputs high.

FUNCTION TABLE

Inputs Outputs

CS1 CS2 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

L
L
L
L
L
L
L

L
H
H
H
H
H
H
H
H

L
L
L

L
H
H
H
H

L

L

L

L
H
H
H
H

L

L
H
H

L

L
H
H

L

L
H
H

L

L
H
H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H

L
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H

L
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H

L
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H

L
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H

L
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H

L
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H

L
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H

L
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H

L
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H

L
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H

L

H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

L

L
H
H

H

L

H

X
X
X

X
X
X

X
X
X

X
X
X

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H = High Level, L = Low Level, X = Don’t Care

C

PD

Power Dissipation Capacitance (Per Package)*

pF

MC54/74HC154

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

SWITCHING WAVEFORMS

INPUT A

OUTPUT Y

50%

50%

V

CC

GND

t

PHL

t

PLH

t

f

t

r

CS1 OR CS2

t

TLH

t

THL

90%

50%

10%

Figure 1.

Figure 2.

TYPICAL APPLICATIONS

Y0

A0
A1
A2

A3

STROBE

1 OF 16 DECODER
SELECTED OUTPUT IS LOW

DATA INPUT

1 OF 16 DEMULTIPLEXER
SELECTED OUTPUT’S LOGIC LEVEL
FOLLOWS LOGIC LEVEL ON DATA INPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 3. Test Circuit

VALID VALID

V

CC

GND

OUTPUT Y

t

PHL

t

PLH

90%

50%

10%

CS1
CS2

CS1
CS2

A0
A1
A2

A3

Y15

Y0

Y15

MC54/74HC154

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

CS1
CS2

A0

A1

A2

A3

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

1

2

3

4

5

6

7

8

9

10

11

13

14

15

16

17

18
19

23

22

21

20

EXPANDED LOGIC DIAGRAM

MC54/74HC154

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 758–02

ISSUE A

NOTES:

1. CHAMFERED CONTOUR OPTIONAL.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

4. CONTROLLING DIMENSION: INCH.

–A–

–B–

24 13

12

1

–T–

SEATING
PLANE

24 PL

K

E

F

N

C

D

G

M

A

M

0.25 (0.010) T

24 PLJ

M

B

M

0.25 (0.010) T

L

M

NOTE 1

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 1.230 1.265 31.25 32.13
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.020 0.38 0.51
E 0.050 BSC 1.27 BSC
F 0.040 0.060 1.02 1.52
G 0.100 BSC 2.54 BSC
J 0.007 0.012 0.18 0.30
K 0.110 0.140 2.80 3.55
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01

_ _ _ _

N SUFFIX

PLASTIC PACKAGE

CASE 724–03

ISSUE D

C

N

K

F

G

B

1

24

12

13

L P

J

SEATING
PLANE

DIMAMIN MAX MIN MAX

MILLIMETERS

1.240 1.285 31.50 32.64

INCHES

B 0.285 0.305 7.24 7.75
C 0.160 0.200 4.07 5.08
D 0.015 0.021 0.38 0.53
F 0.045 0.062 1.14 1.57
G 0.100 BSC 2.54 BSC
J 0.008 0.013 0.20 0.33
K 0.100 0.165 2.54 4.19
L 0.300 0.310 7.62 7.87
N 0.020 0.050 0.51 1.27
P 0.360 0.400 9.14 10.16

NOTES:

3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

4. CONTROLLING DIMENSION: INCH.

5. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

0.25 (0.010)MT A

M

D 24 PL

–T–

–A–

MC54/74HC154

High–Speed CMOS Logic Data
DL129 — Rev 6

7 MOTOROLA

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751E–04

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

–A–

–B–

P

12X

D24X

12

1324

1

M

0.010 (0.25) B

M

S

A

M

0.010 (0.25) B

S

T

–T–

G

22X

SEATING
PLANE

K

C

R

X 45

_

M

F

J

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 15.25 15.54 0.601 0.612
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
J 0.23 0.32 0.009 0.013

K 0.13 0.29 0.005 0.011
M 0 8 0 8
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

____

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