Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
"
!
High–Performance Silicon–Gate CMOS
The MC74HC137 is identical in pinout to the LS137. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC137 decodes a three–bit Address to one–of–eight active–low
outputs. The device has a transparent latch for storage of the Address. Two
Chip Selects, one active–low and one active–high, are provided to facilitate
the demultiplexing, cascading, and chip–selecting functions.
The demultiplexing function is accomplished by using the Address inputs
to select t he desired device output, a nd then by using one of the Chip
Selects as a data input while holding the other one active.
The HC137 is the inverting version of the HC237.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 152 FETs or 38 Equivalent Gates
LOGIC DIAGRAM
5
7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
9
10
11
12
13
14
15
6
4
2
1
CS1
CS2
A0
A1
A2
LATCH ENABLE
ADDRESS
INPUTS
PIN 16 = V
CC
PIN 8 = GND
CHIP–
SELECT
INPUTS
TRANS–
PARENT
LATCH
1–OF–8
DECODER
ACTIVE–
LOW
OUTPUTS
3
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
A0
LATCH ENABLE
A2
A1
Y7
CS1
CS2
GND
Y3
Y2
Y1
Y0
V
CC
Y5
Y4
Y6
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
1
16
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
Inputs Outputs
LE CS1 CS2 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H X X X H H H H H H H H
X L X X X X H H H H H H H H
L H L L L L L H H H H H H H
L H L L L H H L H H H H H H
L H L L H L H H L H H H H H
L H L L H H H H H L H H H H
L H L H L L H H H H L H H H
L H L H L H H H H H H L H H
L H L H H L H H H H H H L H
L H L H H H H H H H H H H L
H H L X X X *
FUNCTION TABLE
*= Depends upon the Address previously applied while LE was
at a low level.
Page 2
MC74HC137
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur .
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 2) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
OL
Maximum Low–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Page 3
MC74HC137
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
PLH
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 6)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PHL
2.0
4.5
6.o
240
48
41
300
60
51
360
72
61
t
PLH
Maximum Propagation Delay, CS1 or CS2 to Output Y
(Figures 2, 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PHL
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
t
PLH
Maximum Propagation Delay, Latch Enable to Output Y
(Figures 4 and 6)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PHL
2.0
4.5
6.0
250
50
43
315
63
54
375
75
64
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 2 and 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
100
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input t
r
= tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
su
Minimum Setup Time, Input A to Latch Enable
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time, Latch Enable to Input A
(Figure 5)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
w
Minimum Pulse Width, Latch Enable
(Figure 4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, t
f
Maximum Input Rise and Fall Times
(Figure 2)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Page 4
MC74HC137
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is enabled,
determine which of the eight outputs is selected.
CONTROL INPUTS
CS1, CS2 (Pins 6, 5)
Chip–Select inputs. For CS1 at a high level and CS2 at a
low level, the chip is enabled and the outputs follow the address inputs (Latch Enable = L). For any other combination of
CS1 and CS2, the outputs are at a high level.
Latch Enable (Pin 4)
Latch–Enable input. A high level at this input latches the
Address. A low level at this input allows the outputs to follow
the data at the Address pins (CS1 = H and CS2 = L).
OUTPUTS
Y0 – Y7
Active–low outputs. One of these eight outputs is selected
when the chip is enabled (CS1 = H and CS2 = L) and the
data on the A0, A1, and A2 inputs correspond to that particular output. The selected output is at a low level while all
others remain at a high level.
SWITCHING WAVEFORMS
Figure 1.
50%
t
PHL
t
PLH
t
THL
t
TLH
V
CC
GND
Figure 2.
Figure 3. Figure 4.
Figure 5.
VALID VALID
INPUT A
OUTPUT Y
50%
V
CC
GND
t
r
t
f
t
PHL
t
PLH
OUTPUT Y
CS2
90%
50%
10%
90%
50%
10%
V
CC
GND
t
PHL
50%
t
PLH
50%
50%
t
w
OUTPUT Y
LATCH
ENABLE
t
r
V
CC
GND
t
PLH
t
TLH
90%
50%
10%
OUTPUT Y
CS1
t
PHL
90%
50%
10%
t
THL
LATCH
ENABLE
V
CC
GND
V
CC
GND
50%
50%
VALID
t
su
t
h
INPUT A
*Includes all probe and jig capacitance
Figure 6. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
t
f
Page 5
MC74HC137
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
A0
A1
A2
LATCH
ENABLE
CS1
CS2
1
2
3
4
6
5
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
EXPANDED LOGIC DIAGRAM
Page 6
MC74HC137
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
–A
–
B
1 8
916
F
H
G
D
16 PL
S
C
–T
–
SEATING
PLANE
K
J
M
L
T A0.25 (0.010)
M M
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
916
–A
–
–B
–
D 16 PL
K
C
G
–T
–
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
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MC74HC137/D
*MC74HC137/D*
◊
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