Page 1
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
1
August 23, 1993 853–1656 10584
FEATURES
•Two 8-bit octal transceivers with D-type
latch
•Live insertation/extraction permitted
•Power-up 3-State
•Power-up reset
•Multiple V
CC
and GND pins minimize
switching noise
•Back-to-back registers for storage
•Separate controls for data flow in each
direction
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
•ESD protection exceeds 2000V per MIL
STD 883 Method 3015 and 200V per
Machine Model
DESCRIPTION
The MB2543 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The MB2543 dual octal registered transceiver
contains two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate Latch Enable (nLEAB
,
nLEBA
) and Output Enable (nOEAB,
nOEBA
) inputs are provided for each
register to permit independent control of data
transfer in either direction. The outputs are
guaranteed to sink 64mA.
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
nAx to nBx
CL = 50pF; VCC = 5V 3.3 ns
C
IN
Input capacitance VI = 0V or V
CC
4 pF
C
I/O
I/O capacitance VO = 0V or V
CC;
3-State 7 pF
I
CCZ
Total supply current Outputs disabled; VCC = 5.5V 120 µA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
52-pin plastic Quad Flat Pack –40°C to +85°C MB2543BB 1418B
PIN CONFIGURATION LOGIC SYMBOL
Vcc
19 2220 231716 25 26241514 2118
2A6
2A7
GND
2EAB
2LEAB
2OEAB
2OEBA
2LEBA
2EBA
2B7
2B6
Vcc
Vcc
1A2
1A3
1A4
GND
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
1
2
3
4
5
6
7
8
9
10
11
12
13
47 4446 434950 41 40425152 4548
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
GND
2B3
2B4
2B5
39
38
37
36
35
34
33
32
31
30
29
28
27
MB2543
52-pin PQFP
1A1
1A0
1EAB
1LEAB
1OEAB
1OEBA
1LEBA
1EBA
GND
1B0
1B1
Vcc
42 41 39 38 37 36 35 34
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
50 51 1 2 3 5 6 7
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
49
44
1EAB
1EBA
48 1LEAB
45 1LEBA
471OEAB
461OEBA
33 32 31 29 28 27 25 24
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
8 9 10 11 12 13 15 16
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
18
23
2EAB
2EBA
19 2LEAB
22 2LEBA
202OEAB
212OEBA
Page 2
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
2
LOGIC DIAGRAM
D
LE
Q
D
LE
Q
DETAIL A
nB0
nB1nA1
nB2nA2
nB3nA3
nB4nA4
nB5nA5
nB6nA6
nB7nA7
DETAIL A X 7
nOEAB
nEAB
nLEAB
nOEBA
nEBA
nLEBA
nA0
LOGIC SYMBOL (IEEE/IEC)
42
41
39
38
37
36
35
34
&
&
&
&
50
51
1
2
3
5
6
7
47
49
48
46
44
45
EN1(AB)
EN2(BA)
∇ 1
&
&
&
&
8
9
10
11
12
13
15
16
20
18
19
21
23
22
EN1(AB)
EN2(BA)
33
32
31
29
28
27
25
24
∇ 1 2 ∇2 ∇
Page 3
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
3
FUNCTIONAL DESCRIPTION
The MB2543 contains two sets of eight
D-type latches, with separate control pins for
each set. Using data flow from A to B as an
example, when the A-to-B Enable (nEAB
)
input and the A-to-B Latch Enable (nLEAB
)
input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the
nLEAB
signal puts the A data into the latches
where it is stored and the B outputs no longer
change with the A inputs. With EAB
and
nOEAB
both Low, the 3-State B output
buffers are active and display the data
present at the outputs of the A latches.
Control of data flow from B to A is similar, but
using the nEBA
, nLEBA, and nOEBA inputs.
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
50, 51, 1, 2, 3, 5, 6, 7,
8, 9, 10, 11, 12, 13, 15, 16
1A0 – 1A7,
2A0 – 2A7
Data inputs/outputs
42, 41, 39, 38, 37, 36, 35, 34,
33, 32, 31, 29, 28, 27, 25, 24
1B0 – 1B7,
2B0 – 2B7
Data inputs/outputs
47, 46, 20, 21
1OEAB, 1OEBA,
2OEAB
, 2OEBA
A to B / B to A Output Enable inputs (active-Low)
49, 44, 18, 23
1EAB, 1EBA,
2EAB
, 2EBA
A to B / B to A Enable inputs (active-Low)
48, 45, 19, 22
1LEAB, 1LEBA,
2LEAB
, 2LEBA
A to B / B to A Latch Enable inputs (active-Low)
4, 17, 30, 43 GND Ground (0V)
14, 26, 40, 52 V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS OUTPUTS STATUS
nOEXX nEXX nLEXX nAx or nBx nBx or nAx
H X X X Z Disabled
X H X X Z Disabled
L
L
↑
↑
L
L
h
l
Z
Z
Disabled + Latch
L
L
L
L
↑
↑
h
l
H
L
Latch + Display
L
L
L
L
L
L
H
L
H
L
Transparent
L L H X NC Hold
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High transition of nLEXX
or nEXX (XX = AB or BA)
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High transition of nLEXX
or nEXX (XX = AB or BA)
X = Don’t care
↑ = Low-to-High transition of nLEXX
or nEXX (XX = AB or BA)
NC= No change
Z = High impedance or “off” state
Page 4
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
4
ABSOLUTE MAXIMUM RATINGS
1 , 2
SYMBOL
PARAMETER CONDITIONS RATING UNIT
V
CC
DC supply voltage –0.5 to +7.0 V
I
IK
DC input diode current VI < 0 –18 mA
V
I
DC input voltage
3
–1.2 to +7.0 V
I
OK
DC output diode current VO < 0 –50 mA
V
OUT
DC output voltage
3
output in Off or High state –0.5 to +5.5 V
I
OUT
DC output current output in Low state 128 mA
T
stg
Storage temperature range –65 to 150 °C
NOTES:
1 . Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2 . The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3 . The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
Min Max
V
CC
DC supply voltage 4.5 5.5 V
V
I
Input voltage 0 V
CC
V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level Input voltage 0.8 V
I
OH
High-level output current –32 mA
I
OL
Low-level output current 64 mA
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
Page 5
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS T
amb
= +25°C
T
amb
= –40°C
to +85°C
UNIT
MIN TYP MAX MIN MAX
V
IK
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
VCC = 4.5V; IOH = –3mA; VI = VIL or V
IH
2.5 2.9 2.5 V
V
OH
High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V
IH
3.0 3.4 3.0 V
VCC = 4.5V; IOH = –32mA; VI = VIL or V
IH
2.0 2.4 2.0 V
V
OL
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
IH
0.42 0.55 0.55 V
V
RST
Power-up output voltage
3
VCC = 5.5V; IO = 1mA; VI = GND or V
CC
0.13 0.55 0.55 V
I
I
Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA
I
OFF
Power-off leakage current VCC = 0.0V; V
O
or VI ≤ 4.5V ±5.0 ±100 ±100 µA
I
PU/PD
Power-up/down 3-State
output current
4
VCC = 2.1V; VO = 0.5V; VI = GND or VCC;
VOE = Don’t care
±5.0 ±50 ±50 µA
IIH + I
OZH
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
IH
5.0 50 50 µA
IIL + I
OZL
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
IH
–5.0 –50 –50 µA
I
CEX
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
CC
5.0 50 50 µA
I
O
Output current
1
VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA
I
CCH
VCC = 5.5V; Outputs High, VI = GND or V
CC
120 250 250 µA
I
CCL
Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V
CC
38 60 60 mA
I
CCZ
VCC = 5.5V; Outputs 3-State;
V
I
= GND or V
CC
120 250 250 µA
∆I
CC
Additional supply current per
input pin
2
VCC = 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.5 1.5 1.5 mA
NOTES:
1 . Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2 . This is the increase in supply current for each input at 3.4V.
3 . For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4 . This parameter is valid for any V
CC
between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transition time of up to 100µsec is permitted.
Page 6
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
6
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25oC
V
CC
= +5.0V
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V ±0.5V
UNIT
MIN TYP MAX MIN MAX
t
PLH
t
PHL
Propagation delay
nAx to nBx, nBx to nAx
2
1.5
1.6
3.2
3.3
4.6
4.6
1.5
1.6
5.2
5.2
ns
t
PLH
t
PHL
Propagation delay
LEBA
to nAx, LEAB to nBx
1, 2
1.9
2.1
3.9
4.1
5.3
5.5
1.9
2.1
6.1
6.2
ns
t
PZH
t
PZL
Output enable time
OEBA
to nAx, OEAB to nBx
4
5
1.6
2.3
3.6
4.5
5.0
5.9
1.6
2.3
5.8
6.6
ns
t
PHZ
t
PLZ
Output disable time
OEBA to nAx, OEAB to nBx
4
5
1.0
1.4
3.6
3.2
5.0
4.6
1.0
1.4
5.7
5.2
ns
t
PZH
t
PZL
Output enable time
EBA
to nAx, EAB to nBx
4
5
1.6
2.3
3.6
4.5
5.0
5.9
1.6
2.3
5.8
6.6
ns
t
PHZ
t
PLZ
Output disable time
EBA
to nAx, EAB to nBx
4
5
1.0
1.4
3.6
3.2
5.0
4.6
1.0
1.4
5.7
5.2
ns
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25oC
V
CC
= +5.0V
T
amb
= -40 to +85oC
V
CC
= +5.0V ±0.5V
UNIT
MIN TYP MIN
ts(H)
ts(L)
Setup time
nAx to LEAB, nBx to LEBA
3
1.0
0.5
0.4
–0.1
1.0
0.5
ns
th(H)
t
h
(L)
Hold time
nAx to LEAB
, nBx to LEBA
3
1.0
0.5
0.2
–0.3
1.0
0.5
ns
ts(H)
t
s
(L)
Setup time
nAx to EAB
, nBx to EBA
3
1.0
0.5
0.2
–0.3
1.0
0.5
ns
th(H)
t
h
(L)
Hold time
nAx to EAB
, nBx to EBA
3
1.0
0.5
0.3
–0.2
1.0
0.5
ns
tw(L) Latch enable pulse width, Low 3 4.0 3.1 4.0 ns
Page 7
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
7
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
Waveform 1. Propagation Delay For Inverting Output
V
M
nAx, nBx
V
M
V
M
V
M
V
MVM
nLEAB, nLEBA,
nEAB
, nEBA
Waveform 3. Data Setup and Hold Times and
Latch Enable Pulse Width
ts(H)
t
h
(H)
t
s
(L)
t
h
(L)
nOEAB, nOEBA,
nEAB
, nEBA
V
M
t
PZH
t
PHZ
0V
V
OH
–0.3V
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
t
PZL
t
PLZ
0V
V
OL
+0.3V
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
V
M
V
M
V
M
V
M
V
M
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
tw(L)
V
IN
V
M
t
PHL
t
PLH
V
M
V
M
V
M
V
OUT
Waveform 2. Propagation Delay For Non-Inverting
Output
V
M
t
PLH
t
PHL
V
M
V
M
V
M
V
IN
V
OUT
nAx, nBx
nOEAB, nOEBA,
nEAB
, nEBA
nAx, nBx
Page 8
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
8
TEST CIRCUIT AND WAVEFORMS
PULSE
GENERATOR
R
T
V
IN
D.U.T
V
OUT
C
L
R
L
V
CC
R
L
7.0V
Test Circuit for 3-State Outputs
V
M
V
M
t
W
AMP (V)
NEGATIVE
PULSE
10% 10%
90%
90%
0V
V
M
V
M
t
W
AMP (V)
POSITIVE
PULSE
90% 90%
10%
10%
0V
t
THL
(tF)
t
TLH
(tR) t
THL
(tF)
t
TLH
(tR)
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate t
W
t
R
t
F
MB 3.0V 1MHz 500ns 2.5ns 2.5ns
SWITCH POSITION
TEST SWITCH
t
PLZ
closed
t
PZL
closed
All other open
Page 9
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
9
Adjustment of t
PHL
for
Load Capacitance and # of Outputs Switching
nAx to nBx or nBx to nAx
t
PLH
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nAx to nBx or nBx to nAx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
Adjustment of t
PLH
for
Load Capacitance and # of Outputs Switching
nAx to nBx or nBx to nAx
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
PHL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nAx to nBx or nBx to nAx
°C
MAX
4.5V
CC
5.5V
CC
MIN
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
PLH
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nLEBA
to nAx or nLEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PLH
for
Load Capacitance and # of Outputs Switching
nLEBA
to nAx or nLEAB to nBx
pF
16 switching
8 switching
1 switching
7
6
5
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
7
6
5
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
6
5
4
3
2
1
0
–1
–2
0 50 100 150 200
5
4
3
2
1
0
–1
–2
0 50 100 150 200
7
6
5
4
3
2
1
–55 –35 –15 5 25 45 65 85 105 125
6
5
4
3
2
1
0
–1
–2
0 50 100 150 200
Page 10
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
10
t
PHL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nLEBA
to nAx or nLEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
Adjustment of t
PHL
for
Load Capacitance and # of Outputs Switching
nLEBA
to nAx or nLEAB to nBx
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
PZH
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nOEBA
to nAx or nOEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PZH
for
Load Capacitance and # of Outputs Switching
nOEBA
to nAx or nOEAB to nBx
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
PZL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nOEBA
to nAx or nOEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PZL
for
Load Capacitance and # of Outputs Switching
nOEBA
to nAx or nOEAB to nBx
pF
16 switching
8 switching
1 switching
8
7
6
5
4
3
2
1
–55 –35 –15 5 25 45 65 85 105 125
7
6
5
4
3
2
1
–55 –35 –15 5 25 45 65 85 105 125
5
4
3
2
1
0
–1
–2
0 50 100 150 200
5
4
3
2
1
0
–1
–2
0 50 100 150 200
8
7
6
5
4
3
2
1
–55 –35 –15 5 25 45 65 85 105 125
5
4
3
2
1
0
–1
–2
0 50 100 150 200
Page 11
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
11
t
PHZ
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nOEBA
to nAx or nOEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
Adjustment of t
PHZ
for
Load Capacitance and # of Outputs Switching
nOEBA
to nAx or nOEAB to nBx
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
PLZ
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nOEBA
to nAx or nOEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PLZ
for
Load Capacitance and # of Outputs Switching
nOEBA
to nAx or nOEAB to nBx
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
PZH
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nEBA
to nAx or nEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PZH
for
Load Capacitance and # of Outputs Switching
nEBA
to nAx or nEAB to nBx
pF
16 switching
8 switching
1 switching
7
6
5
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
7
6
5
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
11
10
9
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
0 50 100 150 200
7
6
5
4
3
2
1
0
–1
–2
0 50 100 150 200
7
6
5
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
5
4
3
2
1
0
–1
–2
0 50 100 150 200
Page 12
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
12
t
PZL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nEBA
to nAx or nEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
ns
Offset in ns
Adjustment of t
PZL
for
Load Capacitance and # of Outputs Switching
nEBA
to nAx or nEAB to nBx
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
PHZ
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nEBA
to nAx or nEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PHZ
for
Load Capacitance and # of Outputs Switching
nEBA
to nAx or nEAB to nBx
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
PLZ
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
nEBA
to nAx or nEAB to nBx
°C
MAX
4.5V
CC
5.5V
CC
MIN
Adjustment of t
PLZ
for
Load Capacitance and # of Outputs Switching
nEBA
to nAx or nEAB to nBx
pF
16 switching
8 switching
1 switching
8
7
6
5
4
3
2
1
–55 –35 –15 5 25 45 65 85 105 125
7
6
5
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
5
4
3
2
1
0
–1
–2
0 50 100 150 200
12
10
8
6
4
2
0
–2
–4
0 50 100 150 200
7
6
5
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
7
6
5
4
3
2
1
0
–1
–2
0 50 100 150 200
Page 13
Philips Semiconductors Advanced BiCMOS Products Product specification
MB2543
Dual octal latched transceivers with dual enable
(3-State)
August 23, 1993
13
t
TLH
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
°C
4.5V
CC
5.5V
CC
ns
Offset in ns
Adjustment of t
TLH
for
Load Capacitance/# of Outputs
pF
16 switching
8 switching
1 switching
ns
Offset in ns
t
THL
vs Temperature (T
amb
)
C
L
= 50pF, 1 Output Switching
°C
4.5V
CC
5.5V
CC
Adjustment of t
THL
for
Load Capacitance and # of Outputs Switching
pF
16 switching
8 switching
1 switching
Volts
Volts
V
OHV
and V
OLP
vs Load Capacitance
V
CC
= 5V, VIN = 0 to 3V
pF
125°C
25°C
–55°C
V
OHP
and V
OLV
vs Load Capacitance
V
CC
= 5V, VIN = 0 to 3V
pF
125°C
25°C
–55°C
125°C
25°C
–55°C
125°C
25°C
–55°C
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
4
3
2
1
0
–55 –35 –15 5 25 45 65 85 105 125
11
9
7
5
3
1
–1
–3
0 50 100 150 200
6
5
4
3
2
1
0
–1
–2
0 50 100 150 200
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 50 100 150 200
6
5
4
3
2
1
0
–1
–2
–3
0 50 100 150 200
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