Datasheet MAS5114LS, MAS5114LL, MAS5114LD, MAS5114CE, MAS5114CD Datasheet (DYNEX)

MA5114

1/12

The MA5114 4k Static RAM is configured as 1024 x 4 bits and
manufactured using CMOS-SOS high performance, radiation hard,
3µm technology.

The design uses a 6 transistor cell and has full static operation with
no clock or timing strobe required. Address input buffers are deselected
when Chip Select is in the HIGH state.

FEATURES

■ 3µm CMOS-SOS Technology

■ Latch-up Free

■ Fast Access Time 90ns Typical

■ Total Dose 10

6

Rad(Si)

■ Transient Upset >10

10

Rad(Si)/sec

■ SEU <10

-10

Errors/bitday

■ Single 5V Supply

■ Three State Output

■ Low Standby Current 50µA Typical

■ -55°C to +125°C Operation

■ All Inputs and Outputs Fully TTL or CMOS

Compatible

■ Fully Static Operation

■ Data Retention at 2V Supply

Figure 2: Block Diagram

Operation Mode CS WE I/O Power

Read L H D OUT ISB1
Write L L D IN

Standby H X High Z ISB2

Figure 1: Truth Table

MA5114

Radiation hard 1024x4 Bit Static RAM

Replaces June 1999 version, DS3591-4.0 DS3591-5.0 January 2000

MA5114

2/12

Symbol Parameter Min. Max. Units

V

CC

Supply Voltage -0.5 7 V

V

I

Input Voltage -0.3 VDD+0.3 V

T

A

Operating Temperature -55 125 °C

T

S

Storage Temperature -65 150 °C

Figure 3: Absolute Maximum Ratings

Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functlonal operation of the device at these condltions,
or at any other condition above those indicated in the
operations section of this specification, is not Implied
Exposure to absolute maxlmum rating conditions for
extended perlods may affect device reliability.

Notes for Tables 4 and 5:

1. Characteristics apply to pre radiation at T

A

= -55°C to +125°C with VDD = 5V ±10% and to post 100k Rad(Si) total dose

radiation at TA = 25°C with VDD = 5V ±10% (characteristics at higher radiation levels available on request).

2. Worst case at TA = +125°C, guaranteed but not tested at TA = -55°C.
GROUP A SUBGROUPS 1, 2, 3.

Symbol Parameter Conditions Min. Typ. Max. Units

V

DD

Supply voltage - 4.5 5.0 5.5 V

V

lH

Input High Voltage - VDD/2 - V

DD

V

V

lL

Input Low Voltage - V

SS

- 0.8 V

V

OH

Output High Voltage I

OH1

= -1mA 2.4 - - V

V

OL

Output Low Voltage IOL = 2mA - - 0.4 V

I

LI

Input Leakage Current (note 2) All inputs except CS --±10 µA

I

LO

Output Leakage Current (note 2) Output disabled, V

OUT

= VSS or V

DD

--±20 µA

I

PUI

Input Pull-Up Current VIN = VSS on CS input only - - -100 µA

I

PDI

Input Leakage Current VIN = VSS on CS input only - - 5 µA

I

DD

Power Supply Current fRC = 1MHz, CS = 50% mark:space- 12 16 mA

I

SB1

Selected Supply Current CS = V

SS

-2535mA

I

SB2

Standby Supply Current Chip disabled - 50 3000 µA

Figure 4: Electrical Characteristics

Symbol Parameter Conditions Min. Typ. Max. Units

V

DR

VCC for Data Retention CS = V

DR

2.0 - - V

I

DDR

Data Retention Current CS = VDR, VDR = 2.0V - 30 2000 µA

Figure 5: Data Retention Characteristics

CHARACTERISTICS AND RATINGS

MA5114

3/12

AC CHARACTERISTICS

Conditions of Test for Tables 5 and 6:

1. Input pulse = VSS to 3.0V.

2. Times measurement reference level = 1.5V.

3. Transition is measured at ±500mV from steady state.

4. This parameter is sampled and not 100% tested.
Notes for Tables 6 and 7:

Characteristics apply to pre-radiation at TA = -55°C to +125°C with V

DD

= 5V±10% and to post 100k Rad(Si) total dose radiation

at TA = 25°C with VDD = 5V ±10%. GROUP A SUBGROUPS 9, 10, 11.

Symbol Parameter Min Max Units

T

AVAVR

Read Cycle Time 135 - ns

T

AVQV

Address Access Time - 135 ns

T

ELQV

Chip Select to Output Valid - 135 ns

T

ELQX

(3,4) Chip Select to Output Active 10 - ns

T

ELQZ

(3,4) Chip Select to Output Tri State 10 50 ns

T

AXQX

Output Hold from Address Change 10 - ns

Figure 6: Read Cycle AC Electrical Characteristics

Symbol Parameter Min Max Units

T

AVAVW

Write Cycle Tlme 135 - ns

T

AVWL

Address Set Up Time 10 - ns

T

WLWH

Write Pulse Width 50 - ns

T

WHAV

Write Recovery Time 5 - ns

T

DVWH

Data Set Up Time 35 - ns

T

NHDX

Data Hold Time 5 - ns

T

WLQZ

(3,4) Write Enable to Output Tri State 10 50 ns

T

ELWL

Chip Selection to Write Low 25 - ns

T

ELWH

Chip Selection to End of Write 85 - ns

T

AVWH

Address Valid to End of Write 80 - ns

T

WHQX

(3,4) Output Active from End to Write 5 - ns

Figure 7: Write Cycle AC Electrical Characteristics

Symbol Parameter Conditions Min. Typ. Max. Units

C

IN

Input Capacitance Vl = 0V - 6 10 pF

C

OUT

Output Capacitance VO = 0V - 8 12 pF

Note: T

A

= 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.

Figure 8: Capacitance

MA5114

4/12

Symbol Parameter Conditions

F

T

Basic Functionality VDD = 4.5V - 5.5V, FREQ = 1MHz

V

IL

= VSS, VIH = VDD, VOL ≤ 1.5V, VOH ≥ 1.5V
TEMP = -55°C to +125°C, GPS PATTERN SET
GROUP A SUBGROUPS 7, 8A, 8B

Figure 9: Functionality

Subgroup Definition

1 Static characteristics specified in Tables 4 and 5 at +25°C
2 Static characteristics specified in Tables 4 and 5 at +125°C
3 Static characteristics specified in Tables 4 and 5 at -55°C

7 Functional characteristics specified in Table 9 at +25°C
8A Functional characteristics specified in Table 9 at +125°C
8B Functional characteristics specified in Table 9 at -55°C

9 Switching characteristics specified in Tables 6 and 7 at +25°C
10 Switching characteristics specified in Tables 6 and 7 at +125°C
11 Switching characteristics specified in Tables 6 and 7 at -55°C

Figure 10: Definition of Subgroups

MA5114

5/12

TIMING DIAGRAMS

Figure 11a: Read Cycle 1

1. WE is high for Read Cycle.

2. Address Vaild prior to or coincident with CS transition low.

T

AVAVR

T

AVQV

T

AXQX

T

ELQV

T

ELQX

T

EHQZ

ADDRESS

CS

DATA OUT

HIGH

IMPEDANCE

DATA VALID

Figure 11b: Read Cycle 2

1. WE is high for Read Cycle.

2. Device is continually selected. CS low.

T

AVAVR

T

AVQV

T

AXQX

ADDRESS

DATA OUT

DATA VALID

MA5114

6/12

Figure 12: Write Cycle

ADDRESS

T

AVAVW

T

AVWH

T

AVWL

T

WLWH (2)

T

WHAV (3)

T

ELWL

(7)

(4)

T

WLQZ

WE

T

AXQX

T

WLQH

DATA OUT

(5) (6)

HIGH

IMPEDANCE

DATA VALIDDATA IN

T

DVWH

T

WHDX

T

ELWH

CS

1. WE must be high during all address transitions.

2. A write occurs during the overlap (T

WLWH

) of a low CS and a low WE.

3. T

WHAV

is measured from either CS or WE going high, whichever is the earlier, to the end of the write cycle.

4. If the CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in
the high impedance state.

5. DATA OUT is in the active state, so DATA IN must not be in opposing state.

6. DATA OUT is the write data of the current cycle, if selected.

7. DATA OUT is the read data of the next address, if selected.

8. T

ELWL

must be met to prevent memory corruption.

MA5114

7/12

OUTLINES AND PIN ASSIGNMENTS

Figure 13: 18-Lead Ceramic DIL (Solder Seal) - Package Style C

Ref

Millimetres Inches

Min. Nom. Max. Min. Nom. Max.

A - - 5.715 - - 0.225

A1 0.38 - 1.53 0.015 - 0.060

b 0.35 - 0.59 0.014 - 0.023
c 0.20 - 0.36 0.008 - 0.014
D - - 23.11 - - 0.910
e - 2.54 Typ. - - 0.100 Typ. -

e1 - 8.13 Typ. - - 0.300 Typ. -

H 4.44 - 5.38 0.175 - 0.212

Me - - 8.28 - - 0.326

Z - - 1.27 - - 0.050

W - - 1.53 - - 0.060

XG406

D

W

A

e b Z

H

A

1

15°

M

E

C

e

1

Seating Plane

19

1810

18 Vdd
17 A7
16

A8
15 A9
14 D1
13

D2
12 D3
11 D4
10

WE

1

A6

2

A5

3

A4

4

A3

5

A0

6

A1

7

A2

8

CS

9

Vss

Top

View

MA5114

8/12

Figure 14: 24-Lead Ceramic Flatpack (Solder Seal) - Package Style F

M

b

e

D

L

A

A1

c

Pin 1

Z

M

E

Ref

Millimetres Inches

Min. Nom. Max. Min. Nom. Max.

A - - 3.07 - - 0.121

A1 0.66 - - 0.026 - -

b 0.38 - 0.48 0.015 - 0.019
c 0.08 - 0.152 0.003 - 0.006

D 14.99 - 15.50 0.590 - 0.610

e - 2.54 - - 0.050 ­L 6.73 - 7.75 0.265 - 0.305

M 9.96 - 10.36 0.392 - 0.408

Me 7.6 - - 0.30 - -

Z 0.13 - 1.14 0.005 - 0.045

XG544

1NC
2A6
3A5
4A4
5A3
6NC
7A0
8A1

9A2
10 NC
11

CS

12 Vss

24Vdd
23A7
22A8
21A9
20NC
19NC
18D1
17D2
16D3
15D4
14NC
13

WE

Bottom

View

MA5114

9/12

Figure 15: 24-Pad Leadless Chip Carrier - Package Style L

Bottom

View

Pad 1

Radius r

3 corners

E

e b

1

D A

Bottom

View

3

2
1

24
23

22

10

11
12

13
14

15

N

C

CS

Vss

WE

N

C

D4

A5
A6

N

C

Vdd

A7
A8

987654

A4

A3

NCA0A1

A2

161718192021

A9

NC

NC

D1

D2

D3

Ref

Millimetres Inches

Min. Nom. Max. Min. Nom. Max.

A - - 2.16 - - 0.096

b1 - 0.51 - - 0.020 -

D 8.76 - 9.14 0.345 - 0.360
E 8.76 - 9.14 0.345 - 0.360

e - 1.02 - - 0.040 -

r - 0.19 - - 0.0075 -

XG470

MA5114

10/12

Package Option Burnin

Function F C L Via Static 1 Static 2 Dynamic Radiation

A6 2 1 2 R 0V 5V F6 5V
A5 3 2 3 R 0V 5V F5 5V
A4 4 3 4 R 0V 5V F4 5V
A3 5 4 5 R 0V 5V F3 5V
A0 7 5 7 R 0V 5V F0 5V
A1 8 6 8 R 0V 5V F1 5V

A2 9 7 9 R 0V 5V F2 5V
NC S 11 8 11 R 0V 5V 0V 5V
VSS 12 9 12 Direct 0V 0V 0V 0V

NW E 13 10 13 R 0V 5V 5V 5V

D4 15 11 15 R 0V 5V LOAD 5V

D3 16 12 16 R 0V 5V LOAD 5V

D2 17 13 17 R 0V 5V LOAD 5V

D1 18 14 18 R 0V 5V LOAD 5V

A9 21 15 21 R 0V 5V F9 5V

A8 22 16 22 R 0V 5V F8 5V

A7 23 17 23 R 0V 5V F7 5V
VDD 24 18 24 Direct 5V 5V 5V 5V

1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc.

2. Burnin R=1k

3. Radiation R=10k

Figure 16: Burnin and Radiation Configuration

MA5114

11/12

RADIATION TOLERANCE

Total Dose Radiation Testing

For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.

The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.

GEC Plessey Semiconductors can provide radiation
testing compliant with MIL-STD-883 test method 1019,
Ionizing Radiation (Total Dose).

Ion LET (MeV.cm2/mg)

UPSET BIT
CROSS-SECTION
(cm2/bit)

Figure 18: Typical Per-Bit Upset Cross-Section vs Ion LET

SINGLE EVENT UPSET CHARACTERISTICS

Total Dose (Function to specification)* 1x105 Rad(Si)
Transient Upset (Stored data loss) 5x10

10

Rad(Si)/sec
Transient Upset (Survivability) >1x1012 Rad(Si)/sec
Neutron Hardness (Function to specification) >1x1015 n/cm

2

Single Event Upset** 3.4x10-9 Errors/bit day
Latch Up Not possible

* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit

Figure 17: Radiation Hardness Parameters

MA5114

12/12

ORDERING INFORMATION

For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.

Unique Circuit Designator

S
L
C
R

Radiation Hard Processing

30 kRads (Si) Guaranteed
50 kRads (Si) Guaranteed

100 kRads (Si) Guaranteed

Radiation Tolerance

C
F
L

Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Leadless Chip Carrier

Package Type

QA/QCI Process

(See Section 9 Part 4)

Test Process

(See Section 9 Part 3)

Assembly Process

(See Section 9 Part 2)

L
C
D
E
B
S

Rel 0
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S

Reliability Level

MAx5114xxxxx

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© Dynex Semiconductor 2000 Publication No. DS3581-5 Issue No. 5.0 January 2000
TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM

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Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started.
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