Datasheet M50LPW116 Datasheet (SGS Thomson Microelectronics)

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Page 1

3V Supply Low Pin Count Flash Memory

■ SUPPLY VOLTAGE

= 3V to 3.6V for Program, Erase and

–V

Read Operations

–V

= 12V for Fast Program and Fast Erase

■ TWO INTERFACES

– Low Pin Count (LPC) Standard I nterface for

embedded operation with PC Chipsets.

– Address/Address Multiplexed (A/A Mux) In-

terface for programm ing equipment compat ibility.

■ LOW PIN COUNT (LPC) HARDWARE

INTERFACE MODE – 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block Pro-

tection – Register Based Read and Write Protection – 5 Additional Ge neral Purp ose I nputs f or pla t-

form design flexibility – Synchronized with 33 MHz PCI clock

■ BYTE PROGRAMMING TIME

– Single Byte Mode: 10µs (typical) – Quadruple Byte Mode: 2.5µs (typical)

■ 50 MEMORY BLOCKS

– 1 Boot Block – 18 Parameter and 31 Main Blocks

■ PROGRAM/ERA SE CON T ROL LER

– Embedded Byte Program and Block/Chip

Erase algorithms – Status Register Bits

■ PROGRAM and ERASE SUSPEND

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 30h

M50LPW116

16 Mbit (2Mb x8, Boot Block)

PRELIMINARY DATA

TSOP40 (N)

10 x 20mm

Figure 1. Logic Diagram (LPC Interface)

ID0-ID3

GPI0-

GPI4

LFRAME

CLK

INIT

M50LPW116

LAD0LAD3

TBL

AI05466

February 2003

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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M50LPW116

Figure 2. Logic Diagram (A/A Mux Interface)

A0-A10

M50LPW116

DQ0-DQ7

AI05468

DESCRIPTION

The M50LPW116 is a 16 Mbit (2Mb x8) nonvolatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming, and fast erasing, an optional 12V power supply can b e used t o reduce the programming and the erasing times.

The memory is divided into blocks that can be erased independently so it is pos sible to pres erve valid data while old data is erased. Blocks can be protected individually (except Blocks 15 to 0, which have global protection) to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The M50LPW116 features an asymm etrical block architecture. It has an array of 50 blocks: 1 Boot Block of 16KBytes, 2 Parameter Blocks of

Figure 3. TSOP Connections

IC (VIH)

NC NC NC NC

A10

NC RC

A/A Mux

RP NC NC

A9 A8 A7 A6 A5 A4 A3

IC (VIL)

NC NC INIT NC RFU NC

GPI4

CLK

RP NC

NC GPI3 GPI2 LAD0 GPI1 ID0 GPI0

TBL

M50LPW116

20 21

31 30

LFRAME

RFU RFU RFU RFU V

LAD3 LAD2 LAD1

ID1 ID2 ID3

W G RB DQ7 DQ6 DQ5 DQ4 V

DQ3 DQ2 DQ1 DQ0 A0 A1 A2

A/A Mux

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M50LPW116

8KBytes, 1 Main Block of 32KBytes, 30 Main Blocks of 64KBytes and 16 Param eter Blocks of 4KBytes.

Two different bus interfaces are supported by t he memory. The primary interface is the Low Pin Count (or LPC) Standard Interface. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50LPW116 acts as the PC BIOS on the Low P in Count bus for these P C Chipsets.

The secondary interface, the Address/Address Multiplexed (or A/A Mux) Int erface, is design ed t o be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.

The memory is offered in TSOP40 (10 x 20mm) package and it is supplied with all the bits eras ed

(set to ’1’).

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on this part. The active interface is selected before power-up or during Reset using the Interface Configur a tion Pin, IC.

The signals for each interface are discussed in the Low Pin Count (LPC) Signal Descriptions section and the Address/Address M ultiplexed (A/A Mux) Signal Descriptions section below. The supply signals are discussed in the Supply S ignal Descriptions section below.

Low Pin Count (LPC) Signal Descriptions

For the Low Pin Count (LPC) Interface see Figure 1, Logic Diagram (LPC Interface), and Table 1, Signal Names (LPC Interface).

The LPC address sequence is 32 bits long. The M50LPW116 responds to addresses mapped to the top of the 4 GByte memory space, from FFFF FFFF h. Address bits A31-A26 must be set to 1. For A25-A23 and A21, refer to Table 2. A22 is set to 1 for array access, and to 0 for register access. A20-A0 are for array addresses.

Input/Output Communications (LAD0-LAD3). All Input and Output Communication with the memory take place on these pi ns. Addresses and Data for Bus Read and Bus W rite operations are en coded on these pins.

Input Communication Frame (LFRAME

). The

) signals the start of a bus operation. When Input Communication Frame is Low, V

, on the rising edge of

the Clock a new bus operat ion is in itiated. If Input Communication Frame is L ow, V

, during a bus

operation then the operation is aborted. When Input Communication Frame is High, V

, the cur-

rent bus operation is proceeding or the bus is idle.

Table 1. Signal Names (LPC Interface)

LAD0-LAD3 Input/Output Communications LFRAME ID0-ID3 Identification Inputs GPI0-GPI4 General Purpose Inputs IC Interface Configuration RP INIT CLK Clock TBL WP

RFU

NC Not Connected Intern ally

Input Communication Frame

Interface Reset CPU Reset

Top Block Lock Write Protect Reserved for Future Use. Leave

disconnected. Supply Voltage Optional Supply Voltage for Fast

Program and Fast Erase Operations Ground

Identification Inputs (ID0-ID3). The Identification Inputs (ID0-ID3) allow to address up to 16 memories on a bus. The value on addresses A21,A23-A25 is compared to the hardware strapping on the ID0-ID3 pins to select which memory is being addressed. For an address bit to be ‘1’ the correspondent ID pin can be left floating or driven Low, V included with a value of R

; an internal pull-down resistor is

. For an address bit to

be ‘0’ the correspondent ID pin must be driven High, V

; there will be a leakage current of I

LI2

through each pin when pulled to VIH; see Table 20. By convention t he boot memory must h ave ID0-

ID3 pins left floating or driven Low, V

and a ‘1’

value on A21,A23-A25 and all additional memories take sequential ID0-ID3 configuration, as shown in Table 2.

General Purpose Inputs (GPI0-GPI4) . The General Purpose Inputs can be used as digital inputs for the CPU to read. The General Purpose Input Register holds the values on these pins. The pins must have stable data from before the start of the cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low, V High, V

IL,

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M50LPW116

Table 2. Memory Identification Input Configuration

Memory Number

1 (Boot)

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

ID3 ID2 ID1 ID0 A25 A24 A23 A21

or floating VIL or floating VIL or floating VIL or floating

or floating VIL or floating VIL or floating V

or floating VIL or floating V

or floating V

VIL or floating VIL or floating VIL or floating VIL or floating VIL or floating V VIL or floating V VIL or floating V

VIL or floating VIL or floating VIL or floating V

VIL or floating

1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

Interface Configuration (IC). The Interface Configuration input selects whether the Low Pin Count (LPC) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be changed . The state of the Interface Configuration, IC, should not be changed during operation.

To select the Low Pin Count (LPC) Interface the Interface Configuration pin should be left to float or driven Low, V

; to select the Address/Address

Multiplexed (A/A Mux) Interface t he pin should be driven High, V included with a value of R current of I

. An internal pull-down resistor is

through each pin when pulled to VIH;

LI2

; there will be a leakage

see Table 20.

Interface Reset (RP

). The Interface Reset (RP)

input is used to reset the memory. When Interface Reset (RP

) is set Low, VIL, the memor y i s i n R ese t mode: the outputs are put to high impedance and the current consumption is minimized. When RP set High, V

, the memory is in no rmal operat ion.

After exiting Reset mode, the memory enters Read mode.

CPU Reset (INIT

). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset . It behaves identically to Interface Reset, RP

, and the internal Reset lin e is the logical OR (elec tric al AND) of RP

and INIT.

Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, LAD0-LAD3. The Clock conforms to the PCI specification.

Top Block Lock (TB L

). The Top Block Lock

input is used to prevent the Top Block (Block 49) from being chan ged. When Top Block Loc k, TBL is set Low, V

, Program and Block Erase

operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL

, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL

, does not affect the protection of the other Blocks (Blocks 0 to 48).

Top Block Lock, TBL

, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL

during Program or Erase Suspend.

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M50LPW116

Table 3. Signal Names (A/A Mux Interface)

IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G W RC RB RP V

NC Not Connected Internally

Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage for Fast

Program and Fast Erase Operations Ground

Wri te Protect (WP). The Write Protect input is used to prevent the Blocks 0 to 48 from being changed. When Write Protect, WP

, is set Low, VIL, Program and Block Erase operations in the Blocks 0 to 48 have no effect, regardless of the state of the Lock Register. When Write Protect, WP High, V

, the protection of the Block is determined

, is set

by the Lock Register. The state of Write Protect, WP

, does not affect the protection of the Top Block

(Block 49). Write Protect, WP

, must be set prior to a Program or Block Erase operation is initiated and mu st not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing WP

during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do not have assigned functions in this revision of the part. They must be left disconnected.

Address/Address Multiplexed (A/A Mux) Signal Descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2, Logic Diagram (A/A Mux Interface), and Table 3, Signal Names (A/A Mux Interface).

Address Inputs (A0-A10). The Address Inputs are used to set th e R ow A ddre ss bit s ( A0- A1 0) an d the Column Address bits (A11-A20). They are latched during any bus operation by the Row/C olumn Address Select input, RC

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data s tored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the C ommand Interface of the internal state machine. The Data I nputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation.

Output Enable (G). The Output Enable , G, controls the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a c e .

Row/Column Address Select (RC

). The Row/

Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A20). The Row Address bits are latched on the falling edge of RC

whereas the Column

Address bits are latched on the rising edge.

Ready/Busy Output (RB

). The Ready/Busy pin

gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, V

, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High,

, the memory is ready for any Rea d, Program

or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfaces.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the L ockout Voltage,

. This prevents Bus Write operations from

LKO

accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After V

becomes valid the Comma nd Interface

is reset to Read mode. A 0.1µF capacitor should be connected between

the V

Supply Voltage pins and the VSS Ground

pin to decouple the current surges from the power supply. Both V

Supply Voltage pins must be

connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.

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M50LPW116

Table 4. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except f or the rating "Operating Temperature Range", str esses above those listed in the T able "Absol ute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Minimum Voltage may undershoot to –2V and for less tha n 20ns during transit i ons. Maxim um Voltage may overs hoot to V

and for less th an 20ns duri ng t ransitions.

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 5) –20 to 85 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage Supply Voltage –0.6 to 4 V Program Voltage –0.6 to 13 V

VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory and to protect the memory. When V

PP<VPPLK

Program and Erase operations cannot be performed and an error is reported in the Status Register if an attempt to change the memory contents is made. When V Program and Erase operations take place as normal. When V

= V

Fast Program

PPH

operations (using the Quadruple Byte Program command, 30h, from Table 11) and Fast Erase operations are used. Any other voltage input to V

will res ult in undefined beha vior and should

not be used. V

should not be set to V

for more than 80

PPH

hours during the life of the memory.

Ground. VSS is the reference for al l the vol t-

age measurements.

BUS OPERATIONS

The two interfaces have similar bus operations but the signals and tim ings are comple tely different. The Low Pin Count (LPC) In terface is the usual interface and all of the functionality of the part is available through this interfac e. Only a subset of functions are available through the Address/ Address Multiplexed (A/A Mux) Interface.

Follow the section Low Pin Count (LPC) Bus Operations below and the section Address/ Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface.

(1)

= V

–0.6 to V

+ 0.6

+2V

Low Pin Count (LPC) Bus Operations

The Low Pin Count (LPC) Interface consists of four data signals (LAD0-LAD3), one control line (LFRAME

) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL (RP

and INIT) are available to put the memory into

and WP). Finally two reset signals

a known state. The data signals, control signal and clock are

designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Low Pin Count Registers. A valid Bus Read operation starts when Input Communication Frame, LFRAME

, is Lo w, VIL, as Clock rises and the correct Start cycle is on LAD0-LAD3. On the following clock cycles the Host will send the Cycle Type + Dir, Address and other control bits on LAD0-LAD3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7.

See Table 6, and to Figure 4 , for a description of the Field definitions for each clock cycle of the transfer. See Table 22, and Figure 9, for details on the timings of the signals.

Bus Write. Bus Write operations write to the Command Interface or Low Pin Count Registers. A valid Bus Write operation starts when Input Communication Frame, LFRAME

, is Low, VIL, as

Clock rises and the correct Start cycle is on LAD0-

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M50LPW116

Table 5. Block Addresses

Size

(Kbytes)

16 1FC000h-1FFFFFh 49 Boot (Top)

8 1FA000h-1FBFFFh 48 Parameter

8 1F8000h-1F9FFFh 47 Parameter 32 1F0000h-1F7FFFh 46 Main 64 1E0000h-1EFFFFh 45 Main 64 1D0000h-1DFFFFh 44 Main 64 1C0000h-1CFFFFh 43 Main 64 1B0000h-1BFFFFh 42 Main 64 1A0000h-1AFFFFh 41 Main 64 190000h-19FFFFh 40 Main 64 180000h-18FFFFh 39 Main 64 170000h-17FFFFh 38 Main 64 160000h-16FFFFh 37 Main 64 150000h-15FFFFh 36 Main 64 140000h-14FFFFh 35 Main 64 130000h-13FFFFh 34 Main 64 120000h-12FFFFh 33 Main 64 110000h-11FFFFh 32 Main 64 100000h-10FFFFh 31 Main 64 0F0000h-0FFFFFh 30 Main 64 0E0000h-0EFFFFh 29 Main 64 0D0000h-0DFFFFh 28 Main 64 0C0000h-0CFFFFh 27 Main 64 0B0000h-0BFFFFh 26 Main

Address Range

Block

Number

Block

Type

64 0A0000h-0A FFFF h 25 Main 64 090000 h-09 FFFFh 24 Main 64 080000 h-08 FFFFh 23 Main 64 070000 h-07 FFFFh 22 Main 64 060000 h-06 FFFFh 21 Main 64 050000 h-05 FFFFh 20 Main 64 040000 h-04 FFFFh 19 Main 64 030000 h-03 FFFFh 18 Main 64 020000 h-02 FFFFh 17 Main 64 010000 h-01 FFFFh 16 Main

4 00F000h-00 FFFFh 15 Parameter 4 00E000 h-00 EFFF h 14 Parameter 4 00D000h-00DFFF h 13 Parameter 4 00C000h-00CFFF h 12 Parameter 4 00B000 h-00 BFFF h 11 Parameter 4 00A000 h-00 AFFF h 10 Parameter 4 00 9000 h-00 9FFFh 9 Parameter 4 00 8000 h-00 8FFFh 8 Parameter 4 00 7000 h-00 7FFFh 7 Parameter 4 00 6000 h-00 6FFFh 6 Parameter 4 00 5000 h-00 5FFFh 5 Parameter 4 00 4000 h-00 4FFFh 4 Parameter 4 00 3000 h-00 3FFFh 3 Parameter 4 00 2000 h-00 2FFFh 2 Parameter 4 00 1000 h-00 1FFFh 1 Parameter 4 00 0000 h-00 0FFFh 0 Parameter

Note: For A21 and A23, refer to Table 2. A22 i s set to 1.

LAD3. On the following Clock cycles the Host will send the Cycle Type + Di r, Address, ot her cont rol bits, Data0-Data3 and Data4-Data7 on LAD0LAD3. The memory outputs Sync data until the wait-states have elapsed.

See Table 7, and to Figure 5, for a description of the Field definitions for each clock cycle of the transfer. See Table 22, and Figure 9, for details on the timings of the signals.

Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when L FRAME V

, during the bus ope ration; the m emory will tri-

is driven Low,

state the Input/Output Communication pins, LAD0-LAD3.

Note that, during a Bus Write operation, the Command Interface starts executing the command as soon a s the data is f ully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately.

Standby. When LFRAME

is High, VIH, the memory is put into Standb y mode where LA D0LAD3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, I

CC1

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP Rese t, IN IT

, is Low, VIL. RP or IN IT must be held

, or CPU

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M50LPW116

Table 6. LPC Bus Read Field Definitions

Clock Cycle

Number

Clock Cycle

Count

Field

LAD0-

LAD3

Memory

I/O

Description

1 1 START 0000b I

CYCTYPE

+ DIR

0100b I

3-10 8 ADDR XXXX I

11 1 TAR 1111b I

12 1 TAR

1111b

(float)

13-14 2 WSYNC 0101b O

15 1 RSYNC 0000b O

16-17 2 DATA XXXX O

18 1 TAR 1111b O

19 1 TAR

1111b

(float)

N/A

On the rising edge of CLK with LFRAME

Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle.

Indicates the type of cycle and selects 1-byte reading. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b for read. Bit 0 is reset to 0.

A 32-bit address phase is transferred starting with the most significant nibble first. A26-A31 must be set to 1. A22 = 1 for Array, A22 = 0 for registers access. For A21, A23A25 values, refers to Table 2.

The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle.

The LPC Flash Memory takes control of LAD0-LAD3

during this cycle. The LPC Flash Memory drives LAD0-LAD3 to 0101b

(short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included.

The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating that data will be available during the next clock cycle.

Data transfer is two CLK cycles, starting with the least significant nibble.

The LPC Flash Memory drives LAD0-LAD3 to 1111b to indicate a turnaround cycle.

The LPC Flash Memory floats its outputs, the host takes control of LAD0-LAD3.

Figure 4. LPC Bus Read Waveforms

CLK

LFRAME

CYCTYPE

+ DIR

1182322

8/36

LAD0-LAD3

Number of clock cycles

START

ADDR TAR SYNC DATA TAR

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Page 9

Table 7. LPC Bu s W ri te Fiel d De finitions

Clock Cycle

Number

Clock Cycle

Count

Field

LAD0-

LAD3

Memory

I/O

M50LPW116

Description

1 1 START 0000b I

CYCTY

3-10 8 ADDR XXXX I

11-12 2 DATA XXXX I

13 1 TAR 1111b I

14 1 TAR

15 1 SYNC 0000b O

16 1 TAR 1111b O

17 1 TAR

PE +

DIR

011Xb I

1111b

(float)

1111b

(float)

N/A

On the rising edge of CLK with LFRAME of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle.

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 1b for write. Bit 0 is don’t care (X).

A 32-bit address phase is transferred starting with the most significant nibble first. A26-A31 must be set to 1. A22 = 1 for Array, A22 = 0 for registers access. For A21, A23-A25 values, refers to Table 2.

Data transfer is two cycles, starting with the least significant nibble.

The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle.

The LPC Flash Memory takes control of LAD0-LAD3 during

this cycle. The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command. The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle. The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

Low, the contents

Figure 5. LPC Bus Write Waveforms

CLK

LFRAME

LAD0-LAD3

Number of clock cycles

Low, VIL, for t

START

. The memory resets to Read

PLPH

CYCTYPE

+ DIR

1182212

mode upon return from Res et mo de and the Lock Registers return to their default states regardless of their state before Reset, see Table 15. If RP

goes Low, VIL, during a Program or Erase

INIT

operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

PLRH

to abort a

Program or Erase operation. Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL

, and

ADDR DATA TAR SYNC TAR

Write Protect, WP

, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus Operations

The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and three control signals (RC signal, RP

, can be used to reset the memory.

, G, W). An additional

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M50LPW116

Table 8. A/A Mux Bus Operations

Operation G W RP

Bus Read Bus Write Output Disable Reset

or V

Table 9. Manufacturer and Device Codes

Operation G

Manufacturer Code Device Code

VIL or V

W RP A20-A1 A0 DQ7-DQ0

Don’t Care Data Output

VCC or V

Don’t Care Hi-Z Don’t Care Hi-Z

V V

PPH

DQ7-DQ0

Data Input

20h 30h

The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Low Pin Count (LPC) Interface are available; these include all the Commands but exclude the Security features and other registers.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface.

Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC Write Enable (W be High, V

) and Interface Reset (RP) must

, and Output Enable, G, Low, VIL, in

. Then

order to perform a Bus Read operation. The Data Inputs/Outputs will output the value, see Figure 11, A/A Mux Interface Read AC Waveforms, and Table 24, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC the Data Inputs/Outputs; Output Enable, G Interface Reset, RP Enable, W

, must be Low, VIL. The Data Inputs/

. The data should be set up on

, and

, must be High, VIH and Write

Outputs are latched on the rising edge of Write Enable, W

. See Figure 12, and Table 25, for

details of the timing requirements.

Output Disa bl e . The data outputs are high-impedance when the Output Enable, G

, is at VIH.

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP held Low, V

for t

is Low, VIL. RP must be

. If RP is goes Low, VIL,

PLPH

during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

to abort a Program or Erase operation.

PLRH

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations.

After power-up or a Reset operation the memory enters Read mode.

The commands are summarized in Table 11, Commands. Refer to Tab le 1 1 in c onjun ction with the text descriptions below.

Read Memory A rray Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array.

While the Program/Erase Controller is executing a Program or Erase operation the m emory will not accept the Read Memory Array command until the operation completes.

Read Statu s Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the

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M50LPW116

command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits.

Read Electronic S ignature C o mmand. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until another command is issued.

After the Read Electronic Signature Command is issued the Manufacturer Code and Devi ce Code can be read using Bus Read op erations us ing the addresses in Table 10.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data in the internal state m achine and starts the Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

If the address falls in a pro tected block then the Program operation will abort, the data in the memory array will no t be changed and the S tatus Register will output the error.

During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 12.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’.

See Figure 13, for a suggested flowchart on using the Program command.

Quadruple Byte Program Command (A/A Mux Mode) . The Quadruple Byte Program Comm and

can be used to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 a nd A1. Programming should not be attempted when V

is not at V

PPH

Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the

Table 10. Read Electronic Signature

Code Address Data

Manufacturer Code 000000h 20h Device Code 000001h 30h

Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspe nd command. All other commands will be ignored. Typical Quadruple Byte Program times are given in Ta ble

12. Note that the Quadruple Byte Program comm and

cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’.

See Figure 14, for a suggested flowchart on using the Quadruple Byte Program command.

Chip Erase Command. The Chip Erase Command can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be attempted when V

is not at V

can also be executed if V

. The operation

PPH

is b elow V sult could be uncertain. Two Bus Write operations are required to issue the com mand and start the Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Chip Erase operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Chip Erase times are given in Table 12. The Chip Erase command sets all of the bits in the memory to ‘1’. See Figure 16, Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only), for a suggested flowchart on using the Chip Erase command.

Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal stat e machine and starts th e Pro-

gram/Erase Controller. Once the command is issued subsequent Bus Read ope rations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

If the block is protected then the Block Erase operation will abort, the data in the block will not be

PPH

, but re-

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M50LPW116

Table 11. Commands

Bus Write Operations

Command

Cycles

Read Memory Array 1 X FFh Read Status Register 1 X 70h

Read Electronic Signature

1X 90h 1X 98h 2X 40hPAPD

Program

2X 10hPAPD

Quadruple Byte Program (A/A Mux Mode)

5X 30h

Chip Erase 2 X 80h X 10h Block Erase 2 X 20h BA D0h Clear Status Register 1 X 50h Program/Erase Suspend 1 X B0h Program/Erase Resume 1 X D0h

1X 00h 1X 01h

Invalid/Reserved

1X 60h 1X2Fh 1XC0h

Note: X Don’t Care, PA Program Address, PD Program Data, A

Read Memory Array. After a Read M em ory Array command, read the memory as normal unti l another comm and is issued. Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature. Af t er a Read Electronic Signature command, read Manufacturer Code, Device Code until another co m -

mand is issued. Block Erase, Program. After th ese com man ds re ad t he S tat us Re gist er un t il th e comm an d comp l etes and an othe r c omma nd is is -

sued. Quadruple Byte Program (A/A Mux Mode). Addres ses A

bit A0 and A1. After this comm and, the us er shou ld rep eat edl y read t he Stat us Regi st er until the co mmand has compl eted, at whic h point ano ther comma nd can be issued.

Chip Eras e. This command is only valid in A/A Mux mode. Aft er this command rea d the Stat us Register until the c ommand comple tes and another command is issued.

Clear Status Register. After the Clear St atus Register command bits 1, 3, 4 and 5 in the Stat us Register a re reset to ‘0’. Program/Erase Susp end. After the Program /Erase Sus pend command has been accept ed, issue Read Mem ory Array, Read Status

Register, Program (during Era se suspend ) and Program/ Erase resum e commands. Program/Erase Resu me. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the Status Register unti l the Program/ E rase Contr ol l er completes and the mem ory returns to Read Mode.

Invalid/Reserved . Do not use In valid or Res erved commands.

1st 2nd 3rd 4th 5th

Addr Data Addr Data Addr Data Addr Data Addr Data

1,2,3,4

, A2, A3 and A4 must be consecutive addresses di ffering only for addre ss

Consecut i ve Addresses, BA Any address in the Block.

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Table 12. Program and Erase Times

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Parameter Interface Test Condition Min

Byte Program 10 200

= 12V ± 5%

Quadruple Byte Program A/A Mux

Chip Erase A/A Mux

Block Program (64 Kbytes)

Block Erase (64 Kbytes)

Program/Erase Suspend to Program pause Program/Erase Suspend to Block Erase pause

Note: 1. TA = 25°C, VCC = 3.3V

2. This time is obtained execut i ng t he Quadrupl e By te Program Command.

3. Sampled only, not 100% tested.

4. Time to program four bytes.

(3)

A/A Mux

(3)

changed and the Status Register will output the error.

During the Block Erase operation the me mory wi ll only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Block Erase times are given in Table 12.

The Block Erase command sets all of the bits in

the block to ‘1’. All previous data in the block is lost.

See Figure 17, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Erase command.

Clear Status Register Command. The Clear St atus Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subs equent Bus Read operations continue to output the same data.

The bits in the Status Register are stic ky and do not automatically return to ‘0’ when a new Program or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program or Erase command.

Program/Erase Suspend Command. The Program/Erase Suspend command can be used to pause a Program or B lock Erase operation. O ne Bus Write cycle is required to issue the Program/ Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase

= 12V ± 5%

= V

= 12V ± 5%

= V

Controller Status bit to find out when the Program/ Erase Controller has paused; no other commands will be accep ted until the Prog ram/ Erase Cont roller has paused. After the Program/Erase Cont roller has paused, the memory will continue to output the Status Register until another command is issued.

During the polling period between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/ Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to d etermine if the opera tion has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 12.

During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspe nded operation was Block Erase then the Program com mand will also be accepte d; only the blocks no t being erased may be read or programmed correctly.

See Figure 15, Program Suspend and Resume Flowchart and Pseudo Code, and Figure 18, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command.

Program / Erase Resume Command. The Program/Erase Resume com m and c an be used to restart the Program/Erase Controller after a

(1)

Typ

18 sec

0.1

0.4 5 sec

0.75 8 sec

Max Unit

(4)

(2)

110sec

200

µ µ

sec

s s

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M50LPW116

Table 13. Status Register Bits

Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

(1)

Program active ‘0’ Program suspended ‘1 Program completed successfully ‘1’ Program failure due to V Program failure due to Block Protection (LPC Interface only) ‘1’ Program failure due to cell failure ‘1’

Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Block Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Error

‘1’

X X X X X X

‘0’ ‘0’ ‘0’ ‘0’ ‘0’

(1)

‘0’ ‘0’ ‘0’ ‘1’ ‘0’

(1)

‘0’ ‘0’ ‘0’ ‘0’ ‘0’

(1)

‘0’ ‘0’ ‘1’ ‘0’ ‘0’

(1)

‘0’ ‘0’ ‘0’ ‘0’ ‘1’

(1)

‘0’ ‘1’ ‘0’ ‘0’ ‘0’

Erase failure due to V Block Erase failure due to Block Protection (LPC Interface

only) Erase failure due to failed cell(s) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ Sequence command error ‘1’ ‘0’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’

Note: 1. For Program operat i ons during Erase Suspend Bit 6 is ‘1’, ot herwise Bi t 6 is ‘0’.

Program/Erase Suspend has p aused it. One Bus Write cycle is required to issue the Program/Erase Resume command. O nc e the command is iss ued subsequent Bus Read operations read the Status Register.

STATUS REGISTER

The Status Register provides information on the current or previous Program or Erase operation. Different bits in the Status Register convey different information and errors on the operation.

To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register c an be read from any address.

The Status Register bits are summarized in Table 13, Status Register Bits. Refer to Table 13 in conjunction with the text descriptions below.

Program/Erase Controller Status (Bit 7). The Progra m/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is

‘0’, the Program/Erase Controller is active; when the bit is ‘1’, the Program/Erase Controller is inactive.

The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Su spend c om m and

Error

‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’

‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’

es. After the Program/Erase Controller pauses the bit is ‘1’.

During Program and Erase operation the Program/Erase Controller Status bit can be poll ed to find the end of the ope ration. The o ther b its in t he Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is ‘1’.

After the Program/Erase Controller completes its operation the Erase Status , Program Status, V Status and Block Protection Status bits should be tested for errors.

Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that a Block Era se operation has been suspended and is waiting to be resumed. The Eras e Suspen d Status sho uld only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.

When the Erase Suspend Sta tus bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/Er ase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program /Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’.

is issued until the Program/Erase Controller paus-

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M50LPW116

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has applied the maximum number of erase pulses to the block(s) and still failed to verify that the block(s) has erased correctly. The Erase Status bit should be read

once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive).

When the Erase Status bit is ‘0’ the memory has successfully verified that the block(s) has erased correctly; when the Erase Status bit is ‘ 1’ the P rogram/Erase Controller has applied the maximum number of pulses to the block(s) an d still failed to verify that the block(s) has erased correctly.

Once the Erase Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. (When Bit 4 and Bit 5 are set to ‘1 ’, a wrong command sequence has been attempted).

Program Status (Bit 4). The Program Status bit can be used to identify if the memory has applied the maximum number of program pulses to the byte and still failed to verify that the byte has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive).

When the Program Status bit is ‘0’ the memory has successfully verified that the byte has programmed correctly; when the Program Status bit is ‘1’ the Program/Erase Controller has applied the maximum number of pulses to the byte an d still failed to verify that the byte has program med c orrectly.

Once the Program Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong command sequence has been attempted) .

Status (Bit 3). The VPP Status bit can be

used to identify an invalid v oltage on the V during Program and Erase operations. The V

pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if V

becomes invalid during a Program or

Erase operation. When the V

pin was sampled at a valid vol tag e; w hen the

Status bit is ‘1’ the VPP pin has a voltage that

is below the V

Status bit is ‘ 0’ the vol tage on the

Lockout Voltage, V

PPLK

, the memory is protected; Program and Erase operation cannot be performed. (The V

status bit is ‘1’

if a Quadruple Byte Program comma nd is issued and the V

signal has a voltage less than V

PPH

applied to it.)

Once the V

Status bit set to ‘1’ it can only be re-

set to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Re sume command is issued the Program Suspend Status bit returns to ‘0’.

Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if the Program or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit i s to ‘0’ no Program or Block Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is ‘1’ a Program or Block E rase operation has been attempted on a protected block.

Once it is set to ‘ 1’ the Block Protection Stat us bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset . If it is set to ‘1’ it should be reset before a new Program or Block Erase command is issued, otherwise the new command will appear to fail.

Using the A/A Mux Interface the Block Protection Status bit is always ‘0’.

Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked.

LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS

When the Low Pin Count Interface is selected several additional registers can be accessed. These registers control the protection status of the Blocks and read the General Purpose Input pins. See Table 14 for an example of the Register Conf iguration map, valid for the boot me mory, i.e. ID0-ID3 floating or driven L

, VIL and A21, A23-A25 set

to ‘1’ .

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M50LPW116

Table 14. Low Pin Count Register Configuration Map

Mnemonic Register Name

T_BLOCK_LK Top Block Lock Register (Block 49) FFBFC002h 01h R/W T_MINUS01_LK Top Block[-01] Lock Register (Block 48) FFBFA002h 01h R/W T_MINUS02_LK Top Block[-02] Lock Register (Block 47) FFBF8002h 01h R/W T_MINUS03_LK Top Block[-03] Lock Register (Block 46) FFBF0002h 01h R/W T_MINUS04_LK Top Block[-04] Lock Register (Block 45) FFBE0002h 01h R/W T_MINUS05_LK Top Block[-05] Lock Register (Block 44) FFBD0002h 01h R/W T_MINUS06_LK Top Block[-06] Lock Register (Block 43) FFBC0002h 01h R/W T_MINUS07_LK Top Block[-07] Lock Register (Block 42) FFBB0002h 01h R/W T_MINUS08_LK Top Block[-08] Lock Register (Block 41) FFBA0002h 01h R/W T_MINUS09_LK Top Block[-09] Lock Register (Block 40) FFB90002h 01h R/W T_MINUS00_LK Top Block[-10] Lock Register (Block 39) FFB80002h 01h R/W T_MINUS11_LK Top Block[-11] Lock Register (Block 38) FFB70002h 01h R/W T_MINUS12_LK Top Block[-12] Lock Register (Block 37) FFB60002h 01h R/W T_MINUS13_LK Top Block[-13] Lock Register (Block 36) FFB50002h 01h R/W T_MINUS14_LK Top Block[-14] Lock Register (Block 35) FFB40002h 01h R/W T_MINUS15_LK Top Block[-15] Lock Register (Block 34) FFB30002h 01h R/W T_MINUS16_LK Top Block[-16] Lock Register (Block 33) FFB20002h 01h R/W T_MINUS17_LK Top Block[-17] Lock Register (Block 32) FFB10002h 01h R/W T_MINUS18_LK Top Block[-18] Lock Register (Block 31) FFB00002h 01h R/W T_MINUS19_LK Top Block[-19] Lock Register (Block 30) FFAF0002h 01h R/W T_MINUS20_LK Top Block[-20] Lock Register (Block 29) FFAE0002h 01h R/W T_MINUS21_LK Top Block[-21] Lock Register (Block 28) FFAD0002h 01h R/W T_MINUS22_LK Top Block[-22] Lock Register (Block 27) FFAC0002h 01h R/W T_MINUS23_LK Top Block[-23] Lock Register (Block 26) FFAB0002h 01h R/W T_MINUS24_LK Top Block[-24] Lock Register (Block 25) FFAA0002h 01h R/W T_MINUS25_LK Top Block[-25] Lock Register (Block 24) FFA90002h 01h R/W T_MINUS26_LK Top Block[-26] Lock Register (Block 23) FFA80002h 01h R/W T_MINUS27_LK Top Block[-27] Lock Register (Block 22) FFA70002h 01h R/W T_MINUS28_LK Top Block[-28] Lock Register (Block 21) FFA60002h 01h R/W T_MINUS29_LK Top Block[-29] Lock Register (Block 20) FFA50002h 01h R/W T_MINUS30_LK Top Block[-30] Lock Register (Block 19) FFA40002h 01h R/W T_MINUS31_LK Top Block[-31] Lock Register (Block 18) FFA30002h 01h R/W T_MINUS32_LK Top Block[-32] Lock Register (Block 17) FFA20002h 01h R/W T_MINUS33_LK Top Block[-33] Lock Register (Block 16) FFA10002h 01h R/W T_MINUS34_LK Top Block[-34] Lock Register (Block 15 to 0) FFA00002h 01h R/W

MANUF_REG Manufacturer Code Register FFBC0000h 20h R

DEV_REG Device Code Register FFBC000 1h 30h R

GPI_REG General Purpose Input Register FFBC0100h N/A R

Note: 1. This ma p i s referred t o the boot mem ory (ID0-ID3 floatin g or driven Lo w, VIL, and A21, A2 3-A25 set to ‘1’ ).

(1)

Memory

Address

Default

Value

Access

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Tabl e 15. Lock R egister Bit Def initions

(1)

Bit Bit Name Value Function

7-3 Reserved

‘1’ Bus Read operations in this Block always return 00h.

2 Read-Lock

Bus read operations in this Block return the Memory Array contents. (Default

‘0’

value). Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset

1 Lock-Down

to ‘0’ following a Reset (using RP Read-Lock and Write-Lock can be changed by writing new values to them. (Default

‘0’

value). Program and Block Erase operations in this Block will set an error in the Status

‘1’

or INIT) or after power-up.

0 Write-Lock

Program and Block Erase operations in this Block are executed and will modify the

‘0’

Block contents.

Note: 1. Applies to T op Blo ck L ock R egi ster (T_ BLOC K_LK) an d To p Bloc k [-1] L oc k Reg ister (T_ MI NUS0 1_LK ) to Top Bl ock [-3 4] Lock

Table 16. General Purpose Input Regi s te r D ef i ni tion

(1)

Bit Bit Name Value Function

7-5 Reserved

Input Pin GPI4 is at V

‘1’

4 GPI4

Input Pin GPI4 is at V

‘0’

Input Pin GPI3 is at V

‘1’

3 GPI3

Input Pin GPI3 is at V

‘0’

Input Pin GPI2 is at V

‘1’

2 GPI2

Input Pin GPI2 is at V

‘0’

Input Pin GPI1 is at V

‘1’

1 GPI1

Input Pin GPI1 is at V

‘0’

Input Pin GPI0 is at V

‘1’

0 GPI0

Input Pin GPI0 is at V

‘0’

Note: 1. Appl i es to the General Purpose Input Register (GPI_RE G).

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M50LPW116

Lock Registers

The Lock Registers control the protection status of the Blocks. Each Block has its own Lock Regi ster. Blocks 0 to 15 have the same Lock Register. Three bits within each Lock Register control the protection of each block, the W rite Lock Bit, the Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written, though care should be taken when writing as, once

the Lock Down Bi t is set, ‘1’, further modifications to the Lock Register cannot be made until cleared, to ‘0’, by a reset or power-up.

See Table 15 for details on the bit definitions of the Lock Registers.

Write Lock. The Write Lock Bit determines whether the contents of the Block can be modified (using the Program or Block Erase Command). When the Write Lock Bit is set, ‘1’, the block is write protected; any operations that attempt to change the data in the block will fail and the Status Register will report the error. When the Write Lock Bit is reset, ‘0’, the block is not write protected through the Lock Register and may be modified unless write protected through some other means.

When V

is less than V

all blocks are pro-

PPLK

tected and cannot be modified, regardl ess of the state of the Write Lock Bit. If Top Block Lock, TBL is Low, V

, then the Top Block (Block 49) is write

protected and cannot be modified. Similarly, if Write Protect, WP

, is Low, VIL, then the Blocks 0

to 48 are write protected and cannot be modified. After power-up or reset the Write Lock Bit is al-

ways set to ‘1’ (write protected). Read Lock. The Read Lock bit determines

whether the contents of the Block can be read (from Read mode). When the Read Lock Bit is set, ‘1’, the block is read prot ected; an y operat ion that attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is reset, ‘0’, read operations in the Block return the data programmed into the block as expected.

After power-up or reset the Read Lock B it is always reset to ‘0’ (not read protected).

Lock Down. The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the Write Lock, Read Lock and Lock Down Bits cannot be performed. A reset or power-up is required before changes to these bits can be made. When the Lock Down Bit is reset, ‘0’, the Write L ock, Read Lock and Lock Down Bits can be changed.

General Purpose Input Register

The General Purpose Input Register holds the state of the General Purpose Input pins, GPI0GPI4. When this register is read, the state of these pins is returned. This register is read-only and writing to it has no effect.

The signals on the General Purpose Input pins should remain constant throughout the whole Bus Read cycle in order to guarantee that the correct data is read.

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M50LPW116

Table 17. LPC Interface AC Measurement Conditions

Parameter Value Unit

Supply Voltage

3.0 to 3.6 V

Load Capacitance (C

)

Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages

Figure 6. LPC Interface AC Testing Input Output Waveforms

0.6 V

0.2 V

Input and Output AC Testing Waveform

IO < I

Output AC Tri-state Testing Waveform

IO > I

IO < I

0.4 V

0.2 V

10 pF

1.4 ns

≤

and 0.6 V

0.4 V

V V

AI03404

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M50LPW116

Table 18. A/A Mux Interface AC Measurement Conditions

Parameter Value U nit

Supply Voltage

3.0 to 3.6 V Load Capacitance (C Input Rise and Fall Times

)

30 pF

10 ns

≤

Input Pulse Voltages 0 to 3 V Input and Output Timing Ref. Voltages 1.5 V

Figure 7. A/A Mux I nte rfac e AC Testing In put Output Wav ef orm

1.5V

AI01417

Table 19. Impedance (T

= 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit

(1)

CLK

(2)

Note: 1. Sampled only, not 100% tested.

2. See PCI Specific ation.

Input Capacitance Clock Capacitance

Recommended Pin Inductance

V V

= 0V = 0V

13 pF

312pF

20 nH

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M50LPW116

Table 20. DC Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Interface Test Condition Min Max Unit

PPLK

LKO

(INIT)

(2)

LI2

PP1

PPH

(1)

CC1

Input High Voltage

Input Low Voltage

Input High Voltage LPC 1.35

INIT

Input Low Voltage LPC –0.5

INIT Input Leakage Current

IC, IDx Input Leakage Current

IC, IDx Input Pull Low Resistor

Output High Voltage

Output Low Voltage

Output Leakage Curren t

VPP Voltage VPP Voltage (Fast

Program/Fast Erase)

(1)

VPP Lockout Voltage VCC Lockout Volt age

Supply Current (Standby) LPC

LPC

A/A Mux

LPC –0.5

0.5 V

0.7 V

CCVCC

+ 0.5 + 0.3

0.3 V

A/A Mux -0.5 0.8 V

+ 0.5

0.2 V

0V ≤ V

IC, ID0, ID1, ID2, ID3 = V

≤ V

±10

200 µA

20 100 k

LPC I

A/A Mux I

LPC

A/A Mux

0V ≤ V

= –500µA

= –100µA

= 1.5mA 0.1 V

= 1.8mA

≤ V

OUT

0.9 V

– 0.4

0.45 V ±10

3 3.6 V

11.4 12.6 V

1.5 V

1.8 2.3 V

LFRAME

All other inputs 0.9 VCC to 0.1 V

= 0.9 VCC, VPP = V

100

VCC = 3.6V, f(CLK) = 33MHz

V V

µA

Ω

V V

µA

CC2

Supply Current (Standby) LPC

LFRAME

All other inputs 0.9 VCC to 0.1 V

= 0.1 VCC, VPP = V

VCC = 3.6V, f(CLK) = 33MHz

= VCC max, VPP = V

Supply Current

CC3

CC4

CC5

PP1

Note: 1. Sampled only, not 100% tested.

(Any internal operation active)

Supply Current (Read) A/A Mux Supply Current

(1)

(Program/Erase) VPP Supply Current

(Read/Standby) VPP Supply Current

(1)

(Program/Erase active)

2. Input leakage currents in cl ude High-Z output leak age for all bi-directional buffers with tri-s tate outputs.

LPC

A/A Mux Program/Erase Controller Active 20 mA

f(CLK) = 33MHz

= VIH, f = 6MHz

= 0mA

OUT

= V

= 12V ± 5%

10 mA

60 mA

20 mA

400

15 mA

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µA µA

Page 22

M50LPW116

Table 21. LPC Interface Clock Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Test Condition Value Unit

CYC

CLK Cycle Time

(1)

Min 30 ns

HIGH

LOW

CLK High Time Min 11 ns CLK Low Time Min 11 ns

Min 1 V/ns

CLK Slew Rate peak to peak

Max 4 V/ns

Note: 1. Devic es on the PCI Bu s m ust work wi th any clo ck frequen cy between D C and 33MHz. Below 16MH z devices may be guar anteed

by design rather than tested. Refer to PCI Specification.

Figure 8. LPC Interface Clock Waveform

tCYC

tHIGH tLOW

0.6 V

0.5 V

0.4 V

0.3 V

0.2 V

CC CC CC CC

0.4 VCC, (minimum)

p-to-p

AI03403

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Page 23

Table 22. LPC Interface AC Signal Timing Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol

PCI

Symbol

Parameter Test Condition Value Unit

M50LPW116

CHQV

(1)

CHQX

CHQZ

AVCH

DVCH

CHAX

CHDX

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-

ification.

2. Applies to all inputs except CLK.

CLK to Data Out

val

CLK to Active

(Float to Active Delay) CLK to Inactive

off

(Active to Float Delay)

Input Set-up Time

Input Hold Time

(2)

Min 2 ns

Max 11 ns

Min 2 ns

Max 28 ns

Min 7 ns

Min 0 ns

Figure 9. LPC Interface AC Signal Timing Waveforms

CLK

LAD0-LAD3

tCHQV

VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA

tCHQZ tCHQX

tDVCH

tCHDX

VALID

AI04431

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Page 24

M50LPW116

Table 23. Reset AC Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Test Condition Value Unit

PLPH

PLRH

PHFL

PHWL

PHGL

Note: 1. See Ch apter 4 of the PCI Specifi cation.

RP or INIT Reset Pulse Width Min 100 ns

RP or INIT Low to Reset

or INIT Slew Rate

(1)

RP or INIT High to LFRAME Low LPC Interface only Min 30 RP High to Write Enable or Output

Enable Low

Figure 10. Reset AC Waveforms

RP, INIT

W, G, LFRAME

Program/Erase Inactive Max 100 ns

Program/Erase Active Max 30

Rising edge only Min 50 mV/ns

A/A Mux Interface only Min 50

tPLPH

tPHWL, tPHGL, tPHFL

tPLRH

AI04432

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Page 25

M50LPW116

Table 24. A/A Mux Interface Read AC Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Test Condition Value Unit

AVAV

AVCL

CLAX

AVCH

CHAX

CHQV

GLQV

PHAV

GLQX

GHQZ

GHQX

Note: 1. G may be delayed up to t

Read Cycle Time Min 250 ns Row Address Valid to RC Low Min 50 ns RC Low to Row Address Transition Min 50 ns Column Address Valid to RC high Min 50 ns RC High to Column Address Transition Min 50 ns

(1)

RC High to Output Valid Max 150 ns

(1)

Output Enable Low to Output Valid Max 50 ns RP High to Row Address Valid Min 1

Output Enable Low to Output Transition Min 0 ns Output Enable High to Output Hi-Z Max 50 ns Output Hold from Output Enable High Min 0 ns

– t

CHQV

after the ri si ng edge of RC without impact on t

GLQV

Figure 11. A/A Mux Interface Read AC Waveforms

tAVAV

CHQV

A0-A10

DQ0-DQ7

ROW ADDR VALID NEXT ADDR VALID

tAVCL tAVCH

tCLAX tCHAX

tPHAV

COLUMN ADDR VALID

tCHQV

tGLQV tGLQX

tGHQZ tGHQX

VALID

AI03406

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Page 26

M50LPW116

Table 25. A/A Mux Interface Write AC Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Test Condition Value Unit

WLWH

DVWH

WHDX

AVCL

CLAX

AVCH

CHAX

WHWL

CHWH

VPHWH

WHGL

WHRL

QVVPL

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

Write Enable Low to Write Enable High Min 100 ns Data Valid to Write Enable High Min 50 ns Write Enable High to Data Transition Min 5 ns Row Address Valid to RC Low Min 50 ns RC Low to Row Address Transition Min 50 ns Column Address Valid to RC High Min 50 ns RC High to Column Address Transition Min 50 ns Write Enable High to Write Enable Low Min 100 ns RC High to Write Enable High Min 50 ns

(1)

VPP High to Write Enable High Write Enable High to Output Enable Low Min 30 ns

Write Enable High to RB Low Min 0 ns

(1,2)

Output Valid, RB High to VPP Low

is seen as a logic i nput (VPP < 3.6V ).

Min 100 ns

Min 0 ns

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Page 27

Figure 12. A/A Mux Interface Write AC Waveforms

M50LPW116

A0-A10

DQ0-DQ7

Write erase or program setup

tAVCL

tWLWH

tCLAX

tWHWL

Write erase confirm or valid address and data

R2 C2

tAVCH

tCHAX

tVPHWH tWHGL

tWHRL

IN1

Automated erase or program delay

tCHWH

IN2

Read Status

tQVVPL

tWHDXtDVWH

VALID SRD

Ready to write

another command

AI04194

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Page 28

M50LPW116

Figure 13. Program Flow c hart and Pseudo Code

Start

LPC

Interface

Only

Write 40h or 10h

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

Suspend

Program to Protected

Block Error (1, 2)

YES

Suspend

VPP Invalid Error (1, 2)

Program

Error (1, 2)

Program command: – write 40h or 10h – write Address & Data (memory enters read status state after the Program command)

do: –read Status Register if Program/Erase Suspend command given execute suspend program loop

Loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4 = 1, Program error: – error handler

If b1 = 1, Program to protected block error: – error handler

AI04433

Note: 1. A Status check of b1 (Protected Block), b3 (VPP invalid ) and b4 (Pro gram Er ror) can be made after each P rogra m operati on by

following the correct command se quence.

2. If an er ror is found, the Status Register must be cleared before further Prog ram /Erase Controller operation s.

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Page 29

M50LPW116

Figure 14. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 30h

Write Address 1

Write Address 2

Write Address 3

Write Address 4

Read Status

& Data 1

& Data 2

& Data 3

& Data 4

b7 = 1

b3 = 0

(3)

YES

Suspend

YES

Suspend

VPP Invalid Error (1, 2)

Loop

Quadruple Byte Program command: – write 30h – write Address 1 & Data 1 – write Address 2 & Data 2 – write Address 3 & Data 3 – write Address 4 & Data 4 (memory enters read status state after the Quadruple Byte Program command)

do: – read Status Register if Program/Erase Suspend command given execute suspend program loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

(3) (3) (3) (3)

b4 = 0

End

Note: 1. A St a t u s check of b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by following the correct com-

mand sequence.

2. If an er ror is found, the Status Register must be cleared before further Prog ram /Erase Controller operation s.

3. Address 1, Addre ss 2, Address 3 and Address 4 m ust be consecutive addr esses differing only for address bit s A 0 and A1.

YES

Program

Error (1, 2)

If b4 = 1, Program error: – error handler

AI03982

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Page 30

M50LPW116

Figure 15. Program Suspend and Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h

Read Status

– write B0h – write 70h

do: – read Status Register

b7 = 1

YES

b2 = 1

YES

Write a read

Command

Read data from

another address

Write D0h

Program Continues

Program Complete

Write FFh

Read Data

while b7 = 1

If b2 = 0 Program completed

Program/Erase Resume command: – write D0h to resume the program – if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).

AI03408

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Page 31

Figure 16. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

M50LPW116

Write 80h

Write 10h

Read Status

YES

VPP Invalid

Error (1)

Command

Sequence Error (1)

b7 = 1

b3 = 0

b4, b5 = 0

b5 = 0 Erase Error (1)

Chip Erase command: – write 80h – write 10h (memory enters read Status Register after the Chip Erase command)

do: – read Status Register

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4, b5 = 1, Command sequence error: – error handler

If b5 = 1, Erase error: – error handler

YES

End

Note: 1. If an error is found, the Status Register m ust be cleared before further Prog ram /Erase Controller operations.

AI04195

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Page 32

M50LPW116

Figure 17. Block Erase Flowchart and Pseudo Code

Start

Write 20h

Write Block Address

& D0h

Read Status

b7 = 1

b3 = 0

b4, b5 = 0

b5 = 0 Erase Error (1)

YES

Suspend

Sequence Error (1)

VPP Invalid

Error (1)

Command

Block Erase command: – write 20h – write Block Address & D0h (memory enters read Status Register after the Block Erase command)

do: – read Status Register – if Program/Erase Suspend command given execute suspend erase loop

YES

Suspend

Loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4, b5 = 1, Command sequence error: – error handler

If b5 = 1, Erase error: – error handler

YES

LPC

Interface

Only

Note: 1. If an error is found, the Status Register m ust be cleared before further Prog ram /Erase Controller operations.

b1 = 0

End

YES

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error: – error handler

32/36

AI04434

Page 33

Figure 18. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h

– write B0h – write 70h

M50LPW116

Read Status

b7 = 1

YES

b6 = 1

YES

Read data from

another block

Program

Write D0h

Erase Continues

Erase Complete

Write FFh

Read Data

do: – read Status Register

while b7 = 1

If b6 = 0, Erase completed

Program/Erase Resume command: – write D0h to resume erase – if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).

AI03410

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Page 34

M50LPW116

Table 26. Ordering Information Scheme

Example: M50LPW116 N1T

Device Type

M50

Architecture

LP = Low Pin Count Interface

Operating Voltage

W = 3.0 to 3.6V

Device Function

116 = 16 Mbit (2Mb x8), Boot Block

Package

N = TSOP40: 10 x 20 mm

Temperature Range

1 = 0 to 70 °C 5 = –20 to 85°C

Option

T = Tape & Reel Packing

For a list of available options or for furt her information on any aspect of this device, please contact the ST Sales Office nearest to you.

Table 27. Revision History

Date Version Revision Details

September 2001 -01 First Issue

12-Dec-2001 -02 Extensions to the descriptions on Quadruple Byte Programming

16-Jan-2002 -03 Device code announced: 30h

01-Mar-2002 -04 RFU pins must be left disconnected

30-Jul-2002 -05 Quadruple Byte Mode, in LPC mode, removed

22-Nov-2002 5.1

13-Feb-2003 5.2 Datasheet promoted from Product Preview to Preliminary Data status.

Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 05 equals 5.0). Document promoted to Product Preview.

34/36

Page 35

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

M50LPW116

Note: Drawing is not to scale.

1 N

N/2

DIE

TSOP-a

LA1 α

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechan ic al Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0 .0472

A1 0.050 0.15 0 0.0020 0.0059

millimeters inches

A2 0.950 1.05 0 0.0374 0.0413

B 0.170 0.270 0.0067 0.0106 C 0.100 0.210 0.0039 0.0083 D 1 9.800 20.200 0.7795 0.7953

D1 18.300 18.500 0.7205 0.7283

E 9.900 10.100 0.3898 0.3976

e 0.500 – – 0.0197 – –

L 0.500 0.700 0.0197 0.0276

0° 5° 0° 5°

N40 40

CP 0.100 0 .0039

35/36

Page 36

M50LPW116

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