Datasheet M50LPW002 Datasheet (SGS Thomson Microelectronics)

3V Supply Low Pin Count Flash Memory

FEATURES SUMMARY

■ SUPPLY VOLTAGE

= 3 V to 3.6 V for Program, Erase and

–V

CC

Read Operations

–V

= 12 V for Fast Program and Fast Erase

PP

(optional)

■ TWO INTERFACES

– Low Pin Count (LPC) Standard Interface for

embedded operation with PC Chipsets.

– Address/Address Multiplexed (A/A Mux)

Interface for programming equipment
compatibility.

■ LOW PIN COUNT (LPC) HARDWARE

INTERFACE MODE
– 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block

Protection
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for

platform design flexibility
– Synchronized with 33 MHz PCI clock

■ PROGRAMMING TIME

– 10 µs typical
– Quadruple Byte Programming Option

■ 7 MEMORY BLOCKS

– 1 Boot Block (Top Location)
– 4 Main Blocks and 2 Parameter Blocks

■ PROGRAM/ERA SE CON T ROL LER

– Embedded Byte Program, Block Erase and

Chip Erase algorithms
– Status Register Bits

■ PROGRAM and ERASE SUSPEND

– Read other Blocks during Program/Erase

Suspend
– Program other Blocks during Erase Suspend

■ FOR USE in PC BIOS APPLICATIONS

M50LPW002

2 Mbit (256Kb x8, Boot Block)

PRELIMINARY DATA

Figure 1. Packages

PLCC32 (K)

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: 31h

May 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/39

M50LPW002

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Low Pin Count (LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address/Address M ultiplexe d (A/A Mux) Sign al Descrip tions . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Supply Signal Description s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memory Identification Input Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Low Pin Count (LPC) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Read Field Definitions (LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Write Field Definitions (LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Address/Address M ultiplexe d (A/A Mux) B us Operati ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

A/A Mux Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Manufacturer and Device Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS. . . . . . . . . . . . . . . . . . . . . . . 18

Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

General Purpose Input Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Low Pin Count Register Configuration Map

(1)

Lock Register Bit Definitions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General Purpose Input Register Definition

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AC Measurement Conditions (LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AC Measurement Conditions (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Device Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clock Characteristics (LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AC Signal Timing Characteristics (LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/39

M50LPW002

Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6

Read AC Characteristics (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Write AC Characteristics (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6

PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data . . . . . . . . . . . . . . . . . 36

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3/39

M50LPW002

SUMMARY DESCRIPTION

The M50LPW002 is a 2 Mbit (256Kb x8) non-vola­tile memory that can be read, erased and repro­grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines an optional 12V power supply can be used to
reduce the programming and the erasing times.

The memory is divided into blocks that can be
erased independently so it is pos sible to pres erve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro­gram or Erase commands from modifying the
memory. Program and Erase com m ands are wri t­ten to the Command Interface of t he memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase op eration can be de tected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.

The device features an asymmetrical blocked ar­chitecture. The device has an array of 7 blocks:

■ 1 Boot Block of 16 KByte

■ 2 Parameter Blocks of 8 KByte each

■ 1 Main Block of 32 KByte

■ 3 Main Blocks of 64 KByte each

Two different bus interfaces are supported by t he
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
current PC Chipsets; the M50LPW002 acts as the
PC BIOS on the Low P in Count bus for these P C
Chipsets.

The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Int erface, is design ed t o
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.

The memory is delivered with al l the bits erased
(set to 1).

Figure 2. PLCC Connections

A/A Mux A/A Mux

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

GPI1
GPI0

WP

TBL

ID3
ID2
ID1
ID0

LAD0

GPI2

9

LAD1

DQ1

RPA8VPPV

A9

RP

VPPV

GPI3

1

32

M50LPW002

17

SS

V

V

SS

RFU

LAD3

DQ3

DQ4

LAD2

DQ2

CC

CC

RC

CLK

RFU

DQ5

A10

GPI4

25

RFU

DQ6

IC (VIL)
NC
NC
V

SS

V

CC

INIT
LFRAME
RFU
RFU

IC (VIH)
NC
NC
V

SS

V

CC

G
W
RB
DQ7

A/A MuxA/A Mux

AI05744

Note: Pi ns 27 and 28 are not interna l l y co nnected.

4/39

M50LPW002

Figure 3. Logic Diagram (LPC Interface)

V

ID0-ID3

GPI0-

GPI4

LFRAME

CLK

IC

RP

INIT

V

4

5

M50LPW002

V

CC

SS

PP

4

LAD0­LAD3

WP

TBL

AI05742

Figure 4. Logic Diagram (A/A Mux Interface)

V

A0-A10

RC

IC

W

RP

V

11

M50LPW002

G

V

CC

SS

PP

8

DQ0-DQ7

RB

AI05743

Table 1. Signal Names (LPC Interface)

LAD0-LAD3 Input/Output Communications
LFRAME
ID0-ID3 Identification Inputs
GPI0-GPI4 General Purpose Inputs
IC Interface Configuration
RP
INIT
CLK Clock
TBL
WP

RFU

V

CC

V

PP

Input Communication Frame

Interface Reset
CPU Reset

Top Block Lock
Write Protect
Reserved for Future Use. Leave

disconnected
Supply Voltage
Optional Supply Voltage for Fast

Erase Operations

Table 2. Signal Names (A/A Mux Interface)

IC Interface Configuration
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
G
W
RC
RB
RP
V

CC

V

PP

V

SS

NC Not Connected Internally

Output Enable
Write Enable
Row/Column Address Select
Ready/Busy Output
Interface Reset
Supply Voltage
Optional Supply Voltage for Fast

Program and Fast Erase Operations
Ground

V

SS

NC Not Connected Internally

Ground

5/39

M50LPW002

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con­figur a tion Pin, IC.

The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address M ultiplexed (A/A Mux)
Signal Descriptions section below. The supply sig­nals are discussed in the Supply S ignal Descrip­tions section below.

Low Pin Count (LPC) Signal Descriptions

For the Low Pin Count (LPC) Interface see Figure
3, Logic Diagram, and Table 1, Signal Names.

Input/Output Communications (LAD0-LAD3). All
Input and Output Communication with the memory
take place on these pi ns. Addresses and Data for
Bus Read and Bus W rite operations are en coded
on these pins.

Input Communication Frame (LFRAME

Input Communication Frame (LFRAME
the start of a bus operation. When Input Commu­nication Frame is Low, V

, on the rising edge of

IL

the Clock a new bus operat ion is in itiated. If Input
Communication Frame is L ow, V

IL

operation then the operation is aborted. When In­put Communication Frame is High, V
rent bus operation is proceeding or the bus is idle.

Identification Inputs (ID0-ID3). The Identification
Inputs (ID0-ID3) allow to address up to 16
memories on a bus. The value on addresses A18­A21 is compared to the hardware strapping on the
ID0-ID3 pins to select which memory is being

addressed. For an address bit to be ‘1’ the
correspondent ID pin c an be left floating or driven
Low, VIL; an internal pull-down resistor is included
with a value of R

. For an address bit to be ‘0’ the

IL

correspondent ID pin must be driven High, V
there will be a leakage current of I
pin when pulled to V

; see Table 20.

IH

LI2

By convention t he boot memory must h ave ID0­ID3 pins left floating or driven Low, V
‘1111’ value on A18-A21 and all additional
memories take sequential ID0-ID3 configuration,
as shown in Table 3.

General Purpose Inputs (GPI0-GPI4). The Gener­al Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Reg­ister holds the values on these pins. The pins must
have stable data from before the start of the cycle
that reads the General Purpose Input Register un­til after the cycle is complete. These pins must not
be left to float, they should be driven Low, V
High, V

.

IH

Interface Configuration (IC). The Interface Con­figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A

). The

) signals

, during a bus

, the cur-

IH

IH

through each

and a

IL

or

IL,

Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be change d. The state of
the Interface Configuration, IC, should not be
changed during operation.

To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
driven Low, V

; to select the Address/Address

IL

Multiplexed (A/A Mux) Interface t he pin should be
driven High, V
included with a value of R
current of I

. An internal pull-down resistor is

IH

through each pin when pulled to VIH;

LI2

; there will be a leakage

IL

see Table 20.

Interface Reset (RP

). The Interface Reset (RP)

input is used to reset the memory. When Interface
Reset (RP

) is set Low, VIL, the memor y i s i n R ese t
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP
set High, V

, the memory is in no rmal operat ion.

IH

After exiting Reset mode, the memory enters
Read mode.

CPU Reset (INIT

). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset .
It behaves identically to Interface Reset, RP
the internal Reset lin e is the logical OR (elec tric al
AND) of RP

and INIT.

Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.

Top Block Lock (TB L

). The Top Block Lock

input is used to pre vent the Top Block (Block 6)
from being chan ged. When Top Block Loc k, TBL
is set Low, V

, Program and Erase operations in

IL

the Top Block have no effect, regardless of the
state of the Lock Register. When To p Bloc k Loc k,

, is set High , VIH, the protection of the Block is

TBL

;

determined by the Lock Register. The state of Top
Block Lock, TBL

, does not affect the protection of

the other blocks (Blocks 0 to 5).
Top Block Lock, TBL

, must be set prior to a Pro­gram or Erase operation is initiated and must not
be changed until the o peration completes or un­predictable results may occur. Care should be tak­en to avoid unpredictable behavior by changing
TBL

during Program or Erase Suspend.

Write Protect (WP

). The Write Protect input is

used to prevent the blocks 0 to 5 from being
changed. When Write Protect, WP

, is s et Lo w, VIL,
Program and Erase operations in these blocks
have no effect, regardless of the state of the Lock
Register. When Write Protect, WP

, the protection of the block is determined by

V

IH

, is set High,

the Lock Regist er. T he st ate of Write Prot ect, WP
does not affect the protection of the Top Block
(Block 6).

is

, and

,

,

6/39

M50LPW002

Write Protect, WP, must be set prior to a Program
or Erase operation is initiated and must not be
changed until the operation completes or unpre­dictable results may occur. Care should be taken
to avoid unpredictable behavior by changing WP
during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do
not have assigned func tions i n this revision of the
part. They must be left disconnected.

Address/Address Multiplexed (A/A Mux)
Signal Descriptions

For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 4, Logic Diagram, and Table
2, Signal Names.

Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A17). They are
latched during any bus operation by the Row/ Col­umn Address Select input, RC

.

Data Inputs/Outputs (DQ0-DQ7). The Data In­puts/Outputs hold the data that is written to or read
from the memory. They output the data s tored at
the selected address during a Bus Read opera­tion. During Bus Write operations they represent
the commands sent t o the Command Interface of
the internal state machine. The Data I nputs/Out­puts, DQ0-DQ7, are latched during a Bus Write
operation.

Output Enable (G

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Com­mand Interf a c e .

Row/Column Address Select (RC

). The Row/

Column Address Select input selects whether the
Address Inputs should be latched into the Row
Address bits (A0-A10) or the Column Address bits
(A11-A17). The Row Address bits are latched on
the falling edge of RC

whereas the Column

Address bits are latched on the rising edge.

Ready/Busy Output (RB

). The Ready/Busy pin

gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, V

OL

, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase

Suspend command. When Ready/Busy is High,
V

, the memory is ready for any Rea d, Program

OH

or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfac­es.

Supply Voltage. The VCC Supply Voltage

V

CC

supplies the power for all operations (Read, Pro­gram, Erase etc.).

The Command Interface is disabled when the V

CC

Supply Voltage is less than the L ockout Voltage,
V

. This prevents Bus Write operations from

LKO

accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the
memory contents being altered will be invalid.
After V

becomes valid the Comma nd Interface

CC

is reset to Read mode.
A 0.1µF capacitor should be connected between

the V

Supply Voltage pins and the VSS Ground

CC

pin to decouple the current surges from the power
supply. Both V

Supply Voltage pins must be

CC

connected to the power supply. The PCB track
widths must be sufficient to carry the currents
required during program and erase operations.

Optional Supply Voltage. The VPP Optional

V

PP

Supply Voltage pin is used to select the Fast
Program (see the Quadruple Byte Program
Command description) and Fast Erase options of
the memory and to protect the memory. When V
< V

Program and Erase operations cannot be

PPLK

PP

performed and an error is reported in the Sta tus
Register if an attempt to change the memory
contents is made. When V

= VCC Program and

PP

Erase operations take place as normal. When
V

PP

= V

Fast Program (if a Quadruple Byte

PPH

Program Command is performed ) and Fast Erase
operations are used. Any other voltage input to

will res ult in undefined beha vior and should

V

PP

not be used.
V

should not be set to V

PP

for more than 80

PPH

hours during the life of the memory.

V

Ground. VSS is the reference for al l the vol t-

SS

age measurements.

7/39

M50LPW002

Table 3. Memory Identification Input Configuration

Memory Number ID3 ID2 ID1 ID0 A21 A20 A19 A18

V

1 (Boot)

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

or floating VIL or floating VIL or floating VIL or floating

IL

V

or floating VIL or floating VIL or floating V

IL

V

or floating VIL or floating V

IL

V

or floating VIL or floating V

IL

V

or floating V

IL

V

or floating V

IL

V

or floating V

IL

V

or floating V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

IH
IH
IH

IH

VIL or floating VIL or floating VIL or floating
VIL or floating VIL or floating V
VIL or floating V
VIL or floating V

V

IH

V

IH

V

IH

V

IH

IH
IH

VIL or floating VIL or floating
VIL or floating V

V

IH

V

IH

IH

IH

VIL or floating VIL or floating
VIL or floating V

V

IH

V

IH

VIL or floating

V

VIL or floating

V

VIL or floating

V

VIL or floating

V

1111

IH

1110
1101

IH

1100
1011

IH

1010
1001

IH

1000
0111

IH

0110
0101

IH

0100
0011

IH

0010
0001

IH

0000

Table 4. Block Addresses

Size

(Kbytes)

Address Range

16 3C000h-3FFFFh 6

8 3A000h-3BFFFh 5

8 38000h-39FFFh 4

32 30000h-37FFFh 3 Main Block
64 20000h-2FFFFh 2 Main Block
64 10000h-1FFFFh 1 Main Block
64 00000h-0FFFFh 0 Main Block

Note: For A18 and A19 values, ref er to Table 3.

8/39

Block

Number

Block Type

Boot Block

Parameter

Parameter

(Top)

Block

Block

BUS OPERATIONS

The two interfaces have similar bus operations but
the signals and tim ings are comple tely different.
The Low Pin Count (LPC) In terface is the usual
interface and all of the functionality of the part is
available through this interfac e. Only a subset of
functions are available through the Address/
Address Multiplexed (A/A Mux) Interface.

Follow the section Low Pin Count (LPC) Bus
Operations below and the section Address/
Address Multiplexed (A/A Mux) Interface Bus
Operations below for a description of the bus
operations on each interface.

Low Pin Count (LPC) Bus Operations

The Low Pin Count (LPC) Interface consists of
four data signals (LAD0-LAD3), one control line
(LFRAME

) and a clock (CLK). In addition
protection against accidental or malicious data
corruption can be achieved using two further
signals (TBL
(RP

and INIT) are available to put the memory into

and WP). Finally two reset signals

a known state.
The data signals, control signal and clock are

designed to be compatible with PCI electrical
specifications. The interface operates with clock
speeds up to 33MHz.

The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Low Pin Count Registers. A valid Bus
Read operation starts when Input Communication
Frame, LFRAME

, is Low, VIL, as Clock rises and
the correct Start cycle is on LAD0-LAD3. On the
following clock cycles the Host will send the Cycle
Type + Dir, Address and other control bits on
LAD0-LAD3. The memory responds by outputting
Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.

Refer to Table 5, Bus Read Field Definitions (LPC
Interface), and Figure 5, Bus Read Waveforms
(LPC Interface), for a description of the Field defi­nitions for each cl ock cycle of the tr ansfer. See Ta­ble 22, AC Signal Timing Characteristics (LPC
Interface), and Figure 10, AC Signal Timing Wave­forms (LPC Interface), for details on the timings of
the signals.

Bus Write. Bus Write operations write to the
Command Interface or Low Pin Count Registers. A
valid Bus Write operation starts when Input

M50LPW002

Communication Frame, LFRAME
Clock rises and the correct Start cycle is on LAD0­LAD3. On the following Clock cycles the Host will
send the Cycle Type + Dir, Add ress, other c ontrol
bits, Data0-Data3 and Data4-Data7 on LAD0­LAD3. The memory outputs Sync data until the
wait-states have elapsed.

Refer to Table 6, Bus Write Field Definitions (LPC
Interface), and Figure 6, Bus Write Waveforms
(LPC Interface), for a description of the Field
definitions for each clock cycle of the transfer. See
Table 22, AC Signal Timing Charac teristics (LPC
Interface), and Figure 10, AC Signal Timing
Waveforms (LPC Interface), for details on the
timings of the signals.

Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when LFRAME
V

, during the bus o peration; the m emory wi ll tri-

IL

state the Input/Output Communication pins,
LAD0-LAD3.

Note that, during a Bus Write operation, the
Command Interface starts executing the
command as soon a s the data is f ully received; a
Bus Abort during the final TAR cycles is not
guaranteed to abort the command; the bus,
however, will be released immediately.

Standby. When LFRAME
memory is put into Standb y mode where LA D0­LAD3 are put into a high-impedance state and the
Supply Current is reduced to the Standby level,
I

.

CC1

Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP
Rese t, IN IT
Low, V

, is Low, VIL. RP or IN IT must be held

, for t

IL

. The memory resets to Read

PLPH

mode upon return from Res et mo de and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 13. If RP
INIT

goes Low, VIL, during a Program or Erase
operation, the operation is aborted and the
memory cells affected no longer contain valid
data; the memory can take up to t
Program or Erase operation.

Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL
Write Protect, WP

, regardless of the state of the

Lock Registers.

, is Low, VIL, as

is driven Low,

is High, VIH, the

, or CPU

or

to abort a

PLRH

, and

9/39

M50LPW002

Table 5. Bus Read Field Definitions (LPC Interface)

Clock
Cycle

Number

Clock
Cycle

Count

Field

LAD0-

LAD3

Memory

I/O

Description

1 1 START 0000b I

CYCTY

21

PE +

0100b I

DIR

3-10 8 ADDR XXXX I

11 1 TAR 1111b I

12 1 TAR

1111b

(float)

13-14 2 WSYNC 0101b O

15 1 RSYNC 0000b O

16-17 2 DATA XXXX O

18 1 TAR 1111b O

19 1 TAR

1111b

(float)

N/A

On the rising edge of CLK with LFRAME

Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 0b for read. Bit 0 is ‘0’.

A 32-bit address phase is transferred starting with the most
significant nibble first. A23-A31 must be set to 1. A22 = 1 for
Array, A22 = 0 for registers access. For A18-A21 values,
refer to Table 3.

The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.

The LPC Flash Memory takes control of LAD0-LAD3 during

O

this cycle.
The LPC Flash Memory drives LAD0-LAD3 to 0101b (short

wait-sync) for two clock cycles, indicating that the data is not
yet available. Two wait-states are always included.

The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.

Data transfer is two CLK cycles, starting with the least
significant nibble.

The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.

The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.

Figure 5. Bus Read Waveforms (LP C Interface)

CLK

LFRAME

CYCTYPE

+ DIR

1182322

ADDR TAR SYNC DATA TAR

10/39

LAD0-LAD3

Number of
clock cycles

START

AI04429

Table 6. Bus Write Field Definitions (LPC Interface)

Clock
Cycle

Number

Clock
Cycle

Count

Field

LAD0-

LAD3

Memory

I/O

M50LPW002

Description

1 1 START 0000b I

CYCTY

21

PE +

011Xb I

DIR

3-10 8 ADDR XXXX I

11-12 2 DATA XXXX I

13 1 TAR 1111b I

14 1 TAR

1111b

(float)

15 1 SYNC 0000b O

16 1 TAR 1111b O

17 1 TAR

1111b

(float)

N/A

On the rising edge of CLK with LFRAME

Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 1b for write. Bit 0 is don’t
care (X).

A 32-bit address phase is transferred starting with the most
significant nibble first. A23-A31 must be set to 1. A22 = 1 for
Array, A22 = 0 for registers access. For A18-A21 values,
refer to Table 3.

Data transfer is two cycles, starting with the least significant
nibble.

The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.

The LPC Flash Memory takes control of LAD0-LAD3 during

O

this cycle.
The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command.
The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle.
The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

Figure 6. Bus Write Waveforms (LPC Interface)

CLK

LFRAME

LAD0-LAD3

Number of
clock cycles

START

CYCTYPE

+ DIR

1182212

ADDR DATA TAR SYNC TAR

AI04430

11/39

M50LPW002

Address/Address Multiplexed (A/A Mux) Bus
Operations

The Address/Address Multiplexed (A/A Mux)
Interface has a more traditional style interface.
The signals consist of a multiplexed address
signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC
signal, RP

, can be used to reset the memory.

, G, W). An additional

The Address/Address Multiplexed (A/A Mux)
Interface is included for use by Flash
Programming equipment for faster factory
programming. Only a subset of the features
available to the Low Pin Count (LPC) Interface are
available; these include all the Commands but
exclude the Security features and other registers.

The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are
unprotected. It is not possible to protect any blocks
through this interface.

Bus Read. Bus Read operations are used to
output the contents of the Memory Array, the
Electronic Signature and the Status Register. A
valid Bus Read operation begins by latching the
Row Address and Column Address signals into
the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC
Write Enable (W
be High, V

) and Interface Reset (RP) must

, and Output Enable, G, Low, VIL, in

IH

. Then

order to perform a Bus Read operation. The Data
Inputs/Outputs will output the value, see Figure
12, Read AC Waveforms (A/A Mux Interface), and
Table 25, Read AC Characteristics (A/A Mux
Interface), for details of when the output becomes
valid.

Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column
Address Select RC
the Data Inputs/Outputs; Output Enable, G
Interface Reset, RP
Enable, W

, must be Low, VIL. The Data Inputs/

. The data should be set up on

, and

, must be High, VIH and Write

Outputs are latched on the rising edge of Write
Enable, W

. See Figure 1 3, Write AC Waveforms
(A/A Mux Interface), and Table 26, Write AC
Characteristics (A/A Mux Interface), for details of
the timing requirements.

Output Disa bl e . The data outputs are high-im­pedance when the Output Enable, G

, is at VIH.

Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP
held Low, V

for t

IL

is Low, VIL. RP must be

. If RP is goes Low, VIL,

PLPH

during a Program or Erase operation, the
operation is aborted and the memory cells affected
no longer contain valid data; the memory can take
up to t

to abort a Program or Erase operation.

PLRH

Table 7. A/A Mux Bus Operations

Operation G W RP

Bus Read
Bus Write
Output Disable
Reset

V

IL

V

IH

V

IH

V

or V

IL

IH

V

IH

V

IL

V

IH

VIL or V

Table 8. Manufacturer and Device Codes

Operation G

Manufacturer Code
Device Code

V

IL

V

IL

W RP A17-A1 A0 DQ7-DQ0

V

IH

V

IH

V

PP

V

IH

V

IH

V

IH

IH

V

IL

V

IH

V

IH

Don’t Care Data Output

VCC or V

Don’t Care Hi-Z
Don’t Care Hi-Z

V
V

PPH

IL

IL

V

IL

V

IH

DQ7-DQ0

Data Input

20h
31h

12/39

M50LPW002

Table 9. Commands

Bus Write Operations

Command

Cycles

Read Memory Array 1 X FFh
Read Status Register 1 X 70h

Read Electronic Signature

1X 90h
1X 98h
2X 40hPAPD

Program

2X 10hPAPD
Quadruple Byte Program 5 X 30h
Chip Erase 2 X 80h X 10h
Block Erase 2 X 20h BA D0h
Clear Status Register 1 X 50h
Program/Erase Suspend 1 X B0h
Program/Erase Resume 1 X D0h

1X 00h

1X 01h
Invalid/Reserved

1X 60h

1X2Fh

1XC0h

Note: X Don’t Care, PA Program Address, PD Program Data, A

Read Memory Array: After a Read M em ory Array command, read the memory as normal unti l another comm and is issued.
Read Status Register: After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature: After a Read E l ectronic S i gnature c ommand, read Manufacturer C ode, Device Code unt i l another co m-

mand is issued.
Block Erase, Byt e Pr og ram : After these commands, read the Status Register until the command completes and another command
is issued.
Quadruple Byte Program: This command is only valid in A/A Mux mode. Addresses A
differing only for address bit A0 and A1. After this command read the Status Register until the command completes and another com­mand is issued.
Chip Era se: This command is only valid in A/A Mux mode. After this command, read the Status Register until the command completes
and another command is issued.

Clear Status Register: After th e Clear Status Register comman d bi t s 1, 3, 4 and 5 in the Status Reg i st er are reset to ‘ 0’ .
Program/Erase Susp end: After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status

Register, Program (during Era se suspend ) and Program/ Erase resum e commands.
Program /Erase Re sume: Af ter the P rogr am /Era se Re sume co mmand t he su sp ended P rogra m/E ras e o perat ion re sum es, read th e
Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.

Invalid/Reserved: Do not use Invalid or Reserved commands.

1st 2nd 3rd 4th 5th

Addr Data Addr Data Addr Data Addr Data Addr Data

A

PD

1

Consecut i ve Addresses, BA Any address in the block .

1,2,3,4

A

PD

2

, A2, A3 and A4 must be consecutive addresses

1

A

PD

3

A

PD

4

13/39

M50LPW002

COMMAND INTERFACE

All Bus Write operations to the memory are
interpreted by the Command Interface.
Commands consist of one or more sequential Bus
Write operations.

After power-up or a Reset operation the memory
enters Read mode.

The commands are summarized in Table 9,
Commands. Refer to Table 9 in conjunction with
the text descriptions below.

Read Memory A rray Command. The Read Mem­ory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is is­sued the memory remains in Read mode until an­other command is issued. From Read mode Bus
Read operations will access the memory array.

While the Program/Erase Controller is executing a
Program or Erase operation the m emory will not
accept the Read Memory Array command until the
operation completes.

Read Statu s Registe r Co mm an d . The Read Sta­tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera­tions read the Status Register until another com­mand is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.

Read Electronic Signature Co mmand. The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read
Electronic Signature command. Once the
command is issued subsequent Bus Read
operations read the Manufacturer Code or the
Device Code until another command is issued.

After the Read Electronic Signature Command is
issued the Manufacturer Code and Devi ce Code
can be read using Bus Read op erations us ing the
addresses in Table 10.

Table 10. Read Electronic Signature

Code Address Data

Manufacturer Code 00000h 20h
Device Code 00001h 31 h

Note: For A18 and A19 values, ref er to Table 3.

Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write
operations are required to issue the command; the

second Bus Write cycle latches the address and
data in the internal state m achine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus R ead operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.

If the address falls in a pro tected block then the
Program operation will abort, the data in the
memory array will no t be changed and the S tatus
Register will output the error.

During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Program
times are given in Table 23.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. One of the
Erase commands must be used to set all of the
bits in the block to ‘1’.

See Figure 14, Program Flowchart and Pseudo
Code, for a suggested flowchart on using the
Program command.

Quadruple Byte Program Command. The Qua­druple Byte Program Comman d c an be only used
in A/A Mux mode to program four adjacent bytes
in the memory array at a time. The four bytes must
differ only for the addresses A0 and A1.
Programming should not be attempted when V
is not at V
if V

is below V

PP

. The operation can also be executed

PPH

, but result could be uncertain.

PPH

PP

Five Bus Write operations are required to issue the
command. The second, the third and the fourth
Bus Write cycle latches respectively the address
and data of the first, the second and the third byte
in the internal state machine. The fifth Bus Write
cycle latches the address and data of the fourth
byte in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus R ead operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.

During the Quadruple Byte Program operation the
memory will only accept the Read Status register
command and the Program/Erase Suspe nd com­mand. All other commands will be ignored. Typical
Quadruple Byte Program times are given in Ta ble

23.
Note that the Quadruple Byte Program comm and

cannot change a bit set to ‘0’ back to ‘1’ and
attempting to do so will not cause any modification
on its value. An Erase command mus t be used to
set all of the bits in the block to ‘1’.

14/39

M50LPW002

See Figure 15, Quadruple Byte Program Flow­chart and Pseudo Code (A/A Mux Interface Only),
for a suggested flowchart on using the Quadruple
Byte Program command.

Chip Erase Command. The Chip Erase com­mand can be used in A/A Mux mode to erase t he
entire chip at a time. Erasing should not be at­tempted when V
can also be executed if V

is not at V

PP

PPH

is b elow V

PP

. The operation

, but re-

PPH

sult could be uncertain. Two Bus Write operations
are required to issue the com mand and start the
Program/Erase Controller. Once the command is
issued, subsequent Bus Read operations read the
Status Register. (See the section on the Status
Register for details of the defini tions of the S tatus
Register bits.)

During the Chip Erase operation, the memory only
accepts the Read Status Register command. All
other commands are ignored.

Typical Chip Erase times are given in Table 23.
The Chip Erase command sets all of the bits in the

memory to ‘1’. See Figure 17, Chip Erase Flow­chart and Pseudo Code, for a suggested flowchart
when using the Chip Erase command.

Block Erase Command. The Block Erase com­mand can be used to erase a block. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the block address
in the internal stat e machine and starts th e Pro­gram/Erase Controller. Once the command is is­sued subsequent Bus Read ope rations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.

If the block is protected then the Erase o peration
will abort, the data in the block will not be changed
and the Status Register will output the error.

During the Erase operation the memory only
accepts the Read Status Regi ster command and
the Program/Erase Su spend command. All ot her
commands are ignored. Typical Erase times are
given in Table 23.

The Erase command sets all of the bits in the block
to ‘1’. All previous data in the block is lost.

See Figure 18, Block Erase Flowchart and Pseudo
Code, for a suggested flowchart on using the
Erase command.

Clear Status Register Command. The Clear Sta­tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. Once the command is issued the mem-

ory returns to its previous mode, subs equent Bus
Read operations continue to output the same data.

The bits in the Status Register are stic ky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta­tus Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.

Program/Erase Suspend Command. The Pro­gram/Erase Suspend command can be used to
pause a Program or Erase operation. One Bus
Write cycle is required to issue the Program/Erase
Suspend command and pause the Program/Erase
Controller. Once the com man d i s issued it is nec­essary to poll the Program/Erase Controller Status
bit to find out when th e Program/Erase Controller
has paused; no other commands will be acc ept ed
until the Program/Erase Controller has paused.
After the Program/Erase Controller has paused,
the memory will continue to output the Status Reg­ister until another command is issued.

During the polling period between issuing the
Program/Erase Suspend command and the
Program/Erase Controller pausing it is possible for
the operation to complete. Once Program/Erase
Controller Status bit indicates that the Program/
Erase Controller is no longer active, the Program
Suspend Status bit or the Erase Suspend Status
bit can be used to d etermine if the opera tion has
completed or is suspended. For timing on the
delay between issuing the Program/Erase
Suspend command and the Program/Erase
Controller pausing see Table 23.

During Program/Erase Suspend the Read
Memory Array, Read Status Register, Read
Electronic Signature and Program/Erase Resume
commands will be accepted by the Command
Interface. Additionally, if the suspe nded operation
was Erase then the Program command will also be
accepted; on ly the blocks n ot being e rased may be
read or programmed correctly.

See Figure 16, Program Suspend and Resume
Flowchart, and Pseudo Code, and Figure 19,
Erase Suspend and Resume Flowchart, and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command .

Program / Erase Resum e Command. The Pro­gram/Erase Resume command can be used to re­start the Program/Erase Controller after a
Program/Erase Suspend has p aused it. One Bus
Write cycle is required to issue the Program/Erase
Resume command. O nc e the command is iss ued
subsequent Bus Read operations read the Status
Register.

15/39

M50LPW002

STATUS REGISTER

The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey
different information and errors on the operation.

To read the Status Register the Read Status
Register command can be issued. The Status
Register is automatically read after Program,
Erase and Program/Erase Resume commands
are issued. The Status Register c an be read from
any address.

The Status Register bits are summarized in Table
11, Status Register Bits. Refer to Table 11 in con­junction with the text descriptions below.

Program/Erase Controller Status (Bit 7). The Pro­gra m/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is

‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac­tive.

The Program/Erase Controller Status is ‘0’ imme­diately after a Program/Erase Su spend c om m and
is issued until the Program/Erase Controller paus­es. After the Program/Erase Controller pauses the
bit is ‘1’.

During Program and Erase operation the Pro­gram/Erase Controller Status bit can be pol led to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro­gram/Erase Controller completes the operation
and the bit is ‘1’.

After the Program/Erase Cont roller completes its
operation the Erase Status, Prog ram Status, V
Status and Block Pr otec tion S tatus b its should be
tested for errors.

Erase Suspend Status (Bit 6). The Erase Sus­pend Status bit indicates that an Erase o peration
has been suspended and is waiting to be re­sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con­troller Status bit is ‘1’ (Program/Erase Controller
inactive); after a Program/Erase Suspend com­mand is issued the memory may still complete the
operation rather than entering the Suspend mode.

When the Erase Suspend Status bit is ‘0’ the Pro­gram/Erase Controller is active or has com pleted
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.

When a Program/Erase Re sume command is is­sued the Erase Suspend Status bit returns to ‘0’.

Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block and

PP

still failed to verify that the block has erased cor­rectly. The Erase Status bit should be read onc e
the Program/Erase Controller Status bit is ‘1’ (Pro­gram/Erase Controller inactive).

When the Erase Status bit is ‘0’ the memory has
successfully verified that the block has erased cor­rectly; when the Erase Status bit is ‘1’ the Pro­gram/Erase Controller has applied the maximum
number of pulses to the block and still failed to ver­ify that the block has erased correctly.

Once the Erase Status bit is set to ‘1’ it can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is­sued, otherwise the new command will appear to
fail.

Program Status (Bit 4). The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
byte and still failed to verify that the byte has pro­grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).

When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has pro­grammed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte an d still
failed to verify that the byte has program med c or­rectly.

Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com­mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.

Status (Bit 3). The VPP Status bit can be

V

PP

used to identify an invalid v oltage on the V
during Program and Erase operations. The V

PP

pin

PP

pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc­cur if V

becomes invalid during a Program or

PP

Erase operation.
When the V

V

pin was sampled at a valid vol tag e; w hen the

PP

Status bit is ‘1’ the VPP pin has a voltage that

V

PP

is below the V

Status bit is ‘ 0’ the vol tage on the

PP

Lockout Voltage, V

PP

PPLK

, the
memory is protected; Program and Erase opera­tion cannot be performed.

Once the V

Status bit set to ‘1’ it can only be re-

PP

set to ‘0’ by a Clear Status Register command or a
hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is­sued, otherwise the new command will appear to
fail.

16/39

M50LPW002

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper­ation has been suspended and is waiting to be re­sumed. The Program Suspend Status should only
be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control­ler inactive); after a Program/Erase Suspend com­mand is issued the memory may still complete the
operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet­ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re­sume command.

When a Program/Erase Re sume command is is­sued the Program Suspend Status bit returns to
‘0’.

gram or Erase operation has tried to modify the
contents of a protected block. When the Block Pro­tection Status bit is to ‘0’ no Program or Erase op­erations have been attempted t o protec ted blocks
since the last Clear Status Register command or
hardware reset; when the Block Protec tion Sta tus
bit is ‘1’ a Program or Erase operation has been at­tempted on a protected block.

Once it is set to ‘ 1’ the Block Protection Stat us bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset . If it is set to ‘1’ it
should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to fail.

Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.

Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.

Block Protection Status (Bit 1). The B lock Pro­tection Status bit can be used to identify if the Pro-

Table 11. Status Register Bits

Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Program active ‘0’
Program suspended ‘1
Program completed successfully ‘1’
Program failure due to V
Program failure due to Block Protection (LPC Interface only) ‘1’
Program failure due to cell failure ‘1’

Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Block Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

PP

Error

‘1’

1

X
X
X
X
X
X

‘0’ ‘0’ ‘0’ ‘0’ ‘0’

1

‘0’ ‘0’ ‘0’ ‘1’ ‘0’

1

‘0’ ‘0’ ‘0’ ‘0’ ‘0’

1

‘0’ ‘0’ ‘1’ ‘0’ ‘0’

1

‘0’ ‘0’ ‘0’ ‘0’ ‘1’

1

‘0’ ‘1’ ‘0’ ‘0’ ‘0’

Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Block Erase failure due to V
Block Erase failure due to Block Protection (LPC Interface

only)
Erase failure due to failed cell(s) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’

Note: 1. For Program o perations during Erase Suspend Bit 6 is ‘1’, otherwise Bi t 6 is ‘0’.

PP

Error

‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’

‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’

17/39

M50LPW002

LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS

When the Low Pin Count Interface is selected sev­eral additional registers can be accessed. These
registers control the protection status of the blocks
and read the General Purpose Input pins. See Ta­ble 12 for an example of the Register Conf igura­tion map, valid for the boot me mory, i.e. ID0-ID3
floating or driven L

, VIL and A18-A21 set to ‘1’.

OW

Lock Registers

The Lock Registers control the protection status of
the blocks. Each block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the W rite Lock Bit, the
Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bi t is set, ‘1’, further modifications
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.

See Table 13 for details on the bit definitions of the
Lock Registers.

Write Lock. The Write Lock Bit determines
whether the contents of the block can be modified
(using the Program or Erase Command). When
the Write Lock Bit is set, ‘1’, the block is write pro­tected; any operations that attempt to change the
data in the block will fail and the Status Register
will report the error. When the Write Lock Bit is re­set, ‘0’, the block is not write protected through the
Lock Register and may be modi fied unless write
protected through some other means.

When V

is less than V

PP

all blocks are pro-

PPLK

tected and cannot be modified, regardl ess of the
state of the Write Lock Bit. If Top Block Lock, TBL
is Low, V

, then the Top Block (Block 6) is write

IL

protected and cannot be modified. Similarly, if

Write Protect, WP
5 are write protected and cannot be modified.

After power-up or reset the Write Lock Bit is al­ways set to ‘1’ (write protected).

Read Lock. The Read Lock bit determines
whether the contents of the block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read prot ected; an y operat ion that
attempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the block return the data pro­grammed into the block as expected.

After power-up or reset the Read Lock B it is al­ways reset to ‘0’ (not read protected).

Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim­ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required be­fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write L ock, Read
Lock and Lock Down Bits can be changed.

General Purpose Input Register

The General Purpose Input Register holds the
state of the General Purpose Input pins, GPI0­GPI4. When this register is read, the state of these
pins is returned. This register is read-only and writ­ing to it has no effect.

The signals on the General Purpose Input pins
should remain constant throughout the whole Bus
Read cycle in order to guarantee that the correct

,

data is read.

, is Low, VIL, then the blocks 0 to

Table 12. Low Pin Count Register Configuration Map

Mnemonic Register Name

T_BLOCK_LK Top Block Lock Register (Block 6) FFBFC002h 01h R/W
T_MINUS01_LK Top Block [-1] Lock Register (Block 5) FFBFA002h 01h R/W
T_MINUS02_LK Top Block [-2] Lock Register (Block 4) FFBF8002h 01h R/W
T_MINUS03_LK Top Block [-3] Lock Register (Block 3) FFBF0002h 01h R/W
T_MINUS04_LK Top Block [-4] Lock Register (Block 2) FFBE0002h 01h R/W
T_MINUS05_LK Top Block [-5] Lock Register (Block 1) FFBD0002h 01h R/W
T_MINUS06_LK Top Block [-6] Lock Register (Block 0) FFBC0002h 01h R/W

GPI_REG General Purpose Input Register FFBC0100h N/A R

Note: 1. T hi s map is refe rred to the boo t memory (ID0-ID3 floating or dri ven, LOW, VIL and A18-A21 set to ‘1’).

18/39

(1)

Memory

Address

Default

Value

Access

M50LPW002

Tabl e 13. Lock Re gister Bit Definitions

(1)

Bit Bit Name Value Function

7-3 Reserved

‘1’ Bus Read operations in this Block always return 00h.

2 Read-Lock

Bus read operations in this Block return the Memory Array contents. (Default

‘0’

value).
Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset

1 Lock-Down

to ‘0’ following a Reset (using RP
Read-Lock and Write-Lock can be changed by writing new values to them. (Default

‘0’

value).
Program and Erase operations in this Block will set an error in the Status Register.

‘1’

The memory contents will not be changed. (Default value).

or INIT) or after power-up.

0 Write-Lock

Program and Erase operations in this Block are executed and will modify the Block

‘0’

contents.

Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-6] Lock Reg-

Table 14. General Purpose Input Regi s te r D ef i ni tion

ister (T_MINUS06_LK).

(1)

Bit Bit Name Value Function

7-5 Reserved

Input Pin GPI4 is at V

‘1’

4 GPI4

Input Pin GPI4 is at V

‘0’

Input Pin GPI3 is at V

‘1’

3 GPI3

Input Pin GPI3 is at V

‘0’

Input Pin GPI2 is at V

‘1’

2 GPI2

Input Pin GPI2 is at V

‘0’

Input Pin GPI1 is at V

‘1’

1 GPI1

Input Pin GPI1 is at V

‘0’

Input Pin GPI0 is at V

‘1’

0 GPI0

Input Pin GPI0 is at V

‘0’

Note: 1. Applies to t he Gener al P urpose I n put Register (G P I_REG) .

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

19/39

M50LPW002

MAXIMUM RATIN G

Stressing the device ab ove the rating listed in t he
Absolute Maximum Ratings table m ay cause per­manent damage to the device. Exposure to Abso­lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the dev ice at

Table 15. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

T

T

BIAS

STG

V

V

CC

IO

Temperature Under Bias –50 125 °C

Storage Temperature
Input or Output Voltage

Supply Voltage –0.6 4 V

(1,2)

these or any other conditions above those indicat­ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and ot her relevant quality docu­ments.

–65 150 °C

V

–0.6

CC

+0.6

V

V

PP

Note: 1. Minimum volta ge may under shoot to –2V du ri ng transition and for less than 20ns during trans i tions.

2. Maximum voltage m ay oversho ot to V

Program Voltage –0.6 13 V

+2V during transition and for less than 20ns during transitions.

CC

20/39

M50LPW002

DC AND AC PARAMETERS

This section summarizes the operat ing and mea­surement conditions, and the DC and AC charac­teristics of the device. The parameters in t he DC
and AC Characteristic tables that follow are de­rived from tests performed under the Measure-

Table 16. Operating Conditions

Symbol Parameter Min. Max. Unit

ment Conditions summarized in the relevant
tables. Designers should chec k th at the o perat ing
conditions in their circuit matc h the meas urement
conditions when relying on the quoted parame­ters.

V

CC

Supply Voltage 3.0 3.6 V
Ambient Operating Temperature (range 1) 0 70 °C

T

A

Ambient Operating Temperature (range 5) –20 85 °C

Figure 7. AC Measurement I/O Waveform (LPC Interface)

0.6 V

CC

0.2 V

CC

Input and Output AC Testing Waveform

IO < I

LO

Output AC Tri-state Testing Waveform

IO > I

LO

IO < I

0.4 V

LO

AI03404

CC

Table 17. AC Measurement Conditions (LPC Interface)

Symbol Parameter Min. Max. Unit

C

L

Load Capacitance 10 pF
Input Rise and Fall Times 1.4 ns

to 0.6V

Input Pulse Voltages
Input and Output Timing Reference Voltages

0.2V

CC

0.4V

CC

CC

V
V

21/39

M50LPW002

Figure 8. AC Measurement I/O Waveform (A/A Mux Interface)

3V

1.5V

0V

AI01417

Table 18. AC Measurement Conditions (A/A Mux Interface)

Symbol Parameter Min. Ma x. Unit

C

L

Load Capacitance 30 pF
Input Rise and Fall Times 10 ns
Input Pulse Voltages
Input and Output Timing Reference Voltages 1.5 V

Table 19. Device Impedan ce

Symbol

C

IN

C

CLK

L

PIN

Note: 1. TA=25°C, f=1 MHz

2. Sampled only, not 100% tested

3. See PCI Specificati on

Parameter

Input Capacitance
Clock Capacitance

Recommended Pin
Inductance

3

0 to 3

1

2

2

Test Condition Min Max Unit

VIN = 0V
VIN = 0V

312pF

13 pF

V

20 nH

22/39

M50LPW002

Table 20. DC Characteristics

Symbol Parameter Interface Test Condition Min Max Unit

Input High Voltage

V

IL

Input Low Voltage

A/A Mux

LPC –0.5

A/A Mux -0.5 0.8 V

V

LPC

IH

0.5 V

0.7 V

CCVCC

CCVCC

+ 0.5
+ 0.3

0.3 V

CC

V
V

V

V

V

V

IH

IL

I

V

V

V

V

PPLK

V

LKO

I

(INIT)
(INIT)

(2)

LI

I

LI2

R

IL

OH

OL

I

LO

PP1

PPH

(1)

CC1

Input High Voltage LPC 1.35

INIT

Input Low Voltage LPC –0.5

INIT
Input Leakage Current

IC, IDx Input Leakage
Current

IC, IDx Input Pull Low
Resistor

Output High Voltage

Output Low Voltage

Output Leakage Curren t

VPP Voltage
VPP Voltage (Fast

Program/Fast Erase)

(1)

VPP Lockout Voltage
VCC Lockout Volt age

Supply Current (Standby) LPC

IC, ID0, ID1, ID2, ID3 = V

LPC I

A/A Mux

LPC

A/A Mux

LFRAME

All other inputs 0.9 VCC to 0.1 V

VCC = 3.6V, f(CLK) = 33MHz

0V ≤ V

IN

≤ V

CC

CC

20 100 k

= –500µA

OH

I

= –100µA

OH

I

= 1.5mA 0.1 V

OL

I

= 1.8mA

OL

0V ≤ V

OUT

≤ V

CC

0.9 V

V

CC

– 0.4

3 3.6 V

11.4 12.6 V

1.5 V

1.8 2.3 V

= 0.9 VCC, VPP = V

CC

CC

CC

V

+ 0.5

CC

0.2 V

CC

±10

200

CC

0.45 V
±10

100

V
V

µA
µA

V

V
V

µA

µ

Ω

A

I

CC2

Supply Current (Standby) LPC

LFRAME

All other inputs 0.9 VCC to 0.1 V

= 0.1 VCC, VPP = V

VCC = 3.6V, f(CLK) = 33MHz

= VCC max, VPP = V

Supply Current

I

CC3

I

CC4

I

CC5

I

I

PP1

Note: 1. Sampled only, not 100% tested.

(Any internal operation
active)

Supply Current (Read) A/A Mux
Supply Current

(1)

(Program/Erase)
VPP Supply Current

PP

(Read/Standby)
VPP Supply Current

(1)

(Program/Erase active)

2. Input l eakage currents include High-Z output leak age for all bi-directional buffers wi th tri-st at e outputs.

LPC

A/A Mux Program/Erase Controller Active 20 mA

V

CC

f(CLK) = 33MHz

I

G

= VIH, f = 6MHz

V

PP

= 0mA

OUT

V

V

>

PP

CC

V

= V

PP

CC

= 12V ± 5%

CC

CC

CC

10 mA

60 mA

20 mA

400

40 mA

15 mA

23/39

A

µ

M50LPW002

Table 21. Clock Characteristics (LPC In terface)

Symbol Parameter Test Condition Value Unit

t

CYC

t

HIGH

t

LOW

CLK Cycle Time
CLK High Time Min 11 ns
CLK Low Time Min 11 ns

CLK Slew Rate peak to peak

Note: 1. Dev i ces on the PCI Bus must work with any clock f requency between DC and 33MHz. Below 16MHz device s may be guaranteed

by design rather than tested. Refer to PCI Specification.

Figure 9. Clock Waveform (LPC Interface)

0.6 V

CC

0.5 V

CC

0.4 V

CC

0.3 V

CC

0.2 V

CC

(1)

tCYC

tHIGH tLOW

Min 30 ns

Min 1 V/ns

Max 4 V/ns

0.4 VCC,
(minimum)

p-to-p

AI03403

24/39

Table 22. AC Signal Timing Characteristics (LPC Interface)

Symbol

t

CHQV

PCI

Symbol

t

val

Parameter Test Condition Value Unit

CLK to Data Out

M50LPW002

Min 2 ns

Max 11 ns

(1)

t

CHQX

t

CHQZ

t

AVCH

t

DVCH

t

CHAX

t

CHDX

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current s pec-

ification.

2. Applies to all inputs except CLK.

t

t

CLK to Active

on

(Float to Active Delay)
CLK to Inactive

off

(Active to Float Delay)

t

su

Input Set-up Time

t

h

Input Hold Time

(2)

(2)

Min 2 ns

Max 28 ns

Min 7 ns

Min 0 ns

Figure 10. AC Signal Timing Waveforms (LPC Interface)

CLK

tCHQV

LAD0-LAD3

tCHQZ
tCHQX

tDVCH

tCHDX

VALID

VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA

AI04431

25/39

M50LPW002

Table 23. Program and Erase Times

Parameter Interface Test Condition Min

Byte Program 10 200

V

Quadruple Byte Program A/A Mux

Chip Erase A/A Mux V

A/A Mux

Block Program (64 KBytes)

Block Erase (64 KBytes)

Program/Erase Suspend to Program pause
Program/Erase Suspend to Block Erase pause

Note: 1. TA = 25°C, VCC = 3.3V

2. This time is obtained executing the Quadruple Byte Program Command.

3. Sampled only, not 100% tested.

(3)

(3)

= 12V ± 5%

PP

= 12V ± 5% 3 sec

PP

V

= 12V ± 5%

PP

= V

V

PP

CC

V

= 12V ± 5%

PP

V

= V

PP

CC

Table 24. Reset AC Characteristics

Symbol Parameter Test Condition Value Unit

t

PLPH

t

PLRH

t

PHFL

t

PHWL

t

PHGL

Note: 1. See Chapter 4 of the PCI Speci fication.

RP or INIT Reset Pulse Width Min 100 ns

Program/Erase Inactive Max 100 ns

RP or INIT Low to Reset

Program/Erase Active Max 30

RP

or INIT Slew Rate

(1)

Rising edge only Min 50 mV/ns
RP or INIT High to LFRAME Low LPC Interface only Min 30
RP High to Write Enable or Output

Enable Low

A/A Mux Interface only Min 50

(1)

Typ

Max Unit

10 200

0.1

(2)

5

0.4 5 sec

0.75 8 sec
110sec

5

30

µ
µ

sec

µ
µ

µ

µ

µ

s

s

s
s

s

s

s

26/39

Figure 11. Reset AC Waveforms

RP, INIT

tPLPH

M50LPW002

tPHWL, tPHGL, tPHFL

W, G, LFRAME

RB

tPLRH

AI04432

27/39

M50LPW002

Table 25. Read AC Characteristics (A/A Mux Interface)

Symbol Parameter Test Condition Value Unit

t

AVAV

t

AVCL

t

CLAX

t

AVCH

t

CHAX

t

CHQV

t

GLQV

t

PHAV

t

GLQX

t

GHQZ

t

GHQX

Note: 1. G may be delayed up to t

Figure 12. Read AC Waveforms (A/A Mux Interface)

Read Cycle Time Min 250 ns
Row Address Valid to RC Low Min 50 ns
RC Low to Row Address Transition Min 50 ns
Column Address Valid to RC high Min 50 ns
RC High to Column Address Transition Min 50 ns

(1)

RC High to Output Valid Max 150 ns

(1)

Output Enable Low to Output Valid Max 50 ns
RP High to Row Address Valid Min 1

Output Enable Low to Output Transition Min 0 ns
Output Enable High to Output Hi-Z Max 50 ns
Output Hold from Output Enable High Min 0 ns

– t

CHQV

after the ri si ng edge of RC without impact on t

GLQV

CHQV

.

s

µ

A0-A10

RC

G

DQ0-DQ7

W

RP

tAVAV

ROW ADDR VALID NEXT ADDR VALID

tAVCL tAVCH

tCLAX tCHAX

tPHAV

COLUMN ADDR VALID

tCHQV

tGLQV
tGLQX

tGHQZ
tGHQX

VALID

AI03406

28/39

M50LPW002

Table 26. Write AC Characteristics (A/A Mux Interface)

Symbol Parameter Test Condition Value Unit

t

WLWH

t

DVWH

t

WHDX

t

AVCL

t

CLAX

t

AVCH

t

CHAX

t

WHWL

t

CHWH

t

VPHWH

t

WHGL

t

WHRL

t

QVVPL

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

Write Enable Low to Write Enable High Min 100 ns
Data Valid to Write Enable High Min 50 ns
Write Enable High to Data Transition Min 5 ns
Row Address Valid to RC Low Min 50 ns
RC Low to Row Address Transition Min 50 ns
Column Address Valid to RC High Min 50 ns
RC High to Column Address Transition Min 50 ns
Write Enable High to Write Enable Low Min 100 ns
RC High to Write Enable High Min 50 ns

(1)

VPP High to Write Enable High

Min 100 ns

Write Enable High to Output Enable Low Min 30 ns
Write Enable High to RB Low Min 0 ns

(1,2)

Output Valid, RB High to VPP Low

is seen as a logic i nput (VPP < 3.6V ).

PP

Min 0 ns

Figure 13. Write AC Waveforms (A/A Mux Interface)

A0-A10

RC

W

G

RB

V

PP

DQ0-DQ7

Write erase or
program setup

R1

tCLAX

tAVCL

tWHWL

tWLWH

Write erase confirm or

valid address and data

C1

R2 C2

tAVCH

tVPHWH tWHGL

D

IN1

tCHAX

tWHRL

D

IN2

Automated erase
or program delay

tCHWH

tWHDXtDVWH

Read Status

Register Data

VALID SRD

Ready to write

another command

tQVVPL

AI04194B

29/39

M50LPW002

Figure 14. Program Flow c hart and Pseudo Code

Start

LPC

Interface

Only

Write 40h or 10h

Write Address

& Data

Read Status

Register

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

NO

NO

NO

NO

NO

Suspend

Program to Protected

Block Error (1, 2)

YES

Suspend

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Program command:
– write 40h or 10h
– write Address & Data
(memory enters read status state after
the Program command)

do:
–read Status Register if Program/Erase
Suspend command given execute
suspend program loop

Loop

while b7 = 1

If b3 = 1, VPP invalid error:
– error handler

If b4 = 1, Program error:
– error handler

If b1 = 1, Program to protected block error:
– error handler

AI04433

Note: 1. A Status check of b1 (Protected Block), b3 (VPP invalid ) and b4 (Pro gram Er ror) can be made after each P rogra m operati on by

following the correct command se quence.

2. If an error is found, the Status Register m ust be cleared before further Prog ram /Erase Controller operations.

30/39

M50LPW002

Figure 15. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 30h

Write Address 1

Write Address 2

Write Address 3

Write Address 4

Read Status

& Data 1

& Data 2

& Data 3

& Data 4

Register

b7 = 1

b3 = 0

(3)

(3)

(3)

(3)

YES

YES

NO

NO

NO

Suspend

YES

Suspend

VPP Invalid

Error (1, 2)

Loop

Quadruple Byte Program command:
– write 30h
– write Address 1 & Data 1
– write Address 2 & Data 2
– write Address 3 & Data 3
– write Address 4 & Data 4
(memory enters read status state after
the Quadruple Byte Program command)

do:
– read Status Register if Program/Erase
Suspend command given execute
suspend program loop

while b7 = 1

If b3 = 1, VPP invalid error:
– error handler

(3)
(3)
(3)
(3)

b4 = 0

End

Note: 1. A Status chec k of b3 ( VPP invalid) and b4 (Program Error) can be made after each Program operation by following the correct com-

mand sequence.

2. If an error is found, the Status Register m ust be cleared before further Prog ram /Erase Controller operations.

3. Addre ss 1, Address 2, Address 3 an d Ad dress 4 must be consecuti ve addresse s differing only for addre ss bits A0 and A 1.

NO

YES

Program

Error (1, 2)

If b4 = 1, Program error:
– error handler

AI03982

31/39

M50LPW002

Figure 16. Program Suspend and Resume Flowchart, and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h

Read Status

Register

– write B0h
– write 70h

do:
– read Status Register

b7 = 1

YES

b2 = 1

YES

Write a read

Command

Read data from

another address

Write D0h

Program Continues

NO

NO

Program Complete

Write FFh

Read Data

while b7 = 1

If b2 = 0 Program completed

Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).

AI03408

32/39

Figure 17. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

M50LPW002

Write 80h

Write 10h

Read Status

Register

YES

YES

YES

NO

NO

NO

NO

VPP Invalid

Error (1)

Command

Sequence Error (1)

b7 = 1

b3 = 0

b4, b5 = 0

b5 = 0 Erase Error (1)

Chip Erase command:
– write 80h
– write 10h
(memory enters read Status Register after
the Chip Erase command)

do:
– read Status Register

while b7 = 1

If b3 = 1, VPP invalid error:
– error handler

If b4, b5 = 1, Command sequence error:
– error handler

If b5 = 1, Erase error:
– error handler

YES

End

Note: 1. If an error is found, the Status Register must be cleared before further Program/E rase Contr ol l er operati ons.

AI04195

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M50LPW002

Figure 18. Block Erase Flowchart and Pseudo Code

Start

Write 20h

Write Block Address

& D0h

Read Status

Register

b7 = 1

b3 = 0

b4, b5 = 0

b5 = 0 Erase Error (1)

NO

YES

NO

YES

NO

YES

NO

Suspend

Sequence Error (1)

NO

VPP Invalid

Error (1)

Command

Erase command:
– write 20h
– write Block Address & D0h
(memory enters read Status Register
after the Erase command)

do:
– read Status Register
– if Program/Erase Suspend command
given execute suspend erase loop

YES

Suspend

Loop

while b7 = 1

If b3 = 1, VPP invalid error:
– error handler

If b4, b5 = 1, Command sequence error:
– error handler

If b5 = 1, Erase error:
– error handler

YES

LPC

Interface

Only

Note: 1. If an error is found, the Status Register must be cleared before further Program/E rase Contr ol l er operati ons.

b1 = 0

End

YES

NO

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error:
– error handler

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AI05442

Figure 19. Erase Suspend and Resume Flow chart, and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h

– write B0h
– write 70h

M50LPW002

Read Status

Register

b7 = 1

YES

b6 = 1

YES

Read data from

another block

or

Program

Write D0h

Erase Continues

NO

NO

Erase Complete

Write FFh

Read Data

do:
– read Status Register

while b7 = 1

If b6 = 0, Erase completed

Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).

AI03410

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M50LPW002

PACKAGE MECHANICAL

PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline

E3

Note: Drawing is not to scale.

D

D1

1 N

D3

D2 D2

E1 E

F

0.51 (.020)

1.14 (.045)

R

A1
A2

B1

E2

e

B

E2

A

CP

PLCC-A

PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 3.18 3.56 0.125 0.140
A1 1.53 2.4 1 0.060 0.095
A2 0.38 – 0.015 –

B 0.33 0.53 0.013 0.021
B1 0.66 0.8 1 0.026 0.032

CP 0.10 0.004

D 12.32 12.57 0.485 0.495
D1 11.35 11.51 0.447 0.453
D2 4.78 5.66 0.188 0.223
D3 7.62 – – 0.300 – –

E 14.86 15.11 0.585 0.595
E1 13.89 14.05 0.547 0.553
E2 6.05 6.9 3 0.238 0.273
E3 1 0.16 – – 0.400 – –

e 1.27 – – 0.050 – –
F 0.00 0.1 3 0.000 0.005
N32 32
R 0.89 – – 0.035 – –

millimeters inches

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PART NUMBERING

Table 27. Ordering Information Scheme

Example: M50LPW002 K 1 T

Device Type

M50

Architecture

LP = Low Pin Count Interface

Operating Voltage

W = 3.0 to 3.6V

Device Function

002 = 2 Mbit (256Kb x8), Boot Block

Package

K = PLCC32

Temperature Range

1 = 0 to 70 °C
5 = –20 to 85°C

M50LPW002

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to 1. For a list of available op­tions (Speed, Package, etc...) or for further information on any aspect of this device, please contac t y our
nearest ST Sales Office.

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M50LPW002

REVISION HIST ORY

Table 28. Document Revision History

Date Version Revision Details

14-Dec-2001 -01 Document released
22-Jan-2002 -02 Details of Chip Erase command added
01-Mar-2002 -03 RFU pins must be left disconnected
12-Mar-2002 -04 Specification of PLCC32 package mechanical data revised

31-May-2002 -05 Document promoted from Product Preview to Preliminary Data

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M50LPW002

Information furnished is believed to be ac curate and reli able. Howev er, STMicroel ectronics assumes no responsibilit y for the consequence s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout express written ap proval of STMi croelect ro nics.

The ST log o i s registered trademark of STMicroelectronics
All other nam es are the pro perty of their respective owners

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