Datasheet M50FW016 Datasheet (SGS Thomson Microelectronics)

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Page 1

3V Supply Firmware Hub Flash Memory

■ SUPPLY VOLTAGE

= 3 V to 3.6 V for Program, Erase and

–V

Read Operations

–V

= 12 V for Fast Program and Fast Erase

■ TWO INTERFACES

– Firmware Hub (FWH) Interface for embedded

operation with PC Chipsets

– Address/Address Multiplexed (A/A Mux) In-

terface for programm ing equipment compat ibility

■ FIRMWARE HUB (FWH) HARDWARE

INTERFACE MODE – 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block Pro-

tection – Register Based Read and Write Protection – 5 Additional Ge neral Pu rpose I nput s f or pla t-

form design flexibility – Multi-byte Read Operation (4/16/128-byte) – Synchronized with 33 MHz PCI clock

■ BYTE PROGRAMMING TIME

– Single Byte Mode: 10µs (typical) – Quadruple Byte Mode: 2.5µs (typical)

■ 32 UNIFORM 64 Kbyte MEMORY BLOCKS

■ PROGRAM and ERASE SUSPEND

– Read other Blocks during Program/Erase

Suspend – Program other Blocks during Erase Suspend

■ FOR USE in PC BIOS APPLICATIONS

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 2Eh

M50FW016

16 Mbit (2Mb x8, Uniform Block)

PRELIMINARY DATA

TSOP40 (N)

10 x 20mm

Figure 1. Logi c D iag ram ( FWH I nte rfa ce)

ID0-ID3

FGPI0-

FGPI4

FWH4

CLK

INIT

M50FW016

FWH0FWH3

TBL

AI04462

February 2003

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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M50FW016

Figure 2. Logic Diagram (A/A Mux Interface)

A0-A10

M50FW016

DQ0-DQ7

AI04463

DESCRIPTION

The M50FW016 is a 16 Mbit (2Mb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing, an optional 12V power supply can b e used t o reduce the programming and the erasing times.

The memory is divided into blocks that can be erased independently so it is pos sible to pres erve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the m emory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Two different bus interfaces are supported by t he memory. The primary interface, the Firmware Hub

(or FWH) Interface, uses Intel’s proprietary FWH protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets; the

Figure 3. TSOP Connections

IC (VIH)

NC NC NC NC

A10

NC RC

A/A Mux

RP NC NC

A9 A8 A7 A6 A5 A4 A3

IC (VIL)

NC NC INIT NC RFU NC

FGPI4

CLK

RP NC

NC FGPI3 FGPI2 FWH0 FGPI1 ID0 FGPI0

TBL

M50FW016

20 21

31 30

FWH4

RFU RFU RFU RFU V

FWH3 FWH2 FWH1

ID1 ID2 ID3

W G RB DQ7 DQ6 DQ5 DQ4 V

DQ3 DQ2 DQ1 DQ0 A0 A1 A2

A/A Mux

AI04464

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M50FW016

M50FW016 acts as the PC BIOS on the Low P in Count bus for these PC Chipsets.

The secondary interface, the Address/Address Multiplexed (or A/A Mux) Int erface, is design ed t o be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.

The memory is offered in TSOP40 (10 x 20mm) package and it is supplied with all the bits eras ed

(set to ’1’).

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on this part. The active interface is selected before power-up or during Reset using the Interface Configur a tion Pin, IC.

The signals for each interface are discussed in the Firmware Hub (FWH) Signal Descriptions section and the Address/Address M ultiplexed (A/A Mux) Signal Descriptions section below. The supply signals are discussed in the Supply S ignal Descriptions section below.

Firmware Hub (FWH) Signal Descriptions

For the Firmware Hub (FWH) Interface see Figure 1, Logic Diagram, and Table 1, Signal Names.

Input/Output Communications (FWH0-FWH3). All Input and Output Communication with the memory take place on these pi ns. Addresses and Data for Bus Read and Bus W rite operations are en coded on these pins.

Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the start of a bus op eration. When Input Communication Frame is Low, V

, on the rising edge of the

Clock a new bus operation is initiated. If Input Communication Frame is L ow, V

, during a bus

operation then the operation is aborted. When Input Communication Frame is High, V

, the cur-

rent bus operation is proceeding or the bus is idle. Identification Inputs (ID0-ID3). The

Identification Inputs select the address that the memory responds to. Up to 16 memories can be addressed on a bus. Fo r an address bit to be ‘0’ the pin can be left floating or driven Low, V

; an

internal pull-down resistor is included with a value

. For an address bit to be ‘1’ the pin must be

of R

driven High, V I

through each pin when pulled to VIH; see Table

LI2

; there will be a leakage current of

20. By convention the boot memory must have

address ‘0000’ and all additional memories take sequential addresses starting from ‘0001’.

By convention the boot memory m ust have ID0ID3 pins left floating or driven Low, V

and a ‘1’

value on A21, A23-A25 and all additional memories take sequential ID0-ID3 configuration.

Table 1. Signal Names (FWH Interface)

FWH0-FWH3 Input/Output Communications FWH4 Input Communication Frame ID0-ID3 Identification Inputs FGPI0-FGPI4 General Purpose Inputs IC Interface Configuration RP INIT CLK Clock TBL WP

RFU

NC Not Connected Intern ally

Interface Reset CPU Reset

Top Block Lock Write Protect Reserved for Future Use. Leave

disconnected. Supply Voltage Optional Supply Voltage for Fast

Program and Fast Erase Operations Ground

General Purpose Inputs (FGPI0-FGPI4) . The General Purpose Inputs can be used as digital inputs for the CPU to read. Th e General Purpose Input Register holds the values on t hese pins. The pins must have stable data f rom before t he s tart of t he cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low,

or High, VIH.

IL,

Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub (FWH) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be change d. The state of the Interface Configuration, IC, should not be changed during operation.

To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to float or driven Low, V

; to select the Address/Address

Multiplexed (A/A Mux) Interface t he pin should be driven High, V included with a value of R current of I

. An internal pull-down resistor is

through each pin when pulled to VIH;

LI2

; there will be a leakage

see Table 20.

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Table 2. Signal Names (A/A Mux Interface)

IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G W RC RB RP V

NC Not Connected Intern ally

Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage for Fast

Program and Fast Erase Operations

Ground

Interface Reset (RP). The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP

) is set Low, VIL, the memor y i s i n R ese t mode: the outputs are put to high impedance and the current consumption is minimized. When RP set High, V

, the memory is in no rmal operat ion.

After exiting Reset mode, the memory enters Read mode.

CPU Reset (INIT

). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset. It behaves identically to Interface Reset, RP

, and the internal Reset lin e is the logical OR (elec tric al AND) of RP

and INIT.

Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification.

Top Block Lock (TB L

). The Top Block Lock

input is used to prevent the Top Block (Block 31) from being chan ged. When Top Block Loc k, TBL is set Low, V

, Program and Block Erase

operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL

, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL

, does not affect the protection of the Main Blocks (Blocks 0 to 30).

Top Block Lock, TBL

, must be set prior to a Pro-

gram or Block Erase operation is initiated and

must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL

Write Protect (WP

during Program or Erase Suspend.

). The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 30) from being changed. W hen Write P rotect, WP set Low, V

, Program and Block Erase operations

in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect,

, is s et High, VIH, the protection of the B lock

WP determined by the Lock Register. The state of Write Protect, WP

, does not affect the protection of

the T op Bl ock (Block 31). Write Protect, WP

, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the o peration completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing

during Program or Erase Suspend.

WP Reserved for Future Use (RFU). These pins do

not have assigned func t ions i n this revision of the part. They must be left disconnected.

Address/Address Multiplexed (A/A Mux) Signal Descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2, Logi c Diagram, and Table 2, Signal Names.

Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A20). They are latched during any bus operation by the Row/ Column Address Select input, RC

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data s tored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the C ommand Interface of the internal state machine. The Data I nputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation.

Output Enable (G

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a c e .

Row/Column Address Select (RC

). The Row/

Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A20). The Row Address bits are latched on the falling edge of RC

whereas the Column

Address bits are latched on the rising edge.

, is

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M50FW016

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the ra ting "Oper at i ng Temperat ure Range", stresse s above th ose listed i n t he Table "Absolute M aximum Rat i ngs" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Minimum Voltage may undershoot to –2V, for less than 20 ns, during transitions. Maximum Voltage may overshoot to V

less than 20 ns, during transitions.

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 5) –20 to 85 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage Supply Voltage –0.6 to 4 V Program Voltage –0.6 to 13 V

Ready/Busy Output (RB). The Ready/Busy pin

gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, V memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High,

, the memory is ready for any Rea d, Program

or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfaces.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V Supply Voltage is less than the L ockout Voltage,

. This prevents Bus Write operations from

LKO

accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during

(1)

, the

–0.6 to V

+ 0.6

+2V, for

widths must be sufficient to carry the currents required during program and erase operations.

Optional Supply Voltage. The VPP Optional

Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory and to protect the memory. When V < V

Program and Erase operations cannot be

PPLK

performed and an error is reported in the Sta tus Register if an attempt to change the memory contents is made. When V Erase operations take place as normal. When V = V

Fast Program operations (using the

PPH

= VCC Program and

Quadruple Byte Program command, 30h, from Table 13) and Fast Erase operations are used. Any other voltage input to V

will result in

undefined behavior and should not be used. V

should not be set to V

for more than 80

PPH

hours during the life of the memory.

Ground. VSS is the reference for al l the vol t-

age measurements.

this time then the operation aborts and the memory contents being altered will be invalid. After V

becomes valid the Comma nd Interface

is reset to Read mode. A 0.1µF capacitor should be connected between

the V

Supply Voltage pins and the VSS Ground

pin to decouple the current surges from the power supply. Both V

Supply Voltage pins must be

connected to the power supply. The PCB track

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M50FW016

Table 4. Block Addresses

Size

(Kbytes)

64 1F0000h-1FFFFFh 31 Top Block 64 1E0000h-1EFFFFh 30 Main Block 64 1D0000h-1DFFFFh 29 Main Block 64 1C0000h-1CFFFFh 28 Main Block 64 1B0000h-1BFFFFh 27 Main Block 64 1A0000h-1AFFFFh 26 Main Block 64 190000h-19FFFFh 25 Main Block 64 180000h-18FFFFh 24 Main Block 64 170000h-17FFFFh 23 Main Block 64 160000h-16FFFFh 22 Main Block 64 150000h-15FFFFh 21 Main Block 64 140000h-14FFFFh 20 Main Block 64 130000h-13FFFFh 19 Main Block 64 120000h-12FFFFh 18 Main Block 64 110000h-11FFFFh 17 Main Block 64 100000h-10FFFFh 16 Main Block 64 0F0000h-0FFFFFh 15 Main Block 64 0E0000h-0EFFFFh 14 Main Block 64 0D0000h-0DFFFFh 13 Main Block 64 0C0000h-0CFFFFh 12 Main Block 64 0B0000h-0BFFFFh 11 Main Block 64 0A0000h-0AFFFFh 10 Main Block 64 090000h-09FFFFh 9 Main Block 64 080000h-08FFFFh 8 Main Block 64 070000h-07FFFFh 7 Main Block 64 060000h-06FFFFh 6 Main Block 64 050000h-05FFFFh 5 Main Block 64 040000h-04FFFFh 4 Main Block 64 030000h-03FFFFh 3 Main Block 64 020000h-02FFFFh 2 Main Block 64 010000h-01FFFFh 1 Main Block 64 000000h-00FFFFh 0 Main Block

Address Range

Block

Number

Block Type

BUS OPERATIONS

The two interfaces have similar bus operations but the signals and tim ings are compl etely different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality of the part is available through this in terface. Only a subset of functions are available through the Address/ Address Multiplexed (A/A Mux) Interface.

Follow the section Firmware Hub (FWH) Bus Operations below and the section Address/ Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface.

Firmware Hub (FWH) Bus Operations

The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one cont rol line (FWH4) and a clock (CLK). In addition protect ion against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals (RP and INIT ) are available to put the memory into a known state.

The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz.

The following operations can be performed using the appropriate bus cycles: B us Read, Bus Write, Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Firmware Hub Reg isters. A valid B us Read operation starts when Input Communication Frame, FWH4, is Low, V

, as Clock rises and the

correct Start cycle is on FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select, Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4Data7.

Refer to Table 5, FWH Bus Read Field Definitions, and Figure 4, FWH Bus Read W avef orms (Sin gle Byte Read), for a description of the F ield definitions for each clock cycle of the transfer. See Table 22, FWH Interface AC Signal Timing Characteristics and Figure 10, FWH Interface AC Signal Timing Waveforms, for details on the timings of the signals.

FWH Bus Write. Bus Write operations write to the Command Interface or Firmware Hub Registers. A valid Bus Write operation starts when Input Communication Frame, FWH4, is Low, V

as Clock rises and the correct Start cycle is on FWH0-FWH3. On the following Clock cycles the Host will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7

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M50FW016

on FWH0-FWH3. The memory outputs Sync data until the wait-states have elapsed.

Refer to Table 6, FWH Bus Write Field Definitions, and Figure 5, FWH Bus Write Waveforms, for a description of the Field definitions for each clock cycle of the transfer. See Table 22, FWH Interface AC Signal Timing Characteristics and Figure 10, FWH Interface AC Signal Timing Waveforms, for details on the timings of the signals.

Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4 is driven Low, V

during the bus operation; the memo ry will tri-state the Input/Output Communication pins, FWH0FWH3.

Note that, during a Bus Write operation, the Command Interface starts executing the command as soon a s the data is f ully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately.

Standby. When F WH4 is High, V

, the me mory

is put into Standby mode where FWH0-FWH3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, I

CC1

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP Rese t, IN IT Low, V

, is Low, VIL. RP or IN IT must be held

, for t

. The memory resets to Read

PLPH

, or CPU

mode upon return from Res et mo de and the Lock Registers return to their default states regardless of their state before Reset, see Table 15. If RP INIT

goes Low, VIL, during a Program or Erase

operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

PLRH

to abort a

Program or Erase operation. Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL Write Protect, WP

, regardless of the state of the

, and

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus Operations

The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and three control signals (RC signal, RP

, can be used to reset the memory.

, G, W). An additional

The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Firmware Hub (FWH) Interface are

available; these include all the Commands but exclude the Security features and other registers.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface.

Bus Read. Bus Read operations are used to output the contents of the Memory Array, the

Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC Write Enable (W be High, V

) and Interface Reset (RP) must

, and Output Enable, G, Low, VIL, in

order to perform a Bus Read operation. The Data Inputs/Outputs will output the value, see Figure 12, A/A Mux Interface Read AC Waveforms , and Table 24, A/A Mux Interface Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC

. The data should be set up on the Data Inputs/Outputs; Output Enable, G Interface Reset, RP Enable, W

, must be Low, VIL. The Data Inputs/

, must be High, VIH and Write

Outputs are latched on the rising edge of Write Enable, W

. See Figure 13, A/A Mux Interface Write AC Waveforms, and Table 25, A/A Mux Interface Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . The data outputs are high-impedance when the Output Enable, G

, is at VIH.

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP held Low, V

for t

is Low, VIL. RP must be

. If RP is goes Low, VIL,

PLPH

during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

to abort a Program or Erase operation.

PLRH

. Then

, and

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M50FW016

Tabl e 5. FWH Bus Read Field Defin itions

Clock Cycle

Number

Clock Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

1 1 START 1101b I

2 1 IDSEL XXXX I

3-9 7 ADDR XXXX I

10 1 MSIZE 0XXXb I

11 1 TAR 1111b I

12 1 TAR

1111b

(float)

13-14 2 WSYNC 0101b O

15 1 RSYNC 0000b O

16-17 2 DATA XXXX O

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Read cycle.

Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

A 28-bit address phase is transferred starting with the most significant nibble first. For the multi-byte read operation, the least significant bits (MSIZE of them) are treated as Don’t Care, and the read operation is started with each of these bits reset to 0.

This one clock cycle is driven by the host to determine how many bytes will be transferred. M50FW016 will support: single byte transfer (0000b), 4-byte transfer (0010b), 16-byte transfer (0100b) and 128-byte transfer (0111b).

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0101b

(short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included.

The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating that data will be available during the next clock cycle.

Data transfer is two CLK cycles, starting with the least significant nibble.

enabled, repeat

If multi-byte read operation is

cycle 16-17 n times, where n = 2

MSIZE

–1

Note 1 1 TAR 1111b O

MSIZE MSIZE

1111b

(float)

–1)*2+18 –1)*2+19

Note 2 1 TAR

Note: 1. Clock Cycle Number = (2

2. Clock Cycle Number = (2

N/A

The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3.

Figure 4. FWH Bus Read Waveforms (Single Byte Read)

CLK

FWH4

START IDSEL ADDR MSIZE TAR SYNC DATA TAR

11712322

8/37

FWH0-FWH3

Number of clock cycles

AI03437

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Table 6. FWH Bus Write Field Definitions (Single Byte)

Clock Cycle

Number

Clock Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

M50FW016

Description

1 1 START 1110b I

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle.

Indicates which FWH Flash Memory is selected. The value

2 1 IDSEL XXXX I

on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

3-9 7 ADDR XXXX I

A 28-bit address phase is transferred starting with the most significant nibble first.

10 1 MSIZE 0000b I Always 0000b (single byte transfer).

11-12 2 DATA XXXX I

13 1 TAR 1111b I

14 1 TAR

1111b

(float)

15 1 S YNC 0000b O

16 1 TAR 1111b O

17 1 TAR

1111b

(float)

N/A

Data transfer is two cycles, starting with the least significant nibble.

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command. The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle. The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

Figure 5. FWH Bus Write Waveforms (Single Byte)

CLK

FWH4

FWH0-FWH3

Number of clock cycles

START IDSEL ADDR MSIZE DATA TAR SYNC TAR

11712212

AI03441

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Table 7. FWH Bus Write Field Definitions (Quadruple Byte Program)

Clock Cycle

Number

Clock Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

1 1 START 1110b I

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle.

Indicates which FWH Flash Memory is selected. The value

2 1 IDSEL XXXX I

on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

A 28-bit address phase is transferred starting with the most

3-9 7 ADDR XXXX I

significant nibble first. The A1-A0 lines are treated as Don’t Care.

10 1 MSIZE 0010b I Always 0010b (quadruple byte transfer).

Data transfer is two cycles, starting with the least significant nibble. (The first pair of nibbles is that at the address with A1-

11-18 8 DATA XXXX I

A0 set to 00, the second pair with A1-A0 set to 01, the third pair with A1-A0 set to 10, and the fourth pair with A1-A0 set to 11.)

19 1 TAR 1111b I

20 1 TAR

1111b

(float)

21 1 S YNC 0000b O

22 1 TAR 1111b O

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command. The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle.

23 1 TAR

1111b

(float)

N/A

The FWH Flash Memory floats its outputs and the host takes control of FWH0-FWH3.

Figure 6. FWH Bus Write Waveforms (Quadruple Byte Program)

CLK

FWH4

FWH0-FWH3

Number of clock cycles

START IDSEL ADDR MSIZE DATA TAR SYNC TAR

11718212

AI05784

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Table 8. A/A Mux Bus Operations

Operation G W RP

Bus Read Bus Write Output Disable Reset

or V

VIL or V

Table 9. Manufacturer and Device Codes

Operation G

Manufacturer Code Device Code

W RP A20-A1 A0 DQ7-DQ0

M50FW016

Don’t Care Data Output

VCC or V

Don’t Care Hi-Z Don’t Care Hi-Z

V V

PPH

DQ7-DQ0

Data Input

20h 2Eh

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations.

After power-up or a Reset operation the memory enters Read mode.

The commands are summarized in Table 11, Commands. Refer to Tab le 1 1 in conjun ction with the text descriptions below.

Read Memory A rray Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array.

While the Program/Erase Controller is executing a Program or Erase operation the m emory will not accept the Read Memory Array command until the operation completes.

Read Statu s Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits.

Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read

operations read the Manufacturer Code or the Device Code until another command is issued.

After the Read Electronic Signature Command is issued the Manufacturer Code and Devi ce Code can be read using Bus Read op erations us ing the addresses in Table 10.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data in the internal state m achine and starts the Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

If the address falls in a pro tected block then the Program operation will abort, the data in the memory array will no t be changed and the S tatus Register will output the error.

During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 12.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’.

See Figure 14, Program Flowchart and Pseudo Code, for a suggested flowchart on using the Program command.

Quadruple Byte Program Command (A/A Mux Mode). The Q uadruple Byte Program Command

can be used to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 a nd A1. Programming

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should not be attempted when VPP is not at V

PPH

Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspe nd command. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table

12. Note that the Quadruple Byte Program comm and

cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’.

See Figure 15, for a suggested flowchart on using the Quadruple Byte Program command.

Quadruple Byte Program Command (FWH Mode). The Q uadruple Byte Program Command

can be used to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 a nd A1. Programming should not be attempted when V

is not at V

PPH

Two Bus Write operations are required to issue the command. The second Bus Write cycle latches the start address and four data byt es in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

12. Note that the Quadruple Byte Program comm and

See Figure 16, for a suggested flowchart on using the Quadruple Byte Program command.

Chip Erase Command. The Chip Erase Command can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be at-

Table 10. Read Electronic Signature

Code Address Data

Manufacturer Code 00000h 20h Device Code 00001h 2Eh

tempted when V can also be executed if V

is not at V

PPH

is b elow V

. The operation

sult could be incertain. Two Bus Write operations are required to issue the com mand and start the Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Chip Erase operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Chip Erase times are given in T able 12. The Chip Erase command sets all of the bits in the memory to ‘1’. See Figure 18, Chip Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Chip Erase command.

Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal stat e machine and starts th e Program/Erase Controller. Once the command is issued subsequent Bus Read ope rations read the Status Register. See the section on the Status Register for details on the definitions of the Status

operation will abort, the data in the block will not be changed and the Status Register will output the error.

During the Block Erase operation the me mory wi ll only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Block Erase times are given in Table 12.

The Block Erase command sets all of the bits in the block to ‘1’. All previous data in the block is lost.

See Figure 19, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Erase command.

Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subs equent Bus Read operations continue to output the same data.

The bits in the Status Register are stic ky and do not automatically return to ‘0’ when a new Program

PPH

, but re-

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M50FW016

Table 11. Commands

Bus Write Operations

Command

Cycles

Read Memory Array 1 X FFh Read Status Register 1 X 70h

Read Electronic Signature

1X 90h 1X 98h 2X 40hPA PD

Program

2X 10hPA PD

Quadruple Byte Program (A/A Mux Mode)

Quadruple Byte Program (FWH Mode)

5X 30h

2 X 30h

Chip Erase 2 X 80h X 10h Block Erase 2 X 20h BA D0h Clear Status Register 1 X 50h Program/Erase Suspend 1 X B0h Program/Erase Resume 1 X D0h

1X 00h 1X 01h

Invalid/Reserved

1X 60h 1X2Fh 1XC0h

Note: X Don’t Care, PA Program Address, PD Program Data, A

Read Memory Array. After a Read M em ory Array command, read the memory as normal unti l another comm and is issued. Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature. Af t er a Read Electronic Signature command, read Manufacturer Code, Device Code until another co m -

mand is issued. Block Erase, Program. After th ese com man ds re ad t he S tat us Re gist er un t il th e comm an d comp l etes and an othe r c omma nd is is -

sued. Quadruple Byte Program (A/A Mux Mode). Addresses A

bit A0 and A1. After this comm and, the us er shou ld rep eat edl y read t he Stat us Regi st er until the co mmand has compl eted, at whic h point another command can be issued.

Quadruple Byte Program (FWH Mode) . A grammed at the ad dress that has A1-A 0 at 00, the second at the ad dress that has A1-A0 at 01, t he third at the ad dress that has A1A0 at 10, and the fourth at the address that has A1-A0 at 11. After this command, the user should repeatedly read the Status Register until the com m and has completed, at which point anot her command can be issu ed.

Chip Er ase. This command is only valid in A /A Mux mode. After this command read the St atus Registe r until t he c ommand complete s and another command is issued.

Clear Status Register. After the Clear St atus Register command bits 1, 3, 4 and 5 in the Stat us Register a re reset to ‘0’. Program/Erase Susp end. After the Program /Erase Sus pend command has been accept ed, issue Read Mem ory Array, Read Status

Register, Program (during Era se suspend ) and Program/ Erase resum e commands. Program/Erase Resu me. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the

Status Register unti l the Program/ E rase Contr ol l er completes and the mem ory returns to Read Mode.

Invalid/Reserved . Do not use In valid or Res erved commands.

1st 2nd 3rd 4th 5th

Addr Data Addr Data Addr Data Addr Data Addr Data

1,2,3,4

, A2, A3 and A4 must be consecutive addresses di ffering only for addre ss

is the sta rt ad dr ess, A 1 a nd A0 are t reat ed a s Don ’t Care. T he f irs t dat a byte is pro -

qbp

Consecut i ve Addresses, BA Any address in the Block.

qbp

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M50FW016

Table 12. Program and Erase Times

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Parameter Interface Test Condition Min

Byte Program 10 200

Quadruple Byte Program

Chip Erase A/A Mux

Block Program

Block Erase

Program/Erase Suspend to Program pause Program/Erase Suspend to Block Erase pause

Note: 1. TA = 25°C, VCC = 3.3V

2. This time is obtai ned executi ng the Quadruple Byte Prog ram Comma nd.

3. Sampled only, not 100% tested.

4. Time to program four bytes.

(3)

A/A Mux

(3)

= 12V ± 5%

= V

(1)

Typ

18 sec

0.1

0.4 5 sec

0.75 8 sec

Max Unit

(4)

(2)

110sec

200

5sec

or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program or Erase command.

Program/Erase Suspend Command. The Program/Erase Suspend command can be used to pause a Program or B lock Erase operation. O ne Bus Write cycle is required to issue the Program/ Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit to find out when the Program/ Erase Controller has paused; no other commands will be accept ed until the Pro gram/ Erase Cont roller has paused. After the Program/Erase Cont roller has paused, the memory will continue to output the Status Register until another command is issued.

During the polling period between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/ Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to d etermine if the operatio n has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 12.

During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume

commands will be accepted by the Command Interface. Additionally, if the suspe nded operation was Block Erase then the Program com mand will also be accepte d; only the blocks no t being erased may be read or programmed correctly.

See Figures 17, Program Suspend & Resume Flowchart and Pseudo Code, and 20, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/ Erase Suspend command.

Program / Erase Resum e Command. The Program/Erase Resume com m and c an be used to restart the Program/Erase Controller after a Program/Erase Suspend has p aused it. One Bus Write cycle is required to issue the Program/Erase Resume command. O nc e the command is iss ued subsequent Bus Read operations read the Status Register.

STATUS REGISTER

The Status Register provides information on the current or previous Program or Erase operation. Different bits in the Status Register convey different information and errors on the operation.

To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register c an be read from any address.

The Status Register bits are summarized in Table 13, Status Register Bits. Refer to Table 13 in conjunction with the text descriptions below.

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Table 13. Status Register Bits

Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

(1)

Program active ‘0’ Program suspended ‘1 Program completed successfully ‘1’ Program failure due to V Program failure due to Block Protection (FWH Interface only) ‘1’ Program failure due to cell failure ‘1’

Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Block Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Error

‘1’

X X X X X X

‘0’ ‘0’ ‘0’ ‘0’ ‘0’

(1)

‘0’ ‘0’ ‘0’ ‘1’ ‘0’

(1)

‘0’ ‘0’ ‘0’ ‘0’ ‘0’

(1)

‘0’ ‘0’ ‘1’ ‘0’ ‘0’

(1)

‘0’ ‘0’ ‘0’ ‘0’ ‘1’

(1)

‘0’ ‘1’ ‘0’ ‘0’ ‘0’

Erase failure due to V Block Erase failure due to Block Protection (FWH Interface

only) Erase failure due to failed cell(s) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’

Note: 1. For Program operations duri ng Erase Suspend Bit 6 is ‘1’ , otherwise Bit 6 is ‘0’ .

Program/Erase Controller Status (Bit 7). The Progra m/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is

‘0’, the Program/Erase Controller is active; when the bit is ‘1’, the Program/Erase Controller is inactive.

The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Su spend c om m and is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is ‘1’.

During Program and Erase operation the Program/Erase Controller Status bit can be pol led to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is ‘1’.

After the Program/Erase Cont roller completes its operation the Erase Status, Prog ram Status, V Status and Block Pr otec tion S tatus b its should be tested for errors.

Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that a Block E rase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.

Error

‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’

‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’

When the Erase Suspend Sta tus bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/Er ase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program /Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’.

Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has applied the maximum number of erase pulses t o the block(s) and still failed to verify that the block(s) has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive).

When the E rase Status bit is ‘0’ the me mory has successfully verified that the block(s) has erased correctly; when the Erase S t atus bit is ‘1 ’ the P rogram/Erase Controller has applied the max imum number of pulses to the bloc k(s) and still failed to verify that the block(s) has erased correctly.

Once the Erase Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase comma nd is issued, otherwise the new command will appear to fail. (When Bit 4 and Bit 5 are set to ‘1’, a wro ng command sequence has been at tempted).

Program Status (Bit 4). The Program Status bit can be used to identify if the memory has applied the maximum number of program pulses to the byte and still failed to verify that the byte has pro-

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M50FW016

grammed correctly. The Program Status bit should be read once the Program/Erase Controller Status

bit is ‘1’ (Program/Erase Controller inactive). When the Program Status bit is ‘0’ the memory has

successfully verified that the byte has programmed correctly; when the Program Status bit is ‘1’ the Program/Erase Controller has applied the maximum number of pulses to the byte an d still failed to verify that the byte has program med c orrectly.

Once the Program Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong command sequence has been attempted).

Status (Bit 3). The VPP Status bit can be

used to identify an invalid v oltage on the V during Program and Erase operations. The V

pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if V

becomes invalid during a Program or

Erase operation. When the V

pin was sampled at a valid vol tag e; w hen the

Status bit is ‘1’ the VPP pin has a voltage that

is below the V

Status bit is ‘ 0’ the vol tage on the

Lockout Voltage, V

PPLK

, the memory is protected; Program and Erase operation cannot be performed. (The V

status bit is ‘1’

if a Quadruple Byte Program comma nd is issued and the V

signal has a voltage less than V

PPH

applied to it.) Once the V

Status bit set to ‘1’ it can only be re-

set to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Re sume command is issued the Program Suspend Status bit returns to ‘0’.

Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if the Program or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is to ‘0’ no Program or BlockErase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is ‘1’ a Program or Block E rase operation has been attempted on a protected block.

Once it is set to ‘ 1’ the Block Protection Stat us bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset . If it is set to ‘1’ it should be reset before a new Program or Block Erase command is issued, otherwise the new command will appear to fail.

Using the A/A Mux Interface the Block Protection Status bit is always ‘0’.

Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked.

FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS

When the Firmware Hub Interface is selected several additional registers can be accessed. These registers control the protection status of the Blocks, read the General Purpose Input pins and identify the memory using the Electronic Signature codes. See Table 14 for t he memory map of the Configuration Registers in the FWH Protocol.

Lock Registers

The Lock Registers control the protection status of the Blocks. Each Block has its own Lock Register. Three bits within each Lock Register control the protection of each block, the W rite Lock Bit, the Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written, though care should be taken when writing as, once the Lock Down Bi t is set, ‘1’, further modifications to the Lock Register cannot be made until cleared, to ‘0’, by a reset or power-up.

See Table 15 for details on the bit definitions of the Lock Registers.

Write Lock. The Write Lock Bit determines whether the contents of the Block can be modified (using the Program or Block Erase Command). When the Write Lock Bit is set, ‘1’, the block is write protected; any operations that attempt to change the data in the block will fail and the Status Register will report the error. When the Write Lock Bit is reset, ‘0’, the block is not write protected through the Lock Register and may be modified unless write protected through some other means.

When V

is less than V

all blocks are pro-

PPLK

tected and cannot be modified, regardl ess of the state of the Write Lock Bit. If Top Block Lock, TBL

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Table 14. Firmware Hub Register Configuration Map

Mnemonic Register Name

T_BLOCK_LK Top Block Lock Register (Block 31) FBF0002h 01h R/W T_MINUS01_LK Top Block [-1] Lock Register (Block 30) FBE0002h 01h R/W T_MINUS02_LK Top Block [-2] Lock Register (Block 29) FBD0002h 01h R/W T_MINUS03_LK Top Block [-3] Lock Register (Block 28) FBC0002h 01h R/W T_MINUS04_LK Top Block [-4] Lock Register (Block 27) FBB0002h 01h R/W T_MINUS05_LK Top Block [-5] Lock Register (Block 26) FBA0002h 01h R/W T_MINUS06_LK Top Block [-6] Lock Register (Block 25) FB90002h 01h R/W T_MINUS07_LK Top Block [-7] Lock Register (Block 24) FB80002h 01h R/W T_MINUS08_LK Top Block [-8] Lock Register (Block 23) FB70002h 01h R/W T_MINUS09_LK Top Block [-9] Lock Register (Block 22) FB60002h 01h R/W T_MINUS10_LK Top Block [-10] Lock Register (Block 21) FB50002h 01h R/W T_MINUS11_LK Top Block [-11] Lock Register (Block 20) FB40002h 01h R/W T_MINUS12_LK Top Block [-12] Lock Register (Block 19) FB30002h 01h R/W T_MINUS13_LK Top Block [-13] Lock Register (Block 18) FB20002h 01h R/W T_MINUS14_LK Top Block [-14] Lock Register (Block 17) FB10002h 01h R/W T_MINUS15_LK Top Block [-15] Lock Register (Block 16) FB00002h 01h R/W T_MINUS16_LK Top Block [-16] Lock Register (Block 15) FAF0002h 01h R/W T_MINUS17_LK Top Block [-17] Lock Register (Block 14) FAE0002h 01h R/W T_MINUS18_LK Top Block [-18] Lock Register (Block 13) FAD0002h 01h R/W T_MINUS19_LK Top Block [-19] Lock Register (Block 12) FAC0002h 01h R/W T_MINUS20_LK Top Block [-20] Lock Register (Block 11) FAB0002h 01h R/W T_MINUS21_LK Top Block [-21] Lock Register (Block 10) FAA0002h 01h R/W T_MINUS22_LK Top Block [-22] Lock Register (Block 9) FA90002h 01h R/W T_MINUS23_LK Top Block [-23] Lock Register (Block 8) FA80002h 01h R/W T_MINUS24_LK Top Block [-24] Lock Register (Block 7) FA70002h 01h R/W T_MINUS25_LK Top Block [-25] Lock Register (Block 6) FA60002h 01h R/W T_MINUS26_LK Top Block [-26] Lock Register (Block 5) FA50002h 01h R/W T_MINUS27_LK Top Block [-27] Lock Register (Block 4) FA40002h 01h R/W T_MINUS28_LK Top Block [-28] Lock Register (Block 3) FA30002h 01h R/W T_MINUS29_LK Top Block [-29] Lock Register (Block 2) FA20002h 01h R/W T_MINUS30_LK Top Block [-30] Lock Register (Block 1) FA10002h 01h R/W T_MINUS31_LK Top Block [-31] Lock Register (Block 0) FA00002h 01h R/W

FGPI_REG Firmware Hub (FWH) General Purpose Input Register FBC0100h N/A R

MANUF_REG Manufacturer Code Register FBC0000h 20h R

DEV_REG Device Code Register FBC0001h 2Eh R

MBR_REG_LB Multi-Byte Read Configuration Register (Low Byte) FBC0005h 4Ah R MBR_REG_HB Multi-Byte Read Configuration Register (High Byte) FBC0006h 00h R MBW_REG_LB Multi-Byte Write Configuration Register (Low Byte) FBC0007h 02h R

MBW_REG_HB Multi-Byte Write Configuration Register (High Byte) FBC0008h 00h R

Memory

Address

Default

Value

Access

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Tabl e 15. Lock Re gister Bit Definitions

Bit Bit Name Value Function

7-3 Reserved

‘1’ Bus Read operations in this Block always return 00h.

2 Read-Lock

1 Lock-Down

0 Write-Lock

Note: 1. Applies to T op Blo ck L ock R eg ister (T_ BLOC K_LK ) an d To p Bl ock [-1] Loc k Reg ist er (T_ MI NUS0 1_ LK) to Top Bl ock [ -31] Lock

Bus read operations in this Block return the Memory Array contents. (Default

‘0’

value). Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following a Reset (using RP

Read-Lock and Write-Lock can be changed by writing new values to them. (Default

‘0’

value). Program and Block Erase operations in this Block will set an error in the Status

‘1’

Register. The memory contents will not be changed. (Default value). Program and Block Erase operations in this Block are executed and will modify the

‘0’

Block contents.

Table 16. General Purpose Input Regi s te r D ef i ni tion

Bit Bit Name Value Function

7-5 Reserved

(1)

or INIT) or after power-up.

(1)

Input Pin FGPI4 is at V

4 FGPI4

3 FGPI3

2 FGPI2

1 FGPI1

0 FGPI0

Note: 1. Appli es to the General Purpose Input Register (FGPI_REG).

‘1’

Input Pin FGPI4 is at V

‘0’

Input Pin FGPI3 is at V

‘1’

Input Pin FGPI3 is at V

‘0’

Input Pin FGPI2 is at V

‘1’

Input Pin FGPI2 is at V

‘0’

Input Pin FGPI1 is at V

‘1’

Input Pin FGPI1 is at V

‘0’

Input Pin FGPI0 is at V

‘1’

Input Pin FGPI0 is at V

‘0’

is Low, VIL, then the Top Block (Block 31) is write protected and cannot be modified. Similarly, if Write Protect, WP

, is Low, VIL, then the Main Blocks (Blocks 0 to 30) are write protected and cannot be modified.

After power-up or reset the Write Lock Bit is al-

ways set to ‘1’ (write protected). Read Lock. The Read Lock bit determines

whether the contents of the Block can be read (from Read mode). When the Read Lock Bit is set, ‘1’, the block is read prot ected; an y operat ion that attempts to read the contents of the block will read

00h instead. When the Read Lock Bit is reset, ‘0’, read operations in the Block return the data programmed into the block as expected.

After power-up or reset the Read Lock B it is always reset to ‘0’ (not read protected).

Lock Down. The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the Write Lock, Read Lock and Lock Down Bits cannot be performed. A reset or power-up is required before changes to these bits can be made. When the

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Lock Down Bit is reset, ‘0’, the Write L ock, Read Lock and Lock Down Bits can be changed.

Firmware Hu b (FWH) Genera l P urp ose I npu t Register

The Firmware Hub (FWH) General Purpose Input Register holds the state of the Firmware Hub Interface General Purpose Input pins, FGPI0-FGPI4. When this register is read, the state of thes e pins is returned. This register is read-only and writing to it has no effect.

Device Code Register

Reading the Device Code Register returns the device code for the memory, 2Eh. This register is read-only and writing to it has no effect.

Multi-Byte Read/Write Configuration Registers

The Multi-Byte Read/Write Configuration Registers contain information as which m ulti-byte read and write access sizes will be accepted. The M50FW016 supports 4/16/128-byte reading and

4-byte writing. The signals on the Firmware Hub Interface General Purpose Input pins should remain constant throughout the whole Bus Read cycle in order to guarantee that the correct data is read.

Manufacturer Code Register

Reading the Manufacturer Code Register returns the manufacturer code for the memory. The manufacturer code for STMicroelectronics is 20h. This register is read-only and writing to it has no effect.

Table 17. FWH Interface AC Measurement Conditions

Parameter Value U nit

Supply Voltage

Load Capacitance (C Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages

)

Figure 7. FWH Interface AC Testing Input Output Waveforms

0.6 V

0.2 V

Input and Output AC Testing Waveform

IO < I

Output AC Tri-state Testing Waveform

IO > I

IO < I

0.4 V

3.0 to 3.6 V 10 pF

1.4 ns

≤

0.2 V

and 0.6 V

0.4 V

V V

AI03404

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Page 20

M50FW016

Table 18. A/A Mux Interface AC Measurement Conditions

Parameter Value U nit

Supply Voltage

3.0 to 3.6 V

Load Capacitance (C Input Rise and Fall Times

)

30 pF

10 ns

≤

Input Pulse Voltages 0 to 3 V Input and Output Timing Ref. Voltages 1.5 V

Figure 8. A/A Mux I nte rfac e AC Testing In put Output Wav ef orm

1.5V

AI01417

Table 19. Impedance (T

= 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit

(1)

CLK

(2)

Note: 1. Sampled only, not 100% tested.

2. See PCI Specific ation.

Input Capacitance Clock Capacitance

Recommended Pin Inductance

V V

= 0V = 0V

13 pF

312pF

20 nH

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Page 21

M50FW016

Table 20. DC Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Interface Test Condition Min Max Unit

PPLK

(INIT)

(2)

LI2

PP1

PPH

LKO

CC1

Input High Voltage

Input Low Voltage

Input High Voltage FWH 1.35

INIT

Input Low Voltage FWH –0.5

INIT Input Leakage Current

IC, IDx Input Leakage Current

IC, IDx Input Pull Low Resistor

Output High Voltage

Output Low Voltage

Output Leakage Curren t

VPP Voltage VPP Voltage (Fast

Program/Fast Erase)

(1)

VPP Lockout Voltage

(1)

VCC Lockout Volt age

Supply Current (Standby) FWH

FWH

A/A Mux

0.5 V

0.7 V

FWH –0.5

CCVCC

+ 0.5 + 0.3

0.3 V

A/A Mux -0.5 0.8 V

+ 0.5

0.2 V

0V ≤ V

IC, ID0, ID1, ID2, ID3 = V

≤ V

±10

200 µA

20 100 k

FWH I

A/A Mux I

FWH

A/A Mux

0V ≤ V

= –500µA

= –100µA

= 1.5mA 0.1 V

= 1.8mA

≤ V

OUT

0.9 V

– 0.4

0.45 V ±10

3 3.6 V

11.4 12.6 V

1.5 V

1.8 2.3 V

FWH4 = 0.9 V

All other inputs 0.9 VCC to 0.1 V

, VPP = V

100

VCC = 3.6V, f(CLK) = 33MHz

V V

µA

Ω

V V

µA

CC2

Supply Current (Standby) FWH

FWH4 = 0.1 V

All other inputs 0.9 VCC to 0.1 V

, VPP = V

VCC = 3.6V, f(CLK) = 33MHz

= VCC max, VPP = V

CC3

(Any internal operation

FWH

active)

Supply Current

CC4

CC5

PP1

Note: 1. Sampled only, not 100% tested.

Supply Current (Read) A/A Mux Supply Current

(1)

(Program/Erase)

A/A Mux Program/Erase Controller Active 20 mA

VPP Supply Current (Read/Standby)

VPP Supply Current

(1)

(Program/Erase active)

2. Input leakage currents in cl ude High-Z output leak age for all bi-directional buffers with tri-s tate outp ut s.

f(CLK) = 33MHz

= VIH, f = 6MHz

= 0mA

OUT

= V

= 12V ± 5%

10 mA

60 mA

20 mA

400

15 mA

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µA µA

Page 22

M50FW016

Table 21. FWH Interface Clock Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Test Condition Value Unit

CYC

CLK Cycle Time

(1)

Min 30 ns

HIGH

LOW

CLK High Time Min 11 ns CLK Low Time Min 11 ns

Min 1 V/ns

CLK Slew Rate peak to peak

Max 4 V/ns

Note: 1. Devic es on the PCI Bus must work with a ny clock frequency be tw een DC and 33MHz. Be l ow 16MHz dev i ces may be guarantee d

by design rather than tested. Refer to PCI Specification.

Figure 9. FWH Interface Clock Waveform

tCYC

tHIGH tLOW

0.6 V

0.5 V

0.4 V

0.3 V

0.2 V

CC CC CC CC

0.4 VCC, (minimum)

p-to-p

AI03403

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Page 23

Table 22. FWH Interface AC Signal Timing Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol

PCI

Symbol

Parameter Test Condition Value Unit

M50FW016

CHQV

(1)

CHQX

CHQZ

AVCH

DVCH

CHAX

CHDX

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-

ification.

2. Applies to all inputs except CLK.

VAL

OFF

CLK to Data Out

CLK to Active

(Float to Active Delay) CLK to Inactive

(Active to Float Delay)

Input Set-up Time

Input Hold Time

(2)

Min 2 ns

Max 11 ns

Min 2 ns

Max 28 ns

Min 7 ns

Min 0 ns

Figure 10. FWH Interface AC Signal Timing Waveforms

CLK

FWH0-FWH3

tCHQV

VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA

tCHQZ tCHQX

tDVCH

tCHDX

VALID

AI03405

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M50FW016

Table 23. Reset AC Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Test Condition Value Unit

PLPH

PLRH

PHFL

PHWL

PHGL

Note: 1. See Chapter 4 of the PCI Specif i cation.

RP or INIT Reset Pulse Width Min 100 ns

RP or INIT Low to Reset

or INIT Slew Rate

(1)

RP or INIT High to FWH4 Low FWH Interface only Min 30 RP High to Write Enable or Output

Enable Low

Figure 11. Reset AC Waveforms

RP, INIT

W, G, FWH4

Program/Erase Inactive Max 100 ns

Program/Erase Active Max 30

Rising edge only Min 50 mV/ns

A/A Mux Interface only Min 50

tPLPH

tPHWL, tPHGL, tPHFL

tPLRH

AI03420

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Page 25

M50FW016

Table 24. A/A Mux Interface Read AC Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Test Condition Value Unit

AVAV

AVCL

CLAX

AVCH

CHAX

CHQV

GLQV

PHAV

GLQX

GHQZ

GHQX

Note: 1. G may be delayed up to t

Read Cycle Time Min 250 ns Row Address Valid to RC Low Min 50 ns RC Low to Row Address Transition Min 50 ns Column Address Valid to RC high Min 50 ns RC High to Column Address Transition Min 50 ns

(1)

RC High to Output Valid Max 150 ns

(1)

Output Enable Low to Output Valid Max 50 ns RP High to Row Address Valid Min 1

Output Enable Low to Output Transition Min 0 ns Output Enable High to Output Hi-Z Max 50 ns Output Hold from Output Enable High Min 0 ns

– t

CHQV

after the ri si ng edge of RC without impact on t

GLQV

Figure 12. A/A Mux Interface Read AC Waveforms

tAVAV

CHQV

A0-A10

DQ0-DQ7

ROW ADDR VALID NEXT ADDR VALID

tAVCL tAVCH

tCLAX tCHAX

tPHAV

COLUMN ADDR VALID

tCHQV

tGLQV tGLQX

tGHQZ tGHQX

VALID

AI03406

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Page 26

M50FW016

Table 25. A/A Mux Interface Write AC Characteristics

= 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)

Symbol Parameter Test Condition Value Unit

WLWH

DVWH

WHDX

AVCL

CLAX

AVCH

CHAX

WHWL

CHWH

VPHWH

WHGL

WHRL

QVVPL

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

Write Enable Low to Write Enable High Min 100 ns Data Valid to Write Enable High Min 50 ns Write Enable High to Data Transition Min 5 ns Row Address Valid to RC Low Min 50 ns RC Low to Row Address Transition Min 50 ns Column Address Valid to RC High Min 50 ns RC High to Column Address Transition Min 50 ns Write Enable High to Write Enable Low Min 100 ns RC High to Write Enable High Min 50 ns

(1)

VPP High to Write Enable High Write Enable High to Output Enable Low Min 30 ns

Write Enable High to RB Low Min 0 ns

(1,2)

Output Valid, RB High to VPP Low

is seen as a logic i nput (VPP < 3.6V ).

Min 100 ns

Min 0 ns

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Page 27

Figure 13. A/A Mux Interface Write AC Waveforms

M50FW016

A0-A10

DQ0-DQ7

Write erase or program setup

tAVCL

tWLWH

tCLAX

tWHWL

Write erase confirm or valid address and data

R2 C2

tAVCH

tCHAX

tVPHWH tWHGL

tWHRL

IN1

Automated erase or program delay

tCHWH

IN2

Read Status

tQVVPL

tWHDXtDVWH

VALID SRD

Ready to write

another command

AI04194

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M50FW016

Figure 14. Program Flow c hart and Pseudo Code

Start

FWH

Interface

Only

Write 40h or 10h

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

Suspend

Program to Protected

Block Error (1, 2)

YES

Suspend

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Program command: – write 40h or 10h – write Address & Data (memory enters read status state after the Program command)

do: –read Status Register if Program/Erase Suspend command given execute suspend program loop

Loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4 = 1, Program error: – error handler

If b1 = 1, Program to protected block error: – error handler

AI03407

Note: 1. A Status check of b1 (Protected Block), b3 (VPP invalid ) and b4 (Pro gram Er ror) can be made after each P rogra m operati on by

following the correct command se quence.

2. If an error is foun d, the Status Register m ust be cleared before further Prog ram /Erase Controller operation s.

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Page 29

M50FW016

Figure 15. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 30h

Write Address 1

Write Address 2

Write Address 3

Write Address 4

Read Status

& Data 1

& Data 2

& Data 3

& Data 4

b7 = 1

b3 = 0

(3)

YES

Suspend

YES

Suspend

VPP Invalid

Error (1, 2)

Loop

Quadruple Byte Program command: – write 30h – write Address 1 & Data 1 – write Address 2 & Data 2 – write Address 3 & Data 3 – write Address 4 & Data 4 (memory enters read status state after the Quadruple Byte Program command)

do: – read Status Register if Program/Erase Suspend command given execute suspend program loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

(3) (3) (3) (3)

b4 = 0

End

Note: 1. A Sta t u s check of b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by following the correct com-

mand sequence.

2. If an error is foun d, the Status Register m ust be cleared before further Prog ram /Erase Controller operation s.

3. Address 1, Address 2, Addre ss 3 and Addres s 4 m ust be consecutive addr esses differing only for address bit s A 0 and A1.

YES

Program

Error (1, 2)

If b4 = 1, Program error: – error handler

AI03982

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M50FW016

Figure 16. Quadruple Byte Program Flowchart and Pseudo Code (FWH Interface Only)

Start

Write 30h

Write Start Address

and 4 Data Bytes

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

(3)

Suspend

Program to Protected

Block Error (1, 2)

YES

Suspend

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Loop

Quadruple Byte Program command: – write 30h – write Start Address and 4 Data Bytes (memory enters read status state after the Quadruple Byte Program command)

do: – read Status Register if Program/Erase Suspend command given execute suspend program loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4 = 1, Program error: – error handler

If b1 = 1, Program to protected block error: – error handler

(3)

YES

End

AI05736B

Note: 1. A Sta t u s check of b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by following the correct com-

mand sequence.

2. If an error is foun d, the Status Register m ust be cleared before further Prog ram /Erase Controller operation s.

3. A1 and A0 ar e treated as Don’t Care. Starting a t the Start Address, the fi rst data byt e is pro gram m ed at th e address that has A1-

A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that has A1-A0 at 10, and the fourth at the address that has A1-A0 at 11.

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Page 31

Figure 17. Program Suspend and Resume Flowchart, and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h

Read Status

– write B0h – write 70h

do: – read Status Register

M50FW016

b7 = 1

YES

b2 = 1

YES

Write a read

Command

Read data from

another address

Write D0h

Program Continues

Program Complete

Write FFh

Read Data

while b7 = 1

If b2 = 0 Program completed

Program/Erase Resume command: – write D0h to resume the program – if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).

AI03408

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M50FW016

Figure 18. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 80h

Write 10h

Read Status

YES

VPP Invalid

Error (1)

Command

Sequence Error (1)

b7 = 1

b3 = 0

b4, b5 = 0

b5 = 0 Erase Error (1)

Chip Erase command: – write 80h – write 10h (memory enters read Status Register after the Chip Erase command)

do: – read Status Register

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4, b5 = 1, Command sequence error: – error handler

If b5 = 1, Erase error: – error handler

YES

End

Note: 1. If an er ror is found, the Status Register must be cleared before further Prog ram /Erase Controller operation s.

32/37

AI04195

Page 33

Figure 19. Block Erase Flowchart and Pseudo Code

Start

M50FW016

Write 20h

Write Block Address

& D0h

Read Status

b7 = 1

b3 = 0

b4, b5 = 0

b5 = 0 Erase Error (1)

YES

Suspend

Sequence Error (1)

VPP Invalid

Error (1)

Command

Block Erase command: – write 20h – write Block Address & D0h (memory enters read Status Register after the Block Erase command)

do: – read Status Register – if Program/Erase Suspend command given execute suspend erase loop

YES

Suspend

Loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4, b5 = 1, Command sequence error: – error handler

If b5 = 1, Erase error: – error handler

YES

FWH

Interface

Only

Note: 1. If an er ror is found, the Status Register must be cleared before further Prog ram /Erase Controller operation s.

b1 = 0

End

YES

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error: – error handler

AI04196

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M50FW016

Figure 20. Erase Suspend and Resume Flow chart, and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h

– write B0h – write 70h

Read Status

b7 = 1

YES

b6 = 1

YES

Read data from

another block

Program

Write D0h

Erase Continues

Erase Complete

Write FFh

Read Data

do: – read Status Register

while b7 = 1

If b6 = 0, Erase completed

Program/Erase Resume command: – write D0h to resume erase – if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued).

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AI03410

Page 35

Table 26. Ordering Information Scheme

Example: M50FW016 N1T

Device Type

M50

Architecture

F = Firmware Hub Interface

Operating Voltage

W = 3.0 to 3.6V

Device Function

016 = 16 Mbit (2Mb x8), Uniform Block

Package

N = TSOP40: 10 x 20 mm

Temperature Range

1 = 0 to 70 °C 5 = –20 to 85°C

M50FW016

Option

T = Tape & Reel Packing

For a list of available options or for furt her information on any aspect of this device, please contact the ST Sales Office nearest to you.

Table 27. Revision History

Date Version Revision Details

May 2001 -01 First Issue

October 2001 -02

21-Feb-2002 -03 Removed LPC Bus Read and Bus Write cycles 01-Mar-2002 -04 RFU pins must be left disconnected

30-Jul-2002 -05 Quadruple Byte Mode changed to 4/16/128 bytes

13-Feb-2003 5.1

Added LPC Bus Read and Bus Write cycles Added FWH 64 and 128 byte Bus Reading

Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 05 equals 5.0) Datasheet promoted from Product Preview to Preliminary Data status.

35/37

Page 36

M50FW016

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

Note: Drawing is not to scale.

1 N

N/2

TSOP-a

DIE

LA1 α

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechan ic al Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

millimeters inches

A2 0.950 1.050 0.0374 0.0413

B 0.170 0.270 0.0067 0 .0106 C 0.100 0.210 0.0039 0.0083 D 19.800 20.200 0.7795 0.7953

D1 18.300 18.500 0.7205 0 .7283

E 9.900 10.100 0.3898 0.3976

e 0.500 – – 0.0197 – –

L 0.500 0.700 0.0197 0.0276

0° 5° 0° 5°

N40 40

CP 0.100 0.0039

36/37

Page 37

M50FW016

Information furnished is believed to be ac curate and reli able. Howev er, STMicroel ectronics assumes no responsibilit y for the consequence s of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout express written ap proval of STMi croelect ro nics.

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