Datasheet M48Z30-100PM1 Datasheet (SGS Thomson Microelectronics)

INTEGRATED LOW POWER SRAM,
POWER-FAILCONTROL CIRCUIT and
BATTERY

CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITECYCLES

10 YEARSof DATA RETENTION in the
ABSENCEof POWER

M48Z30

M48Z30Y

CMOS 32K x 8 ZEROPOWERSRAM

PIN and FUNCTION COMPATIBLEwith
JEDECSTANDARD 32K x 8SRAMs

AUTOMATIC POWER-FAILCHIP DESELECT
and WRITEPROTECTION

CHOICEof TWOWRITE PROTECT
VOLTAGES:

– M48Z30:4.5V ≤ V
– M48Z30Y:4.2V≤ V

PFD

PFD

≤ 4.75V

≤ 4.50V

BATTERYINTERNALLYISOLATEDUNTIL
POWERIS APPLIED

DESCRIPTION



The M48Z30/30Y32K x 8 ZEROPOWER

RAMis
a non-volatile262,144bitStaticRAMorganizedas
32,768 words by 8 bits. The device combines an
internallithium batteryand a full CMOSSRAMina
plastic 28 pin DIP Module. The ZEROPOWER

Table 1. Signal Names

A0 - A14 Address Inputs

28

1

PMDIP28 (PM)

Module

Figure 1. Logic Diagram

DQ0 - DQ7 Data Inputs / Outputs

E Chip Enable

G Output Enable

W Write Enable

V

CC

V

SS

July 1994 1/12

Supply Voltage

Ground

M48Z30, M48Z30Y

Table 2. Absolute MaximumRatings

Symbol Parameter Value Unit

T

A

T

STG

T

BIAS

T

SLD

V

IO

V

CC

Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to the absolute maximumratings conditions for extended periods of time may affect reliability.

CAUTION: Negative undershootsbelow –0.3 volts are notallowed onany pin while in the Battery Back-up mode.

Table 3. OperatingModes

Ambient Operating Temperature 0 to 70 °C
Storage Temperature(VCCOff) –40 to 70 °C
Temperature Under Bias –10 to 70 °C
Lead Soldering Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to7 V
Supply Voltage –0.3 to7 V

Mode V

CC

Deselect

Write V

Read V

4.75V to 5.5V
or

4.5V to 5.5V

Read V

Deselect V

SO

Deselect ≤ V

Note:X=VIHor V

IL

to V

(min) X X X High Z CMOS Standby

PFD

SO

Figure2. DIP Pin Connections

E G W DQ0-DQ7 Power

V

IH

IL

IL

IL

X X High Z Standby
XVILD

V

IL

V

IH

V

IH

V

IH

IN

D

OUT

High Z Active

Active
Active

X X X High Z Battery Back-up Mode

DESCRIPTION (cont’d)
RAMdirectlyreplacesindustrystandardSRAMs.It

alsofits into manyEPROMandEEPROM sockets,
providing the nonvolatilityof PROMs without any
requirement for special write timing or limitations
on the number of writes that can be performed.

The M48Z30/30Y has its own Power-fail Detect
Circuit.Thecontrolcircuitryconstantlymonitorsthe
single5V supply for an out of tolerancecondition.
When V

is out of tolerance, the circuit write

CC

protectstheSRAM,providinga highdegreeofdata
security in the midst of unpredictable system op­erationsbrought onby lowV

.AsVCCfallsbelow

CC

approximately3V,the controlcircuitryconnectsthe
battery which sustains data until valid power re­turns.

2/12

READMODE

The M48Z30/30Y is in the Read Mode whenever
W(Write Enable)ishighandE(ChipEnable)islow.
The device architecture allows ripple-through ac­cessof data from eight of 262,144locations in the
static storage array. Thus, the unique address

Figure3. Block Diagram

M48Z30, M48Z30Y

specified by the 15 Address Inputs defines which
one of the32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within t

(Address Access Time) after the last

AVQV

addressinput signal is stable, providing that theE
and G (OutputEnable) access times are alsosat­isfied.If theE andGaccesstimesarenotmet, valid
data will be availableafter the later ofChipEnable
AccessTime(t

).

(t

GLQV

)orOutputEnableAccessTime

ELQV

The state of the eight three-stateData I/Osignals
iscontrolledbyEand G.Iftheoutputsareactivated
before t
indeterminate state until t

, the data lines will be driven to an

AVQV

. If the Address In-

AVQV

putsare changedwhile Eand Gremainlow, output
data will remain valid for t

(Output Data Hold

AXQX

Time) but will go indeterminate until the next Ad­dressAccess.

WRITE MODE

TheM48Z30/30Yis inthe Write ModewheneverW
and E are active.The start of a write is referenced
fromthe latter occurring falling edge of W or E.

AC MEASUREMENT CONDITIONS

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data
is no longer driven.

Figure 4. AC TestingLoad Circuit

3/12

M48Z30, M48Z30Y

Table4. Capacitance

(1, 2)

(TA=25°C, f = 1 MHz)

Symbol Parameter TestCondition Min Max Unit

C

IN

(3)

C

IO

Notes:1. Effective capacitance measured with power supply at 5V.

2. Sampled only,not 100% tested.

3. Outputs deselected

Input Capacitance VIN=0V 10 pF
Input / Output Capacitance V

=0V 10 pF

OUT

Table 5. DC Characteristics (TA= 0 to 70°C;VCC= 4.75V to 5.5Vor 4.5Vto 5.5V)

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

(1)

I

LO

I

CC

I

CC1

I

CC2

V

IL

V

IH

V

OL

V

OH

Note: 1. Outputs deselected.

Input Leakage Current 0V ≤ VIN≤ V
Output Leakage Current 0V ≤ V

OUT

≤ V

CC

CC

±1 µA
±1 µA

Supply Current E = VIL, Outputs open 85 mA
Supply Current (Standby) TTL E = V

IH

7mA
Supply Current (Standby) CMOS E≥ VCC– 0.2V 4 mA
Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2 VCC+ 0.3 V
Output Low Voltage IOL= 2.1mA 0.4 V
Output High Voltage IOH= –1mA 2.4 V

Table6. Power Down/Up Trip Points DC Characteristics

(1)

(TA=0 to 70°C)

Symbol Parameter Min Typ Max Unit

V

PFD

V

PFD

V

SO

t

DR

Notes: 1. All voltages referenced to VSS.

2. @ 25°C

Power-fail Deselect Voltage(M48Z30) 4.5 4.6 4.75 V
Power-fail Deselect Voltage(M48Z30Y) 4.2 4.3 4.5 V
Battery Back-up Switchover Voltage 3 V

(2)

Data Retention Time 10 YEARS

4/12

M48Z30, M48Z30Y

Table 7. Power Down/Up Mode AC Characteristics(TA= 0 to 70°C)

Symbol Parameter Min Max Unit

(1)

t

F

(2)

t

FB

V

(max) to V

PFD

V

(min) to VSOVCCFall Time 10 µs

PFD

(min) VCCFall Time 300 µs

PFD

t

WP

t

R

t

ER

Notes:1.V

2. V

V

Write Protect Time from VCC=V
VSOto V

(max) VCCRise Time 0 µs

PFD

PFD

E Recovery Time 40 120 ms

(max) to V

PFD

passes V

CC

(min) to VSOfall time of less than tFBmay cause corruption of RAM data.

PFD

(min) fall time of less than tFmay result in deselection/write protection not occurring until 200 µs after

PFD

(min).

PFD

Figure5. Power Down/Up Mode AC Waveforms

40 150 µs

5/12

M48Z30, M48Z30Y

Table8. ReadMode AC Characteristics (TA=0 to 70°C; VCC=4.75V to 5.5V or 4.5Vto 5.5V)

M48Z30 / 30Y

Symbol Parameter

-85 -100

Min Max Min Max

Unit

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

Notes: 1. CL= 100pF (see Figure 4).

2. C

Read Cycle Time 85 100 ns

(1)

Address Validto Output Valid 85 100 ns

(1)

Chip Enable Low to Output Valid 85 100 ns

(1)

Output EnableLow to Output Valid 45 50 ns

(2)

Chip Enable Low to Output Transition 5 5 ns

(2)

Output EnableLow to Output Transition 5 5 ns

(2)

Chip Enable High to Output Hi-Z 40 40 ns

(2)

Output EnableHigh to Output Hi-Z 35 35 ns

(1)

Address Transitionto Output Transition 10 10 ns

= 5pF(see Figure 4)

L

Figure6. AddressControlled,Read Mode AC Waveforms

Note: E = Low, G= Low, W= High.

6/12

Figure7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

M48Z30, M48Z30Y

Note: W = High.

WRITE MODE (cont’d)

Awriteis terminatedby the earlier risingedge of W
or E. Theaddressesmust be heldvalidthroughout
the cycle. E or W mustreturn high for minimum of
t

EHAX

fromE or t

fromW prior to the initiation

WHAX

ofanotherread orwritecycle.Data-inmust bevalid

priorto the end of write andremain validfor

t

DVWH

t

WHDX

or t

afterward. G should be kept high

EHDX

during write cycles to avoid bus contention; al­though, if the output bus has been activatedby a
lowonE andG, a low onWwill disablethe outputs

after W falls.

t

WLQZ

DATA RETENTION MODE

Withvalid V
as a conventional BYTEWIDE

applied,the M48Z30/30Yoperates

CC

TM

static RAM.

Should the supply voltage decay, the RAM will

automatically power-fail deselect, write protecting
itself t

after VCCfalls below V

WP

. All outputs

PFD

becomehigh impedance,andall inputsaretreated
as ”don’tcare.”

If powerfail detectionoccursduringa validaccess,
the memory cycle continues to completion. If the
memorycyclefails to terminate withinthetime t

WP

write protection takes place. When Vcc drops be­low V

, the control circuit switches power to the

SO

internal energy sourcewhich preserves data.
The internal coin cell will maintain data in the

M48Z30/30Y after the initialapplicationof V

CC

for

an accumulated period of at least 10 years when

islessthanVSO. Assystem powerreturnsand

V

CC

Vcc risesabove V

, the battery is disconnected,

SO

and the power supply is switched to externalVcc.
Writeprotectioncontinuesfort

to allow for processor stabilization. AftertER,

V

PFD

afterVCCreaches

ER

normal RAMoperation can resume.

,

7/12

M48Z30, M48Z30Y

Table 9. Write Mode AC Characteristics (TA= 0 to70°C; VCC=4.75V to 5.5V or 4.5Vto 5.5V)

M48Z30 / 30Y

Symbol Parameter

-85 -100

Min Max Min Max

Unit

t

AVAV

t

AVWL

t

AVEL

t

WLWH

t

ELEH

t

WHAX

t

EHAX

t

DVWH

t

DVEH

t

WHDX

t

EHDX

t

WLQZ

t

AVWH

t

AVEH

t

WHQX

Notes: 1. CL= 5pF (see Figure 4).

2. If E goes low simultaneously with Wgoing low after W going low, the outputs remain in the high-impedance state.

Write Cycle Time 85 100 ns
Address Validto Write Enable Low 0 0 ns
Address Validto Chip Enable Low 0 0 ns
Write Enable Pulse Width 65 75 ns
Chip Enable Low to ChipEnable High 75 90 ns
Write Enable High to Address Transition 5 5 ns
Chip Enable High to Address Transition 15 15 ns
Input Valid to Write Enable High 35 40 ns
Input Valid to Chip Enable High 35 40 ns
Write Enable High to Input Transition 0 0 ns
Chip Enable Highto Input Transition 15 15 ns

(1,2)

Write Enable Low to Output Hi-Z 35 35 ns
Address Validto Write Enable High 75 80 ns
Address Validto Chip Enable High 75 80 ns

(1,2)

Write Enable High to Output Transition 5 5 ns

8/12

Figure8. WriteEnable Controlled, Write AC Waveforms

M48Z30, M48Z30Y

Note: G =High.

Figure9. Chip Enable Controlled, Write ACWaveforms

Note: G =High.

9/12

M48Z30, M48Z30Y

ORDERING INFORMATION SCHEME

Example: M48Z30Y -85 PM 1

Supply Voltageand Write

Protect Voltage

30 V

30Y V

= 4.75V to 5.5V

CC

V

= 4.5V to 4.75V

PFD

= 4.5V to 5.5V

CC

V

= 4.2V to 4.5V

PFD

Speed

-85 85ns

-100 100ns

Package

PM PMDIP28

Temp.Range

1 0 to 70°C

For a list of availableoptions (Package and Speed) refer to the current Memory Shortformcatalogue.
For further information or any aspect of this device, please contact the SGS-THOMSON Sales Office

nearestto you.

10/12

PMDIP28 - 28 pin Plastic DIP Module

M48Z30, M48Z30Y

Symb

Typ Min Max Typ Min Max

A 9.27 9.52 0.365 0.375

A1 0.38 – 0.015 –

B 0.43 0.59 0.017 0.023
C 0.20 0.33 0.008 0.013
D 37.34 38.10 1.470 1.500

E 18.03 18.80 0.710 0.740

e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430

eA 14.99 16.00 0.590 0.630

L 3.05 3.81 0.120 0.150

S 1.91 2.79 0.075 0.110
N28 28

PMDIP28

mm inches

Drawing is notto scale

A1AL

S

Be1

eA

C

e3

D

N

E

1

PMDIP

11/12

M48Z30, M48Z30Y

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under anypatentor patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics productsare notauthorized for use as critical components in life supportdevices or systemswithout express
written approval of SGS-THOMSON Microelectronics.

 1994 SGS-THOMSON Microelectronics - AllRights Reserved

 ZEROPOWER is a registered trademark of SGS-THOMSON Microelectronics

 BYTEWIDE is a trademark of SGS-THOMSON Microelectronics

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12/12