Datasheet M29W640DT, M29W640DB Datasheet (SGS Thomson Microelectronics)

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Page 1

64 Mbit (8Mb x8 or 4Mb x16, Boot Block)

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V –V

■ ACCESS TIME: 70, 90 ns

■ PROGRAMMING TIME

– 10 µs per Byte/Word typical – Double Word Programming Option

■ 135 MEMORY BLOCKS

– 1 Boot Block and 7 Parameter Blocks,

– 127 Main Blocks, 64 KBytes each

■ PROGRAM/E RA SE CONTROLLER

– Embedded Byte/Word Program algorithms

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programm ing

■ V

PROTECT

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ COMMON FLASH INTERFACE

– 64-bit Security Code

■ EXTENDED MEMORY BLOCK

– Extra block used as security block or to store

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ER ASE CYCL ES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h – Top Device Code M29W640DT: 22DEh – Bottom Device Code M29W640DB: 22DFh

2.7V to 3.6V for Program, Erase, Read

CC =

=12 V for Fast Program (optional)

8 KBytes each (Top or Bottom Location)

Erase Suspend

/WP Pin for FAST PROGRAM and WRITE

additional information

M29W640DT

M29W640DB

3V Supply Fl ash Me m ory

PRELIMINARY DATA

Figure 1. Packages

TSOP48 (N)

12 x 20mm

FBGA

TFBGA63 (ZA)

63 ball array

April 2003

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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M29W640DT, M29W640DB

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output or Address Input (DQ15A–1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (V

PP/

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PP/

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations, BYTE = V Table 3. Bus Operations, BYTE = V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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Erase Suspend Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Exit Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Commands, 16-bit mode, BYTE = V Table 5. Commands, 8-bit mode, BYTE = V

Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 17

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Operating and AC Measurement Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 13. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 27

Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 27

Figure 15. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline . . . . . . . . . . 28

Table 17. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . . 28

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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APPENDIX A. BLOCK ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19. Top Boot Block Addresses, M29W640DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20. Bottom Boot Block Addresses, M29W640DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 21. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 22. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 23. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 24. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 25. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 26. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Customer Lockable Extended Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 27. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX D. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 28. Programmer Technique Bus Operations, BYTE = V

or VIL . . . . . . . . . . . . . . . . . . . . . 44

Figure 16. Programmer Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 18. In-System Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

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SUMMARY DESCRIPTION

The M29W640D is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory d efaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is pos sible to pres erve valid data while old data is erased. Blocks can be protected in units of 256 KByte (generally groups of four 64 KByte blocks), to prevent accidental Program or Erase commands from modifying the memory. Program and Erase com m ands are wri tten to the Command Interface of t he memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase op eration can be de tected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The device features an asymmetrical blocked architecture. The device has an array of 135 blocks:

■ 8 Parameters Blocks of 8 KBytes each (or

4KWords each)

■ 127 Main Blocks of 64 KBytes each (or

32 KWords each)

M29W640DT has the Parameter Blocks at the top of the memory address space while the M29W640DB locates the Parameter Blo cks starting from the bottom.

The M29W640D has an extra block, the Extended Block, (of 32 KWords in x16 mode or of 64 KBytes in x8 mode) that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple conne ction to most m icroprocessors, often without additional logic.

The V

/WP signal is used to enable faster pro-

gramming of the device, enabling double word programming. If this signal is held at V

, the boot

block, and its adjacent parameter blo ck, are protected from program and erase operations.

The memor y is del ivered with all t he bit s eras ed (set to 1).

M29W640DT, M29W640DB

Figure 2. Logic Diagram

VPP/WP

A0-A21

Table 1. Signal Names

A0-A21 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 (or DQ15)

E G W RP RB BYTE V

VPP/WP

M29W640DT

M29W640DB

Data Input/Output or Address Input (or Data Input/Output)

Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select Supply Voltage Supply Voltage for Fast Program

(optional) or Write Protect

DQ0-DQ14

DQ15A–1 BYTE RB

AI05733

NC Not Connected Internally

Ground

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M29W640DT, M29W640DB

Figure 3. TSOP Connections

A15

48 A14 A13 A12 A11 A10 DQ14

A8 A19 A20

M29W640DT M29W640DB

A21

12 13

37 36

VPP/WP

RB A18 A17

A7 A6 A5 A4 A3 A2 A1

24 25

AI05734

A16 BYTE V

DQ15A–1 DQ7

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

E A0

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Figure 4. TFBGA Connections (Top view through package)

M29W640DT, M29W640DB

(1)

A12A13

A15A14

A16

BYTE

A11 DQ7

A20

DQ2

DQ12DQ5A19A21

A1A2

(1)

A0A4A3

CBAEDFGH

DQ15

A–1

DQ6DQ13DQ14A10A8A9

DQ4

DQ3DQ11DQ10A18

DQ1DQ9DQ8DQ0A6A17A7

JKLM

(1)

Note: 1. Bal l s ar e shorted to get her via the substrate but not connec ted to the die.

AI05735

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M29W640DT, M29W640DB

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and T able 1, Sign al Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A21). The Address Inputs select the cells i n the memory array to a ccess during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when B Y TE V

. When BYTE is Low, VIL, these pins are not

used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

Data Input/Output o r Address Input (DQ15A –1).

When BYTE

is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

is Low, VIL, this pin behaves as an address

BYTE

pin; DQ15A–1 Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE High and references to the Address Inputs to include this pin when BYTE

is Low except when

stated explicitly otherwise.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V

Output Enable (G

, all other pins are ignored.

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a c e .

Write Protect (VPP/WP). The VPP/Write

PP/

Protect

pin provides two functions. The VPP function allo ws the memory to use an exte rnal high volt age power suppl y t o reduce t he time r e quire d for Unlock Bypass Program operations. The Write P ro tec t func ti on pr ov i des a ha rd ware met hod of protecting the two outermost boot blocks. The V

/Write Protect pin must not be left floating

or unconnected. When V

/Write Protect is L ow , VIL, the memory

protects the two outermost boot blocks; Program

is High,

and Erase operations in this block are ignored while V

When V

/Write Protect is Low.

/Write Protect is High, VIH, the memo r y

reverts to the previous protection status of the two outermost boot blocks. Program and Erase operations can now modify the data in the two outermost boot blocks unless the block is protected using Block Protection.

When V

/Write Protect is raised to V

the mem-

ory automatically enters the Unlock Bypass mode. When V

/Write Protect returns to VIH or VIL nor-

mal operation resumes. During Unlock Bypass Program operations the memory draws I

from the pin to supply the programming circuits. See the description of the Unlock Bypass comm and in the Command Interface section. The transitions from V

to VPP and from VPP to VIH must be slower

than t Never raise V

, see Figure 13.

VHVPP

/Write Protect to VPP from any

mode except Read m ode, otherwise the memory may be left in an indeterminate state.

A 0.1µF capacitor should be connected between the V

/Write Protect pin and the VSS Ground pin

to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, I

Reset/Block Temporary Unprotect (RP

). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that hav e b een protected.

Note that i f V

/WP is at VIL, then the two ou ter-

most boot blocks will remain protected even if RP

is at V A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V

. After Reset/Block Temporary Unprotect

PLPX

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t t

, whichever occurs last. See the Ready/Busy

RHEL

, for at least

PHEL

Output section, Table 15 and Figure 12, Reset/ Block Temporary Unprotect AC Characteristics, for more details.

Holding RP

at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from V t

PHPHH

Ready/Busy Output (RB

to VID must be slower than

). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, V

. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode and Erase Suspend mode.

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M29W640DT, M29W640DB

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Tabl e 15 and Figure 12, Reset/Block Temporary Unprotect AC Characteristics.

The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE

). The

Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organizati on Select is Low, V High, V

, the memory is in x8 mode, when it is

, the memory is in x16 mode.

Supply Voltage (2.7V to 3.6V). VCC pro- vides the power supply for all operations (Read, Program and Erase).

The Command Interface is disabled when the V

Supply Voltage is less than the L ockout Voltage, V

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor should be connected between the V

Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, I

Ground. VSS is the reference for all voltage

measurements. The device f eatu res two V

CC3

pins

which must be both connected to the system ground.

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BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Wri te, Output Disable, Standby and Automatic Standby. See Table 2 and T able 3, Bus Operat ions, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low sig nal, V and Output Enable and keeping Write Enable High, V

. The Data Inputs/Outputs will output the

value, see Figure 9, Read Mode AC Waveforms, and Table 12, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desire d address on t he Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs a re latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V

Write operation. See Figure 10 and Figure 11, Write AC Waveforms, and Table 13 and Table 14, Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . The Data Inputs/Outputs are in the high impedance s tate when Output Enable is High, V

Standby. When Chip Enable is High, V memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the S upply Current to the Standby Supply Current, I

CC2

, to Chip Enable

, during the whole Bus

, the

, Chip Enable should

be held within V

± 0.2V. For the Standby current

level see Table 11, DC Characteristics. During program or erase operations the memory

will continue to use the Program/Erase Supply Current, I

, for Program or Erase operations un-

CC3

til the operation completes. Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, I

CC2

. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protec tion. These bus operations are intended for use by programming equipment and are not usually used in applications. They require V

to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying t he signals listed in Table 2 and Table 3, Bus Operations.

Block Protect and Chip Unprotect.

Groups of blocks can be protected against accidental Program or Erase. The P rotec tion G roups are shown in Appendix A, Table 19 and Table 20, Block Addresses. The whole chip can be unprotected to allow the data inside the blocks to be changed.

The V the two outermost boot blocks. When V Protect

/Write Protect pin ca n be used to prote c t

is at V

the two outermost boot blocks are

/Write

protected an d remain pr otected regardless of t he Block Protection Status or the Reset/Block Temporary Unprotect pin status.

Block Protect and Chip Unprote ct operations are described in Appendix D.

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Table 2. Bus Operations, BYTE = V

Operation E G W

Bus Read Bus Write Output Disable X Standby Read Manufacturer

Code

Read Device Code

Extended Memory Block Verify Code

Note: X = VIL or VIH.

V V

X X X Hi-Z Hi-Z

Table 3. Bus Operations, BYTE = V

Operation E

Bus Read Bus Write Output Disable X Standby Read Manufacturer

Code

Read Device Code

Extended Memory Block Verify Code

Note: X = VIL or VIH.

V V

G W

X X X Hi-Z

Address Inputs

DQ15A–1, A0-A21

Cell Address Hi-Z Data Output

Command Address Hi-Z Data Input

X Hi-Z Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others V A0 = VIH, A1 = VIL,

A9 = V

or V

, Others VIL or V

DQ14-DQ8 DQ7-DQ0

Data Inputs/Outputs

Hi-Z 20h

Hi-Z

DEh (M29W640DT) DFh (M29W640DB)

98h (factory locked)

A0 = VIH, A1 = VIH, A6 = VIL,

A9 = V

, Others VIL or V

Hi-Z

18h (not factory locked)

88h (factory locked)

08h (not factory locked)

Address Inputs

A0-A21

Cell Address Data Output

Command Address Data Input

X Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others V A0 = VIH, A1 = VIL, A9 = VID,

Others V

or V

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

22DEh (M29W640DT) 22DFh (M29W640DB)

M29W640DT

98h (factory locked)

A0 = VIH, A1 = VIH, A6 = VIL,

A9 = V

, Others VIL or V

18h (not factory locked)

M29W640DB

88h (factory locked)

08h (not factory locked)

M29W640DT

M29W640DB

0020h

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COMMAND INTERFACE

All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 4, or Table 5, depending on the configuration that is being used, for a summary of the commands.

Read/Reset Command.

The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a Block erase operation then

the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend.

Auto Select Command.

The Auto Select command is used to read the Manufacturer Code, the Device Code , the Block Protection Status and the Extended Memory Block Verify Code. Three c onsecutive Bus W rite operations are required to iss ue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset comma nds are ac cept ed i n Aut o Select mode, all other commands are ignored.

In Auto Select mode the Manufac turer Code can be read using a Bus Read operation with A0 = V and A1 = VIL. The other address bits may be set to either V Microelectronics is 0020h.

The Device Code can be read using a B us Read operation with A0 = V address bits may be set to e ither V Device Code for the M29W640DT is 22DEh and for the M29W640DB is 22DFh.

The Bl ock Prot ection S tatus of each block can be read using a Bus Read operation with A0 = V A1 = V the bl ock. The oth er addr ess bit s may b e set t o either V then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.

or VIH. The Manufacturer Code f or ST-

and A1 = VIL. The other

, and A 12 -A 21 spec ify i n g t he address of

or VIH. If t h e ad dr ess ed b loc k is pro tec te d

or VIH. The

Read CFI Query Command

The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read Array mode, or when the device is in Autose lec ted mode .

One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read ope rations read from the Common Flash Interface Memory Area.

The Read/Reset command m ust be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode.

See Appendix B, Table 21 to Table 26 for details on the information contained in the Common Flash Interface (CFI) memory area.

Program Command.

The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller.

If the address falls in a pro tected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operat ion the memo ry will ignore all commands. I t is n ot poss ible t o iss ue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program o peration will output the Status Register on the Data Inputs/Outputs. See the section on the S tatus Register for more details.

After the program operation has completed the memory will return to the Read mode, unle ss an

error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ’0’ bac k to ’1’. One of the E rase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Fast Program Commands

There are two Fast Program com man ds availa ble

to improve the programming throughput, by writing several adjacent words or bytes in parallel. The Quadruple Byte Program command is available for x8 operations, while the Double Word Program command is available for x16 operations.

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Quadruple Byte Program Command. The Qua-

druple Byte Program command is used to write a page of four adjacent Bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the Quadruple Byte Program command .

■ The first bus cycle sets up the Quadruple Byte

Program Command.

■ The second bus cycle latches the Address and

the Data of the first byte to be written.

■ The third bus cycle latches the Address and the

Data of the second byte to be written.

■ The fourth bus cycle latches the Address and

the Data of the third byte to be written.

■ The fifth bus cycl e latches the Addres s and th e

Data of the fourth byte to be written and starts the Program/Erase Controller.

Double Word Program Command. The Double Word Program command is used to write a p age of two adjacent words in parallel. Th e two words must differ only for the address A0.

Three bus write cycles are necessary to issue the Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts the Program/Erase Controller.

Only one bank can be programmed at any one time. The other b ank must be in Read mode or Erase Suspend.

Programming should not be attempted when V is not at V

PPH

After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other B ank outpu t the cont ents of t he memory ar ray.

After the program operation has completed the memory will return to the Read mode, unle ss an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return t o Read mode.

Note that the Fast Program commands cannot

change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Typical Program times are given in Tab le 6, Program, Erase Times and Program, Erase Endurance Cycles.

Unlock Bypass Command.

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When th e cycle time to the device is long (as with some EPROM programmers) considerable time saving can be m ade by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypas s command has bee n issued the memory will only accept the Unloc k Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

When V

is applied to the VPP/Write Protect pin

the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately.

Unlock Bypass Program Command.

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. Whe n the cycle time t o the device is long (as with some EPROM programmers) considerable time saving can be m ade by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypas s command has bee n issued the memory will only accept the Unloc k Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

The memory offers accelerated program operations through the V system asserts V

/Write Protect pin. When the

on the VPP/Write Protect pin,

the memory automatically enters the Unlock Bypass mode. The system may then write the twocycle Unlock Bypass program command sequence. The memory uses the higher voltage on the V

/Write Protect pin, to accelerate the Unlock

Bypass Program operation. Never raise V

/Write Protect to VPP from any

mode except Read m ode, otherwise the memory may be left in an indeterminate state.

Unlock Bypass Reset Command.

The Unlock Bypass Rese t command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/ Reset command does not exit from Unlock Bypass Mode.

Chip Erase Command.

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations a re re-

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M29W640DT, M29W640DB

quired to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protect e d th e Chip Erase op erat i on ap-

pears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the erase operation the memory will ignore all commands, including the Erase Suspen d command. It is not possible to i ssue any c ommand t o abort the operation. Typical chip erase tim es are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the Chip Erase operation has completed t he memory will return to the Read Mode, unle ss an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.

Block Erase Command.

The Block Erase com mand can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the li st. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The B lock Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Pr ogram /Erase Co ntroller st arts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth B us Write operation. See the Status Register section for details on how to identify if the Program/ Erase Con troller has st arted the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are p rotected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the Block Erase operation the me mory wi ll ignore all commands except the Erase Susp end command. Typical b lock era se tim es are g iven in Table 6. All Bus Read operations during the Block Erase ope ra tion will outp ut the S t atus R e gister on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode, unle ss an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.

Erase Suspend Command.

The Erase Suspend Command may be used to temporarily suspend a B lock Eras e operation and return the memory to Read mode. T he comm and requires one Bus Write operation.

The Program/Erase Controller will sus pend within the Erase Suspend Latency time of the Erase Suspend Command being issued. Once the Program/ Erase Controller has stopped the mem ory will be set to Read mode and the E ras e wi ll be s uspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Er ase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possibl e to select any further blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program comm and is ignored and the data remains unchanged. The Status Register is not read and no error condi tion is given. Reading from blocks that are being erased will output the Status Register.

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands du ring an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepte d.

Erase Resume Command.

The Erase Resume command must be used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspe nded and resumed mo re t han once.

Enter Extended Block Command

The device has an extra 64 KByte block (Extended Block) that can on ly be acc essed usin g the Enter Extended Block command. Three Bus write cycles are required to issue the Extended Block command. Once the c ommand has been issued the device enters Extended Block mode where all Bus

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M29W640DT, M29W640DB

Read or Write operations to the Boot Block addresses access the Extended Bloc k. The Extended Block (with the same address as the Boot Blocks) cannot be erased, and can be t reated as one-time programmable (OTP) memory. In Extended Block mode the Boot Blocks are not accessible.

To exit from the Extended Block mode the Exit Extended Block command must be issued.

The Extended Block can be protected, however once protected the protection cannot be undone.

Exit Extended Block Com m a n d

The Exit Extended Block command is used to exit from the Extended Block mod e and ret urn the de-

vice to Read mode. Four Bus Write operations are required to issue the command.

Block Protect and Chip Unprotect Commands Groups of blocks can be protected against acci-

dental Program or Erase. The Protection Groups are shown in Appendix A, T able 1 9 and T able 20, Block Addresses. The whole chip can be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprote ct operations are described in Appendix D.

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Table 4. Commands, 16-bit mode, BYTE = V

Bus Write Operations

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Dat a

1X F0

Read/Reset

3 555 AA 2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Double Word Program 3 555 50 PA0 PD0 PA1 PD1 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read CFI Query 1 55 98 Enter Extended Block 3 555 AA 2AA 55 555 88 Exit Extended Block 4 555 AA 2AA 55 555 90 X 00

Note: X Don’t Care, PA Prog ram Addre ss , P D Program Data, BA An y address in the Block. All values in the table are in hexadecimal .

The Com ma nd In terf ace o nly us es A –1, A0-A 10 a nd DQ 0-DQ 7 t o ver ify the com man ds; A 11-A 2 0, D Q8-DQ1 4 a nd DQ 15 ar e D on’t Care. DQ15A–1 is A– 1 when BYTE

is VIL or DQ15 when BYTE is VIH.

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Table 5. Commands, 8-bit mode, BYTE = V

Bus Write Operations

Command

1st 2nd 3rd 4th 5th 6th

Length

Add Data Add Data Add Data Add Data Add Data Add Data

1X F0

Read/Reset

3 AAA AA 555 55 X F0 Auto Select 3 AAA AA 555 55 AAA 90 Program 4 AAA AA 555 55 AAA A0 PA PD Quadruple Byte Program 5 AAA 55 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read CFI Query 1 AA 98 Enter Extended Block 3 AAA AA 555 55 AAA 88 Exit Extended Block 4 AAA AA 555 55 AAA 90 X 00

Note: X Don’t Care, PA Prog ram Addre ss , P D Program Data, BA An y address in the Block. All values in the table are in hexadecimal .

The Com ma nd In terf ace o nly us es A –1, A0-A 10 a nd DQ 0-DQ 7 t o ver ify the com man ds; A 11-A 2 0, D Q8-DQ1 4 a nd DQ 15 ar e D on’t Care. DQ15A–1 is A– 1 when BYTE

is VIL or DQ15 when BYTE is VIH.

Table 6. Program, Erase Times and Progra m , Erase Endurance Cycles

Parameter Min

Typ

(1, 2)

Chip Erase 80 Block Erase (64 KBytes) 0.8 Erase Suspend Latency Time

Program (Byte or Word) 10 Double Word Program (Byte or Word) 10 Chip Program (Byte by Byte) 80 Chip Program (Word by Word) 40 Chip Program (Quadruple Byte or Double Word) 20

Program/Erase Cycles (per Block) 100,000 cycles Data Retention 20 years

Note: 1. Typi cal values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value m easured at worst case conditions for both temperature and V

4. Maximum value m easured at worst case conditions for both temperature and V

after 100,0 0 program/erase cycle s.

Max

400

200 200 400 200 100

(4)

(3)

(2)

Unit

µs µs µs

s s

s s s

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STATUS REGISTER

Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed.

The bits in the Status Register are summarized in Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed o utput DQ7, not its complement.

During Er ase ope rations the Data Polling Bit ou t-

puts ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation.

Figure 5, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspen d. The Toggle Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’ 1’ to ’ 0’, et c., with su ccessive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation.

Figure 6, Dat a Toggle Flowchart, gives an example of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error B it is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Rese t command must be iss ued before other commands are issued. The E rror bit is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will s h ow the bit is s ti ll ‘0’. One o f t he E r as e commands must b e used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional block s to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.

Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will ou tput the memory cell data as if in Read mode.

After an Erase operation that c auses t he Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Re ad Operations from addresses within blocks that have not erased correctly. The Alternative Togg le Bit does not change if the addressed block has erased correctly.

18/50

Page 19

M29W640DT, M29W640DB

Table 7. Status Register Bits

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2

Program Any Address DQ7 Toggle 0 ––0 Program During Erase

Suspend

Any Address DQ7

Program Error Any Address DQ7

Toggle 0 – – 0

Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Block Erase before

timeout

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase

Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erasing Block 1 No Toggle 0 – Toggle 1

Erase Suspend

Non-Erasing Block Data read as normal 1

Good Block Address 0 Toggle 1 1 No Toggle 0

Erase Error

Faulty Block Address 0 Toggle 1 1 Toggle 0

Note: Unspecif ied data bit s should be ignored.

Figure 5. Dat a Po ll i ng Fl o wc h a rt Figure 6. Data Toggle Fl owchart

READ DQ6

DQ5 & DQ6

TOGGLE

READ DQ6

TOGGLE

START

READ

DQ6

DQ5

= 1

TWICE

DQ6

YES

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

YES

DATA

DQ5

= 1

YES

READ DQ7

at VALID ADDRESS

DQ7

YES

DATA

FAIL PASS

AI90194

FAIL PASS

AI90195B

19/50

Page 20

M29W640DT, M29W640DB

MAXIMUM RATIN G

Stressing the device ab ove the rating listed in t he Absolute Maximum Ratings table m ay cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the dev ice at

Table 8. Absolute Maximum Ratings

Symbol Parameter Min Max Un it

BIAS

STG

(3)

Note: 1. M in i m um voltage ma y undershoot to –2V during transitio n and for less t han 20ns during transitions.

2. Maximum volta ge m ay oversho ot to V

3. V

Temperature Under Bias –50 125 °C

Storage Temperature Input or Output Voltage

(1,2)

Supply Voltage –0.6 4 V Identification Voltage –0.6 13.5 V Program Voltage –0.6 13.5 V

+2V during transition and for less than 20ns during transitions.

must not rem ai n at 12V for more than a total of 80hrs.

these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and ot her relevant quality documents.

–65 150 °C

–0.6

+0.6

20/50

Page 21

M29W640DT, M29W640DB

DC AND AC PARAMETERS

This section summarizes the operat ing and measurement conditions, and the DC and AC characteristics of the device. The parameters in t he DC and AC Characteristic tables that follow are derived from tests performed under the Measure-

Table 9. Operating and AC Measurement Conditions

Parameter

Min Max Min Max

Supply Voltage

Ambient Operating Temperature –40 85 –40 85 °C

ment Conditions summarized in the relevant tables. Designers should chec k th at the o perat ing conditions in their circuit matc h the meas urement conditions when relying on the quoted parameters.

M29W640D

3.0 3.6 2.7 3.6 V

Unit70 90

Load Capacitance (C

)

30 30 pF Input Rise and Fall Times 10 10 ns Input Pulse Voltages Input and Output Timing Ref. Voltages

0 to V

/2 VCC/2

0 to V

Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit

VCC/2

AI05557

DEVICE

UNDER

TEST

0.1µF

CL includes JIG capacitance

V V

25kΩ

AI05558

Table 10. Device Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

= 0V

6pF

12 pF

OUT

Note: Sampled only, not 10 0% tested.

Input Capacitance Output Capacitance

21/50

Page 22

M29W640DT, M29W640DB

Table 11. DC Characteristics

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

CC3

V V

LKO

Note: 1. Sampled only, not 100% tested.

Input Leakage Current

Output Leakage Current

Supply Current (Read)

Supply Current (Standby)

Supply Current (Program/ Erase)

Input Low Voltage –0.5 0.8 V

Input High Voltage

Voltage for V Acceleration

Current for V

/WP Program

Acceleration Output Low Voltage

Output High Voltage

Identification Voltage 11.5 12.5 V

Program/Erase Lockout Supply

(1)

V oltage

0V ≤ V

= VIL, G = VIH,

f = 6MHz

= VCC ±0.2V,

= VCC ±0.2V

Program/Erase

Controller active

= 3.0V ±10%

= 1.8mA

= –100µA

OUT

≤ V

/WP = V

/WP = or V

±1 ±1

10 mA

100

20 mA

0.7V

VCC +0.3

11.5 12.5 V

15 mA

0.45 V

–0.4

1.8 2.3 V

µA µA

µA

22/50

Page 23

Figure 9. Read Mode AC Waveforms

A0-A20/ A–1

tAVQV tAXQX

DQ0-DQ7/ DQ8-DQ15

tBHQV

BYTE

tELBL/tELBH tBLQZ

M29W640DT, M29W640DB

tAVAV VALID

tELQV tEHQX

tELQX tEHQZ

tGLQX tGHQX

tGLQV

tGHQZ

VALID

AI05559

Table 12. Read AC Characteristics

Symbol Alt Parameter Test Condition

AVAV

AVQV

(1)

ELQX

ELQV

(1)

GLQX

GLQV

(1)

EHQZ

(1)

GHQZ

EHQX

GHQX

AXQX

ELBL

ELBH

BLQZ

BHQV

Note: 1. Sampled only, not 100% tested.

ACC

OLZ

ELFL

ELFH

FLQZ

FHQV

Address Valid to Next Address Valid

Address Valid to Output Valid

Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z

Chip Enable, Output Enable or Address Transition to Output Transition

Chip Enable to BYTE Low or High Max 5 5 ns

BYTE Low to Output Hi-Z Max 25 30 ns BYTE High to Output Valid Max 30 40 ns

= VIL,

= V

= VIL,

= V

M29W640D

Unit

70 90

Min 70 90 ns

Max 70 90 ns

Min 0 0 ns

Max 70 90 ns

Min 0 0 ns Max 30 35 ns Max 25 30 ns

Max 25 30 ns

Min 0 0 ns

23/50

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M29W640DT, M29W640DB

Figure 10. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20/ A–1

tAVWL

VALID

tWLAX

tWHEH

tELWL

tWLWHtGHWL

tDVWH

DQ0-DQ7/ DQ8-DQ15

tVCHEL

VALID

tWHRL

Table 13. Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter

AVAV

ELWL

WLWH

DVWH

WHDX

WHEH

WHWL

AVWL

WLAX

GHWL

WHGL

(1)

WHRL

VCHEL

Note: 1. Sampled only, not 100% tested.

WPH

OEH

BUSY

VCS

Address Valid to Next Address Valid Min 70 90 ns Chip Enable Low to Write Enable Low Min 0 0 ns Write Enable Low to Write Enable High Min 45 50 ns Input Valid to Write Enable High Min 45 50 ns Write Enable High to Input Transition Min 0 0 ns Write Enable High to Chip Enable High Min 0 0 ns Write Enable High to Write Enable Low Min 30 30 ns Address Valid to Write Enable Low Min 0 0 ns Write Enable Low to Address Transition Min 45 50 ns Output Enable High to Write Enable Low Min 0 0 ns Write Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 35 ns VCC High to Chip Enable Low

tWHGL

tWHWL

tWHDX

AI05560

M29W640D

Unit

70 90

Min 50 50 µs

24/50

Page 25

Figure 11. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20/ A–1

tAVEL

VALID

M29W640DT, M29W640DB

tELAX

tEHWH

tWLEL

tELEHtGHEL

tDVEH

DQ0-DQ7/ DQ8-DQ15

tVCHWL

VALID

tEHRL

Table 14. Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

AVAV

WLEL

ELEH

DVEH

EHDX

EHWH

EHEL

AVEL

ELAX

GHEL

EHGL

(1)

EHRL

VCHWL

Note: 1. Sampled only, not 100% tested.

CPH

OEH

BUSY

VCS

Address Valid to Next Address Valid Min 70 90 ns Write Enable Low to Chip Enable Low Min 0 0 ns Chip Enable Low to Chip Enable High Min 45 50 ns Input Valid to Chip Enable High Min 45 50 ns Chip Enable High to Input Transition Min 0 0 ns Chip Enable High to Write Enable High Min 0 0 ns Chip Enable High to Chip Enable Low Min 30 30 ns Address Valid to Chip Enable Low Min 0 0 ns Chip Enable Low to Address Transition Min 45 50 ns Output Enable High Chip Enable Low Min 0 0 ns Chip Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 35 ns VCC High to Write Enable Low

tEHGL

tEHEL

tEHDX

AI05561

M29W640D

Unit

70 90

Min 50 50 µs

25/50

Page 26

M29W640DT, M29W640DB

Figure 12. Reset/Block Temporary Unp rotec t AC Waveforms

E, G

tPHWL, tPHEL, tPHGL

Table 15. Reset/Block Temporary Unprotect AC Characteristics

Symbol Alt Parameter

(1)

PHWL

PHEL

(1)

PHGL

(1)

RHWL

(1)

RHEL

(1)

RHGL

PLPX

PLYH

(1)

PHPHH

(1)

VHVPP

Note: 1. Sampled only, not 100% tested.

READY

VIDR

tPLPX

tPLYH

RP High to Write Enable Low, Chip Enable Low, Output Enable Low

RB High to Write Enable Low, Chip Enable Low, Output Enable Low

RP Pulse Width Min 500 500 ns RP Low to Read Mode Max 50 50 µs

RP Rise Time to V

VPP Rise and Fall Time

tRHWL, tRHEL, tRHGL

tPHPHH

AI02931B

M29W640D

Unit

70 90

Min 50 50 ns

Min 0 0 ns

Min 500 500 ns Min 250 250 ns

Figure 13. Accelerated Program Timing Waveforms

VPP/WP

or V

26/50

tVHVPP

AI05563

Page 27

M29W640DT, M29W640DB

PACKAGE MECHANICAL

Figure 14. TSO P48 – 48 lead Plastic Thin Smal l Outline, 12 x 20mm, Package Outline

1 N

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

LA1 α

Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Me chan ica l Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472 A1 0.100 0.050 0.150 0.0039 0.0020 0.0059 A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D 19.800 20.200 0.7795 0.7953

millimeters inches

D1 18.300 18.500 0.7205 0.7283

e 0.500 – – 0.0 197 – –

E 11. 900 12. 100 0.4685 0.4764

L 0.500 0.700 0.0197 0.0276

alfa 0 5 0 5

N48 48

27/50

Page 28

M29W640DT, M29W640DB

Figure 15. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Packa ge Ou tline

Note: Drawing is not to scale.

BALL "A1"

BGA-Z33

ddd

Table 17. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Packag e Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472 A1 0.2 50 0.0098 A2 0.9 00 0.0354

b 0.350 0.450 0.0138 0.0177

millimeters inches

D 7.000 6.900 7.100 0.2756 0.2717 0.2795

D1 5.600 – – 0.2205 – –

ddd – – 0.1 00 – – 0.0039

E 11.000 10.900 11.100 0.4331 0.4291 0.4370 E1 8.800 – – 0.3465 – –

e 0.800 – – 0.0 315 – –

FD 0.700 – – 0.0276 – – FE 1.100 – – 0.0433 – – SD 0.4 00 – – 0.0157 – – SE 0.400 – – 0.0157 – –

28/50

Page 29

M29W640DT, M29W640DB

PART NUMBERING

Table 18. Ordering Information Scheme

Example: M29W 640DB 90 N 1 T

Device Type

M29

Operating Voltage

W = V

Device Function

640D = 64 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot B = Bottom Boot

Speed

70 = 70 ns 90 = 90 ns

= 2.7 to 3.6V

Package

N = TSOP48: 12 x 20 mm ZA = TFBGA63: 7x11mm, 0.80 mm pitch

Temperature Range

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing

Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office.

Devices are shipped from the factory with the memory content bits erased to 1. For a list of available options (Speed, Package, et c.) or for further i nformation on any as pect of t his device, p lease contact your nearest ST Sales Office.

29/50

Page 30

M29W640DT, M29W640DB

APPENDIX A. BLOCK ADDRESSES

Table 19. Top Boot Block Addresses, M29W640DT

Block KBytes/K Words

Protection Block

Group

(x8) (x16)

0 64/32

1 64/32 010000h–01FFFFh 008000h–00FFFFh

Protection Group

2 64/32 020000h–02FFFFh 010000h–017FFFh 3 64/32 030000h–03FFFFh 018000h–01FFFFh 4 64/32 5 64/32 050000h–05FFFFh 028000h–02FFFFh

Protection Group

6 64/32 060000h–06FFFFh 030000h–037FFFh 7 64/32 070000h–07FFFFh 038000h–03FFFFh 8 64/32 9 64/32 090000h–09FFFFh 048000h–04FFFFh

Protection Group

10 64/32 0A0000h–0AFFFFh 050000h–057FFFh 11 64/32 0B0000h–0BFFFFh 058000h–05FFFFh 12 64/32 13 64/32 0D0000h–0DFFFFh 068000h–06FFFFh

Protection Group

14 64/32 0E0000h–0EFFFFh 070000h–077FFFh 15 64/32 0F0000h–0FFFFFh 078000h–07FFFFh 16 64/32 17 64/32 110000h–11FFFFh 088000h–08FFFFh

Protection Group

18 64/32 120000h–12FFFFh 090000h–097FFFh

000000h–00FFFFh 000000h–007FFFh

040000h–04FFFFh 020000h–027FFFh

080000h–08FFFFh 040000h–047FFFh

0C0000h–0CFFFFh 060000h–067FFFh

100000h–10FFFFh 080000h–087FFFh

19 64/32 130000h–13FFFFh 098000h–09FFFFh 20 64/32 21 64/32 150000h–15FFFFh 0A8000h–0AFFFFh

Protection Group

22 64/32 160000h–16FFFFh 0B0000h–0B7FFFh 23 64/32 170000h–17FFFFh 0B8000h–0BFFFFh 24 64/32 25 64/32 190000h–19FFFFh 0C8000h–0CFFFFh

Protection Group

26 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh 27 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh 28 64/32

29 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh

Protection Group

30 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh 31 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh

30/50

140000h–14FFFFh 0A0000h–0A7FFFh

180000h–18FFFFh 0C0000h–0C7FFFh

1C0000h–1CFFFFh 0E0000h–0E7FFFh

Page 31

M29W640DT, M29W640DB

Block KBytes/KWords

32 64/32

33 64/32 210000h–21FFFFh 108000h–10FFFFh 34 64/32 220000h–22FFFFh 110000h–117FFFh 35 64/32 230000h–23FFFFh 118000h–11FFFFh 36 64/32 37 64/32 250000h–25FFFFh 128000h–12FFFFh 38 64/32 260000h–26FFFFh 130000h–137FFFh 39 64/32 270000h–27FFFFh 138000h–13FFFFh 40 64/32 41 64/32 290000h–29FFFFh 148000h–14FFFFh 42 64/32 2A0000h–2AFFFFh 150000h–157FFFh 43 64/32 2B0000h–2BFFFFh 158000h–15FFFFh 44 64/32 45 64/32 2D0000h–2DFFFFh 168000h–16FFFFh 46 64/32 2E0000h–2EFFFFh 170000h–177FFFh

47 64/32 2F0000h–2FFFFFh 178000h–17FFFFh 48 64/32

49 64/32 310000h–31FFFFh 188000h–18FFFFh 50 64/32 320000h–32FFFFh 190000h–197FFFh 51 64/32 330000h–33FFFFh 198000h–19FFFFh 52 64/32

Protection Block

Group

Protection Group

(x8) (x16)

200000h–20FFFFh 100000h–107FFFh

240000h–24FFFFh 120000h–127FFFh

280000h–28FFFFh 140000h–147FFFh

2C0000h–2CFFFFh 160000h–167FFFh

300000h–30FFFFh 180000h–187FFFh

340000h–34FFFFh 1A0000h–1A7FFFh 53 64/32 350000h–35FFFFh 1A8000h–1AFFFFh 54 64/32 360000h–36FFFFh 1B0000h–1B7FFFh 55 64/32 370000h–37FFFFh 1B8000h–1BFFFFh 56 64/32 57 64/32 390000h–39FFFFh 1C8000h–1CFFFFh 58 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh 59 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh 60 64/32 61 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh 62 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh 63 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh

Protection Group

380000h–38FFFFh 1C0000h–1C7FFFh

Protection Group

3C0000h–3CFFFFh 1E0000h–1E7FFFh

Protection Group

31/50

Page 32

M29W640DT, M29W640DB

Block KBytes/KWords

64 64/32

65 64/32 410000h–41FFFFh 208000h–20FFFFh 66 64/32 420000h–42FFFFh 210000h–217FFFh 67 64/32 430000h–43FFFFh 218000h–21FFFFh 68 64/32 69 64/32 450000h–45FFFFh 228000h–22FFFFh 70 64/32 460000h–46FFFFh 230000h–237FFFh 71 64/32 470000h–47FFFFh 238000h–23FFFFh 72 64/32 73 64/32 490000h–49FFFFh 248000h–24FFFFh 74 64/32 4A0000h–4AFFFFh 250000h–257FFFh 75 64/32 4B0000h–4BFFFFh 258000h–25FFFFh 76 64/32 77 64/32 4D0000h–4DFFFFh 268000h–26FFFFh 78 64/32 4E0000h–4EFFFFh 270000h–277FFFh 79 64/32 4F0000h–4FFFFFh 278000h–27FFFFh 80 64/32 81 64/32 510000h–51FFFFh 288000h–28FFFFh 82 64/32 520000h–52FFFFh 290000h–297FFFh 83 64/32 530000h–53FFFFh 298000h–29FFFFh 84 64/32

Protection Block

Group

Protection Group

(x8) (x16)

400000h–40FFFFh 200000h–207FFFh

440000h–44FFFFh 220000h–227FFFh

480000h–48FFFFh 240000h–247FFFh

4C0000h–4CFFFFh 260000h–267FFFh

500000h–50FFFFh 280000h–287FFFh

540000h–54FFFFh 2A0000h–2A7FFFh 85 64/32 550000h–55FFFFh 2A8000h–2AFFFFh 86 64/32 560000h–56FFFFh 2B0000h–2B7FFFh 87 64/32 570000h–57FFFFh 2B8000h–2BFFFFh 88 64/32 89 64/32 590000h–59FFFFh 2C8000h–2CFFFFh 90 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh 91 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh 92 64/32 93 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh 94 64/32 5E0000h–5EFFFFh 2F0000h–2F7FFFh 95 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh

32/50

Protection Group

580000h–58FFFFh 2C0000h–2C7FFFh

Protection Group

5C0000h–5CFFFFh 2E0000h–2E7FFFh

Protection Group

Page 33

M29W640DT, M29W640DB

Block KBytes/KWords

96 64/32

97 64/32 610000h–61FFFFh 308000h–30FFFFh 98 64/32 620000h–62FFFFh 310000h–317FFFh 99 64/32 630000h–63FFFFh 318000h–31FFFFh

100 64/32 101 64/32 650000h–65FFFFh 328000h–32FFFFh 102 64/32 660000h–66FFFFh 330000h–337FFFh 103 64/32 670000h–67FFFFh 338000h–33FFFFh 104 64/32 105 64/32 690000h–69FFFFh 348000h–34FFFFh 106 64/32 6A0000h–6AFFFFh 350000h–357FFFh 107 64/32 6B0000h–6BFFFFh 358000h–35FFFFh 108 64/32 109 64/32 6D0000h–6DFFFFh 368000h–36FFFFh 110 64/32 6E0000h–6EFFFFh 370000h–377FFFh

111 64/32 6F0000h–6FFFFFh 378000h–37FFFFh

112 64/32

113 64/32 710000h–71FFFFh 388000h–38FFFFh 114 64/32 720000h–72FFFFh 390000h–397FFFh 115 64/32 730000h–73FFFFh 398000h–39FFFFh 116 64/32

Protection Block

Group

Protection Group

(x8) (x16)

600000h–60FFFFh 300000h–307FFFh

640000h–64FFFFh 320000h–327FFFh

680000h–68FFFFh 340000h–347FFFh

6C0000h–6CFFFFh 360000h–367FFFh

700000h–70FFFFh 380000h–387FFFh

740000h–74FFFFh 3A0000h–3A7FFFh

117 64/32 750000h–75FFFFh 3A8000h–3AFFFFh 118 64/32 760000h–76FFFFh 3B0000h–3B7FFFh 119 64/32 770000h–77FFFFh 3B8000h–3BFFFFh 120 64/32 121 64/32 790000h–79FFFFh 3C8000h–3CFFFFh 122 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh 123 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh

Protection Group

780000h–78FFFFh 3C0000h–3C7FFFh

Protection Group

33/50

Page 34

M29W640DT, M29W640DB

Block KBytes/KWords

124 64/32

Protection Block

Group

(x8) (x16)

7C0000h–7CFFFFh 3E0000h–3E7FFFh 125 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh 126 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh

127 8/4 128 8/4 129 8/4

Protection Group

130 8/4 131 8/4 132 8/4 133 8/4 134 8/4

Note: 1. Used as the Extended Block Addresses in Ext ended Block m ode.

7F0000h–7F1FFFh 7F2000h–7F3FFFh 7F4000h–7F5FFFh 7F6000h–7F7FFFh 7F8000h–7F9FFFh 7FA000h–7FBFFFh

7FC000h–7FDFFFh

7FE000h–7FFFFFh

(1)

3F8000h–3F8FFFh 3F9000h–3F9FFFh 3FA000h–3FAFFFh

3FB000h–3FBFFFh 3FC000h–3FCFFFh 3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

Table 20. Bottom Boot Block Addresses, M29W640DB

Block KBytes/KWords

0 8/4 1 8/4 2 8/4 3 8/4 4 8/4 5 8/4 6 8/4 7 8/4

8 64/32 010000h-01FFFFh 008000h–00FFFFh 9 64/32 020000h-02FFFFh 010000h–017FFFh

Protection Block

Group

Protection Group

(x8) (x16)

000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

00E000h-00FFFFh

(1)

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

(1)

10 64/32 030000h-03FFFFh 018000h–01FFFFh 11 64/32

040000h-04FFFFh 020000h–027FFFh

12 64/32 050000h-05FFFFh 028000h–02FFFFh

Protection Group

13 64/32 060000h-06FFFFh 030000h–037FFFh 14 64/32 070000h-07FFFFh 038000h–03FFFFh

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Page 35

M29W640DT, M29W640DB

Block KBytes/KWords

15 64/32

16 64/32 090000h-09FFFFh 048000h–04FFFFh 17 64/32 0A0000h-0AFFFFh 050000h–057FFFh 18 64/32 0B0000h-0BFFFFh 058000h–05FFFFh 19 64/32 20 64/32 0D0000h-0DFFFFh 068000h–06FFFFh 21 64/32 0E0000h-0EFFFFh 070000h–077FFFh 22 64/32 0F0000h-0FFFFFh 078000h–07FFFFh 23 64/32 24 64/32 110000h-11FFFFh 088000h–08FFFFh 25 64/32 120000h-12FFFFh 090000h–097FFFh 26 64/32 130000h-13FFFFh 098000h–09FFFFh 27 64/32 28 64/32 150000h-15FFFFh 0A8000h–0AFFFFh 29 64/32 160000h-16FFFFh 0B0000h–0B7FFFh 30 64/32 170000h-17FFFFh 0B8000h–0BFFFFh 31 64/32 32 64/32 190000h-19FFFFh 0C8000h–0CFFFFh 33 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh 34 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh 35 64/32

Protection Block

Group

Protection Group

(x8) (x16)

080000h-08FFFFh 040000h–047FFFh

0C0000h-0CFFFFh 060000h–067FFFh

100000h-10FFFFh 080000h–087FFFh

140000h-14FFFFh 0A0000h–0A7FFFh

180000h-18FFFFh 0C0000h–0C7FFFh

1C0000h-1CFFFFh 0E0000h–0E7FFFh 36 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh 37 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh 38 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh 39 64/32 40 64/32 210000h-21FFFFh 108000h–10FFFFh 41 64/32 220000h-22FFFFh 110000h–117FFFh 42 64/32 230000h-23FFFFh 118000h–11FFFFh 43 64/32 44 64/32 250000h-25FFFFh 128000h–12FFFFh 45 64/32 260000h-26FFFFh 130000h–137FFFh 46 64/32 270000h-27FFFFh 138000h–13FFFFh

Protection Group

200000h-20FFFFh 100000h–107FFFh

Protection Group

240000h-24FFFFh 120000h–127FFFh

Protection Group

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Page 36

M29W640DT, M29W640DB

Block KBytes/KWords

47 64/32

48 64/32 290000h-29FFFFh 148000h–14FFFFh 49 64/32 2A0000h-2AFFFFh 150000h–157FFFh 50 64/32 2B0000h-2BFFFFh 158000h–15FFFFh 51 64/32 52 64/32 2D0000h-2DFFFFh 168000h–16FFFFh 53 64/32 2E0000h-2EFFFFh 170000h–177FFFh 54 64/32 2F0000h-2FFFFFh 178000h–17FFFFh 55 64/32 56 64/32 310000h-31FFFFh 188000h–18FFFFh 57 64/32 320000h-32FFFFh 190000h–197FFFh 58 64/32 330000h-33FFFFh 198000h–19FFFFh 59 64/32 60 64/32 350000h-35FFFFh 1A8000h–1AFFFFh 61 64/32 360000h-36FFFFh 1B0000h–1B7FFFh 62 64/32 370000h-37FFFFh 1B8000h–1BFFFFh 63 64/32 64 64/32 390000h-39FFFFh 1C8000h–1CFFFFh 65 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh 66 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh 67 64/32

Protection Block

Group

Protection Group

(x8) (x16)

280000h-28FFFFh 140000h–147FFFh

2C0000h-2CFFFFh 160000h–167FFFh

300000h-30FFFFh 180000h–187FFFh

340000h-34FFFFh 1A0000h–1A7FFFh

380000h-38FFFFh 1C0000h–1C7FFFh

3C0000h-3CFFFFh 1E0000h–1E7FFFh 68 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh 69 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh 70 64/32 3F0000h-3FFFFFh 1F8000h–1FFFFFh 71 64/32 72 64/32 410000h-41FFFFh 208000h–20FFFFh 73 64/32 420000h-42FFFFh 210000h–217FFFh 74 64/32 430000h-43FFFFh 218000h–21FFFFh 75 64/32 76 64/32 450000h-45FFFFh 228000h–22FFFFh 77 64/32 460000h-46FFFFh 230000h–237FFFh 78 64/32 470000h-47FFFFh 238000h–23FFFFh

36/50

Protection Group

400000h-40FFFFh 200000h–207FFFh

Protection Group

440000h-44FFFFh 220000h–227FFFh

Protection Group

Page 37

M29W640DT, M29W640DB

Block KBytes/KWords

79 64/32

80 64/32 490000h-49FFFFh 248000h–24FFFFh 81 64/32 4A0000h-4AFFFFh 250000h–257FFFh 82 64/32 4B0000h-4BFFFFh 258000h–25FFFFh 83 64/32 84 64/32 4D0000h-4DFFFFh 268000h–26FFFFh 85 64/32 4E0000h-4EFFFFh 270000h–277FFFh 86 64/32 4F0000h-4FFFFFh 278000h–27FFFFh 87 64/32 88 64/32 510000h-51FFFFh 288000h–28FFFFh 89 64/32 520000h-52FFFFh 290000h–297FFFh 90 64/32 530000h-53FFFFh 298000h–29FFFFh 91 64/32 92 64/32 550000h-55FFFFh 2A8000h–2AFFFFh 93 64/32 560000h-56FFFFh 2B0000h–2B7FFFh 94 64/32 570000h-57FFFFh 2B8000h–2BFFFFh 95 64/32 96 64/32 590000h-59FFFFh 2C8000h–2CFFFFh 97 64/32 5A0000h-5AFFFFh 2D0000h–2D7FFFh 98 64/32 5B0000h-5BFFFFh 2D8000h–2DFFFFh 99 64/32

Protection Block

Group

Protection Group

(x8) (x16)

480000h-48FFFFh 240000h–247FFFh

4C0000h-4CFFFFh 260000h–267FFFh

500000h-50FFFFh 280000h–287FFFh

540000h-54FFFFh 2A0000h–2A7FFFh

580000h-58FFFFh 2C0000h–2C7FFFh

5C0000h-5CFFFFh 2E0000h–2E7FFFh

100 64/32 5D0000h-5DFFFFh 2E8000h–2EFFFFh 101 64/32 5E0000h-5EFFFFh 2F0000h–2F7FFFh 102 64/32 5F0000h-5FFFFFh 2F8000h–2FFFFFh 103 64/32 104 64/32 610000h-61FFFFh 308000h–30FFFFh 105 64/32 620000h-62FFFFh 310000h–317FFFh 106 64/32 630000h-63FFFFh 318000h–31FFFFh 107 64/32 108 64/32 650000h-65FFFFh 328000h–32FFFFh 109 64/32 660000h-66FFFFh 330000h–337FFFh 110 64/32 670000h-67FFFFh 338000h–33FFFFh

Protection Group

600000h-60FFFFh 300000h–307FFFh

Protection Group

640000h-64FFFFh 320000h–327FFFh

Protection Group

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Page 38

M29W640DT, M29W640DB

Block KBytes/KWords

111 64/32

112 64/32 690000h-69FFFFh 348000h–34FFFFh 113 64/32 6A0000h-6AFFFFh 350000h–357FFFh 114 64/32 6B0000h-6BFFFFh 358000h–35FFFFh 115 64/32 116 64/32 6D0000h-6DFFFFh 368000h–36FFFFh 117 64/32 6E0000h-6EFFFFh 370000h–377FFFh 118 64/32 6F0000h-6FFFFFh 378000h–37FFFFh 119 64/32 120 64/32 710000h-71FFFFh 388000h–38FFFFh 121 64/32 720000h-72FFFFh 390000h–397FFFh 122 64/32 730000h-73FFFFh 398000h–39FFFFh 123 64/32 124 64/32 750000h-75FFFFh 3A8000h–3AFFFFh 125 64/32 760000h-76FFFFh 3B0000h–3B7FFFh 126 64/32 770000h-77FFFFh 3B8000h–3BFFFFh 127 64/32 128 64/32 790000h-79FFFFh 3C8000h–3CFFFFh 129 64/32 7A0000h-7AFFFFh 3D0000h–3D7FFFh 130 64/32 7B0000h-7BFFFFh 3D8000h–3DFFFFh 131 64/32

Protection Block

Group

Protection Group

(x8) (x16)

680000h-68FFFFh 340000h–347FFFh

6C0000h-6CFFFFh 360000h–367FFFh

700000h-70FFFFh 380000h–387FFFh

740000h-74FFFFh 3A0000h–3A7FFFh

780000h-78FFFFh 3C0000h–3C7FFFh

7C0000h-7CFFFFh 3E0000h–3E7FFFh

132 64/32 7D0000h-7DFFFFh 3E8000h–3EFFFFh 133 64/32 7E0000h-7EFFFFh 3F0000h–3F7FFFh 134 64/32 7F0000h-7FFFFFh 3F8000h–3FFFFFh

Note: 1. Used as the Extended Block Addresses in Ext ended Block m ode.

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Protection Group

Page 39

M29W640DT, M29W640DB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to det ermine various electrical and t iming parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary.

Table 21. Query Structure Overvi ew

Address

Sub-section Name Description

x16 x8

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Table 21 to Table 26 show the addresses used to retrieve the data.

The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 26, Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change t he secu rity number after it has been written by ST.

40h 80h

61h C2h Security Code Area 64 bit unique device number

Note: Query data are always presented on the lowest order data outputs.

Primary Algorithm-specific Extended Query table

Additional information specific to the Primary Algorithm (optional)

Table 22. CFI Query Identification String

Address

x16 x8

10h 20h 0051h “Q” 11h 22h 0052h Query Unique ASCII String "QRY" "R" 12h 24h 0059h "Y" 13h 26h 0002h 14h 28h 0000h 15h 2Ah 0040h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 0000h 19h 32h 0000h

1Ah 34h 0000h

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Data Description Value

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 25) P = 40h

Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table

AMD

Compatible

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Page 40

M29W640DT, M29W640DB

Table 23. CFI Query System Interface Information

Address

x16 x8

1Bh 36h 0 027h

1Ch 38h 0036h

1Dh 3Ah 00B5h

1Eh 3Ch 00C5h

1Fh 3Eh 0004h

20h 40h 0000h 21h 42h 000Ah 22h 44h 0000h 23h 46h 0004h 24h 48h 0000h 25h 4Ah 0003h 26h 4Ch 0000h

Data Description Value

Logic Supply Minimum Program/Erase voltage

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV

Logic Supply Maximum Program/Erase voltage

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

Typical timeout per single byte/word program = 2

Typical timeout for minimum size write buffer program = 2 Typical timeout per individual block erase = 2 Typical timeout for full chip erase = 2 Maximum timeout for byte/word program = 2 Maximum timeout for write buffer program = 2 Maximum timeout per individual block erase = 2 Maximum timeout for chip erase = 2

times typical

µs

times typical

µs

2.7V

3.6V

11.5V

12.5V

16µs

256 µs

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Page 41

Table 24. Device Geometry Definition

Address

x16 x8

27h 4Eh 0017h

Data Des cripti on Value

Device Size = 2

in number of bytes

M29W640DT, M29W640DB

8 MByte

28h 29h

2Ah 2Bh

2Ch 58h 0002h

2Dh

2Eh 2Fh

30h 31h

32h 33h

34h

Note: The region info rmat ion cont aine d in add re sses 2Dh to 34h ( or 5Ah to 68h) is co rre ct for t he M29 W6 40DB . Fo r the M29 W6 40D T the

regions must be revers ed.

50h 52h

54h 56h

5Ah 5Ch

5Eh

60h 62h

64h 66h

68h

0002h 0000h

0000h 0000h

0007h 0000h

0020h 0000h

007Eh 0000h

0000h 0001h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2 Number of Erase Block Regions. It specifies the number of

regions containing contiguous Erase Blocks of the same size. Region 1 Information

Number of identical size erase block = 0007h+1 Region 1 Information

Block size in Region 1 = 0020h * 256 byte Region 2 Information

Number of identical size erase block = 007Eh+1 Region 2 Information

Block size in Region 2 = 0100h * 256 byte

x8, x16

Async.

8Kbyte

127

64Kbyte

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M29W640DT, M29W640DB

Table 25. Primary Algorithm-Sp ecific Extend ed Qu ery Ta ble

Address

x16 x8

Data Description Value

40h 8 0h 0050h

41h 82h 0052h "R" 42h 84h 0049h "I" 43h 86h 0030h Major version number, ASCII "0" 44h 88h 0030h Minor version number, ASCII "0" 45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)

46h 8Ch 0002h Erase Suspend

47h 8Eh 0004h Block Protection

48h 90h 0001h Temporary Block Unprotect

49h 92h 0004h Block Protect /Unprotect

4Ah 94h 0000h Simultaneous Operations, 00 = not supported No 4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No 4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No 4Dh 9Ah 00B5h V

4Eh 9Ch 00C5h V

4Fh 9Eh 000xh Top/Bottom Boot Block Flag

Primary Algorithm extended Query table unique ASCII string “PRI”

00 = required, 01= not required Silicon Revision Number (bits 7 to 2)

00 = not supported, 01 = Read only, 02 = Read and Write

00 = not supported, x = number of blocks per protection group

00 = not supported, 01 = supported

04 = M29W400B

Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

02h = Bottom Boot device, 03h = Top Boot device

"P"

Yes

11.5V

12.5V

–

Table 26. Security Code Area

Address

x16 x8

61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX

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Data Description

64 bit: unique device number

Page 43

APPENDIX C. EXTENDED MEMORY BLOCK

The M29W640D has an extra block, the Extended Block, that can be accessed using a dedicated command.

This Extended Block is 32 KWords in x16 mode and 64 KBytes in x8 mode. It is used as a security block (to provide a permanent security identification number) or to store additional information.

The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit

DQ7. This bit is permane ntly set t o either ‘ 1’ or ‘ 0’ at the factory and cannot be changed. When set to ‘1’, it indicates that the device is factory locked and the Extended Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one.

Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific proced ure must be followed to read it. See “Extended Memory Block Verify Code

tions, BYTE = V V

, respectively, for details of how to read bit

” in Table s 2 a nd 3, Bus O pera-

and Bus Operat ions, BYTE =

DQ7. The Extended Block can only be accessed when

the device is in Extended Block mode. Fo r det ails of how the Extended Block mode is entered and exited, refer to the Enter Extended Block Command and Exit E xtended Block Command para-

graphs, and to Tables 4 and 5, “Commands, 16-bit mode, B YTE = V BYTE = V

”, respectively.

” and “Commands, 8-bit m ode,

M29W640DT, M29W640DB

Factory Locked Extended Block

In devices where the Extended Block is factory locked, the Security Identification Number is written to the Extended Block address space (see Table 27, Extended Block Address and Data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.

Customer Lockable Extended Block

A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to ‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the Extended Block but care must be taken because the protection of the Extended Block is not reversible.

There are two ways of protecting the Extended Block:

■ Issue the Enter Extended Block command t o

place the device in Extended Block mode, then use the In-System Technique (refer to Appendix D, In-System Technique and to the corresponding flowcharts, Figures 18 and 19, for a detailed explanation of the technique).

■ Issue the Enter Extended Block command to

place the device in Extended Block mode, then use the Programmer Technique (refer to Appendix D, Programmer Technique and to the corresponding flowcharts, Figures 16 and 17, for a detailed explanation of the technique).

Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode.

Table 27. Extended Block Address and Data

Device

7F0000h-7F000Fh 3F8000h-3F8007h

M29W640DT

7F0010h-7FFFFFh 3F8008h-3FFFFFh Unavailable

000000h-00000Fh 000000h-000007h

M29W640DB

000010h-00FFFFh 000008h-007FFFh Unavailable

Note: 1. See Tables 19 and 20, Top and Bottom Boot Block Addresses.

Address

x8 x16 Factory Locked Customer Lockable

(1)

Security Identification

Number

Security Identification

Number

Data

Determined by

Customer

Determined by

Customer

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M29W640DT, M29W640DB

APPENDIX D. BLOCK PROTECTION

Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A, Table 19 and Tab le 20 for details of the Protection Groups . Once protected, Program and Erase operations w ithin the protected group fail to change the data.

There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/B lock Temporary Unprotection pin, RP scriptions section.

Progra m me r Technique

The Programmer techniq ue uses high (V age levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended on ly for use in Programming Equipment.

To protect a group of blocks follow the flowchart in Figure 16, Program me r E quipm ent Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 17, Programmer Equipment Chip Unprotect Flowchart. Table 28, Programmer Technique Bus Ope rations, BYTE =

or VIL, gives a summary of each operation.

; this is described in the Signal De-

) volt-

The timing on these flowcharts is critical. Care should be taken to en sure that, where a pau se is specified, it is followed as closely as possible. Do not abort the procedure be fore reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.

In-System Technique

The In-System technique requires a high volt age level on the Reset/Blocks Temporary Unprotect pin, RP

. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system.

To protect a group of blocks follow the flowchart in Figure 18, In-System Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 19, In-System Equipment Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care should be taken to en sure that, where a pau se is specified, it is followed as closely as possible. Do not allow the microprocessor to s ervice interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.

Table 28. Programmer Tech niqu e Bus Op erati ons, BYTE

Operation E G W

Block (Group)

(1)

Protect

Chip Unprotect

Block (Group) Protection Verify

Block (Group) Unprotection Verify

Note: 1. Block Pr otection Gr oups are show n i n A ppendix A, Tables 19 and 20.

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VIDVIL Pulse

IDVIDVIL

Pulse

A9 = V

A0 = VIL, A1 = VIH, A6 = VIL, A9=VID,

A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

Address Inputs

A0-A21

, A12-A21 Block Address

Others = X

A9 = V

, A12 = VIH, A15 = VIH

Others = X

A12-A21 Block Address

Others = X

A12-A21 Block Address

Others = X

= VIH or V

Data Inputs/Outputs

DQ15A–1, DQ14 -DQ0

Pass = XX01h

Retry = XX00h

Retry = XX01h

Pass = XX00h

Page 45

Figure 16. Programmer Equipment Group Protect Flowchart

START

ADDRESS = GROUP ADDRESS

W = V

n = 0

G, A9 = VID,

E = V

Wait 4µs

W = V

Wait 100µs

W = V

M29W640DT, M29W640DB

Verify Protect Set-upEnd

E, G = VIH,

A0, A6 = VIL,

A1 = V

E = V

Wait 4µs

G = V

Wait 60ns

Read DATA

DATA

01h

YES

A9 = V

E, G = V

PASS

++n

= 25

A9 = V

E, G = V

YES

Note: Block Protection Groups are shown in Appendix D, Table 19 and Table 20.

FAIL

AI05574

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Page 46

M29W640DT, M29W640DB

Figure 17. Pro gramme r E quipme nt Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

CURRENT GROUP = 0

ADDRESS = CURRENT GROUP ADDRESS

n = 0

A6, A12, A15 = V

E, G, A9 = V

Wait 4µs

W = V

Wait 10ms

W = V

E, G = V

A0 = VIL, A1, A6 = V

E = V

Wait 4µs

(1)

G = V

Wait 60ns

Verify Unprotect Set-upEnd

++n

= 1000

YES

A9 = V

E, G = V

FAIL PASS

Note: Block Protection Groups are shown in Appendix D, Table 19 and Table 20.

Read DATA

DATA

00h

YESNO

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INCREMENT

CURRENT GROUP

LAST

GROUP

YES

A9 = V

E, G = V

AI05575

Page 47

Figure 18. I n-System Eq ui pm ent Group Prot ec t Fl owchart

START

n = 0

RP = V

M29W640DT, M29W640DB

Verify Protect Set-upEnd

ADDRESS = GROUP ADDRESS

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

Wait 100µs

WRITE 40h

A0 = VIL, A1 = VIH, A6 = V

Wait 4µs

READ DATA

A0 = VIL, A1 = VIH, A6 = V

DATA

RP = V

01h

YES

++n

= 25

ISSUE READ/RESET

COMMAND

PASS

Note: Block Protection Groups are shown in Appendix D, Table 19 and Table 20.

YES

RP = V

ISSUE READ/RESET

COMMAND

FAIL

AI05576

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Page 48

M29W640DT, M29W640DB

Figure 19. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

Verify Unprotect Set-upEnd

CURRENT GROUP = 0

A0 = VIL, A1 = VIH, A6 = V

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

n = 0

RP = V

WRITE 60h

ANY ADDRESS WITH

WRITE 60h

ANY ADDRESS WITH

Wait 10ms

WRITE 40h

Wait 4µs

READ DATA

INCREMENT

CURRENT GROUP

DATA

00h

++n

= 1000

YES

RP = V

ISSUE READ/RESET

COMMAND

FAIL

Note: Block Protection Groups are shown in Appendix D, Table 19 and Table 20.

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YESNO

LAST

GROUP

RP = V

ISSUE READ/RESET

COMMAND

PASS

YES

AI05577

Page 49

REVISION HIST ORY

Table 29. Document Revision History

Date Version Revision Details

14-Dec-2001 -01 Document released

Description of Ready/Busy signal clarified (and Figure 12 modified)

19-Apr-2002 -02

Clarified allowable commands during block erase Clarified the mode the device returns to in the CFI Read Query command section tPLYH (time to reset device) respecified. Correction to table of Commands.

M29W640DT, M29W640DB

24-Apr-2002 -03

05-Sep-2002 3.1

08-Jan-2003 3.2

04-Apr-2003 3.3

Values for addresses 23h and 25h corrected in CFI Query System Interface Information table in Appendix B

When in Extended Block mode, the block at the boot block address can be used as OTP. Value of electronic signature changed. Data Toggle Flow chart corrected. SO44 package removed. Double Word Program Time (typ) changed to 20s. Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 03 equals 3.0).

Values corrected for typical times for Double Word Program (Byte or Word) and Chip Program (Quadruple Byte, Double Word) in the Program, Erase Times and Program, Erase Endurance Cycles table. Document promoted from Product Preview to Preliminary Data.

Data Retention and Erase Suspend Latency Time parameters added to T able 6, Program, Erase Times and Program, Erase Endurance Cycles, and Typical after 100k W/E Cycles column removed.

(Identification) current removed from Table 11, DC Characteristics. Data modified at

addresses 2Eh, 31h, 32h in Table 24.

Extended Memory Block Verify Codes modified in T ables 2 and 3, “Bus Operations, BYTE

” and “Bus Operations, BYTE = VIH”, respectively. Block 75 address space corrected

= V

for x8 mode in Table 19, Top Boot Block Addresses, M29W640DT, and Block 71 address space corrected for x8 mode in Table 20, Bottom Boot Block Addresses, M29W640DB. Appendix C, EXTENDED MEMORY BLOCK, added. V

pin connection to ground

clarified. Lead-free package options E and F added to Table 18, Ordering Information Scheme.

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M29W640DT, M29W640DB

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Datasheet M29W640DT, M29W640DB Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES SUMMARY

Figure 1. Packages

TABLE OF CONTENTS

SUMMARY DESCRIPTION

Figure 2. Logic Diagram

Table 1. Signal Names

Figure 3. TSOP Connections

Figure 4. TFBGA Connections (Top view through package)

SIGNAL DESCRIPTIONS

Address Inputs (A0-A21). The Address Inputs select the cells i n the memory array to a ccess dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the Command Interface of the Program/Erase Con­troller.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when B Y TE V

Data Input/Output o r Address Input (DQ15A –1).

BUS OPERATIONS

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address Inputs, applying a Low sig nal, V and Output Enable and keeping Write Enable High, V

Output Disa bl e . The Data Inputs/Outputs are in the high impedance s tate when Output Enable is High, V

Standby. When Chip Enable is High, V memory enters Standby mode and the Data In­puts/Outputs pins are placed in the high-imped­ance state. To reduce the S upply Current to the Standby Supply Current, I

til the operation completes. Automatic Standby. If CMOS levels (V

Special Bus Operations

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying t he signals listed in Table 2 and Table 3, Bus Operations.

Block Protect and Chip Unprotect.

COMMAND INTERFACE

Read/Reset Command.

Auto Select Command.

Read CFI Query Command

Program Command.

Fast Program Commands

Quadruple Byte Program Command. The Qua-

Double Word Program Command. The Double Word Program command is used to write a p age of two adjacent words in parallel. Th e two words must differ only for the address A0.

Unlock Bypass Command.

Unlock Bypass Program Command.

Unlock Bypass Reset Command.

Chip Erase Command.

Block Erase Command.

Erase Suspend Command.

Erase Resume Command.

Enter Extended Block Command

Exit Extended Block Com m a n d

Table 6. Program, Erase Times and Progra m , Erase Endurance Cycles

STATUS REGISTER

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its opera­tion or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read.

Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has re­sponded to an Erase Suspen d. The Toggle Bit is output on DQ6 when the Status Register is read.

Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Al­ternative Toggle Bit is output on DQ2 when the Status Register is read.

Table 7. Status Register Bits

Figure 5. Dat a Po ll i ng Fl o wc h a rt Figure 6. Data Toggle Fl owchart

MAXIMUM RATIN G

Table 8. Absolute Maximum Ratings

DC AND AC PARAMETERS

Table 9. Operating and AC Measurement Conditions

Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit

Table 10. Device Capacitance

Table 11. DC Characteristics

Figure 9. Read Mode AC Waveforms

Table 12. Read AC Characteristics

Figure 10. Write AC Waveforms, Write Enable Controlled

Table 13. Write AC Characteristics, Write Enable Controlled

Figure 11. Write AC Waveforms, Chip Enable Controlled

Table 14. Write AC Characteristics, Chip Enable Controlled

Figure 12. Reset/Block Temporary Unp rotec t AC Waveforms

Table 15. Reset/Block Temporary Unprotect AC Characteristics

Figure 13. Accelerated Program Timing Waveforms

PACKAGE MECHANICAL

Figure 14. TSO P48 – 48 lead Plastic Thin Smal l Outline, 12 x 20mm, Package Outline

Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Me chan ica l Data

Figure 15. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Packa ge Ou tline

Table 17. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Packag e Mechanical Data

PART NUMBERING

Table 18. Ordering Information Scheme

APPENDIX A. BLOCK ADDRESSES

Table 19. Top Boot Block Addresses, M29W640DT

Table 20. Bottom Boot Block Addresses, M29W640DB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

Table 21. Query Structure Overvi ew

Table 22. CFI Query Identification String

Table 23. CFI Query System Interface Information

Table 24. Device Geometry Definition

Address Inputs (A0-A21). The Address Inputs select the cells i n the memory array to a ccess during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low sig nal, V and Output Enable and keeping Write Enable High, V

Standby. When Chip Enable is High, V memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the S upply Current to the Standby Supply Current, I

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read.

Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspen d. The Toggle Bit is output on DQ6 when the Status Register is read.

Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.