Datasheet M29W320DT, M29W320DB Datasheet (ST)

Download

Page 1

查询M29W320供应商

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V

■ ACCESS TIME: 70, 90ns

■ PROGRAMMING TIME

– 10µs per Byte/Word typical

■ 67 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location) – 2 Parameter and 64 Main Blocks

■ PROGRAM/ERA SE CONTROLLER

– Embedded Byte/Word Program algorithms

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Progra mming

■ V

PROTECT

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCL ES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h – Top Device Code M29W320DT: 22CAh – Bottom Device Code M29W320D B: 22CBh

2.7V to 3.6V for Program, Erase and

CC =

Read

=12V for Fast Program (optional)

Erase Suspend

/WP PIN for F AST PROGRAM and WRIT E

M29W320DT

M29W320DB

32 Mbit (4Mb x8 or 2Mb x16, Boot Block)

3V Supp l y Fl ash Memory

Figure 1. Packages

TSOP48 (N)

12 x 20mm

FBGA

TFBGA63 (ZA) TFBGA48 (ZE)

1/46August 2005

Page 2

M29W320DT, M29W320DB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 4. TFBGA63 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 5. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 6. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E Output Enable (G Write Enable (W V

Write Protect (V

PP/

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Ready/Busy Output (RB Byte/Word Organization Select (BYTE V

Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PP/

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. Bus Operations, BYTE Table 2. Bus Operations, BYTE

= VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

= VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2/46

Page 3

M29W320DT, M29W320DB

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Suspend Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Com m ands , 16-bit mode, BYTE Table 4. Com m ands , 8-bit mode, BYTE

Table 5. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10.Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

= VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

= VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 9. Dev ice Capacitanc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13.Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11.Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 14.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 12.Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 13. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 16.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14.Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8

Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Bottom View Package Out line . . 28

Table 15. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechani c al Data . . . . . 28

Figure 19.TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline. . . . . . . . . . .29

Table 16. TF BGA 63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . . 29

3/46

Page 4

M29W320DT, M29W320DB

Figure 20.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 30

Table 17. TF BGA 48 6x8m m - 6x8 Ball Array, 0.8mm Pitch, Package M echanical Data. . . . . . . . . 30

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 18.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 19.Top Boot Block Addresses, M29W320DT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 20.Bottom Boot Block Addresses, M29W320DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 21.Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 22.CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 23.CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 25. Prim ary Algorithm-Spec ific Extended Query Tabl e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 26.Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 27. Programmer Technique Bus Operations, BYTE

= VIH or V

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 21.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 22.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 23.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 24.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 28.Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4/46

Page 5

SUMMARY DESCRIPTION

The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory d efaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to pres erve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase c omm ands are wri tten to the Command Interface of t he memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase op eration can be de tected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory are as ymmetrically arranged, see Figure 6. and Figure 7., Table 19. and Table 20.The first or l ast 6 4 Kby tes h ave been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for p aramet er storag e and the remaining 32 K byte is a sm all Ma in Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple conne ction to most microprocessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm) TFBGA63 (7x11mm, 0.8mm pitch) and TFBGA48 (6x8mm, 0.8mm pitch) packages. The memory is supplied with all the bi t s erased (set to 1 ).

M29W320DT, M29W320DB

Figure 2. Logic Diagram

VPP/WP

A0-A20

BYTE

M29W320DT M29W320DB

Table 1. Signal Names

A0-A20 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E G

Chip Enable Output Enable

DQ0-DQ14

DQ15A–1

AI90189B

W RP RB BYTE V

VPP/WP

NC Not Connected Internally

Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select Supply Voltage VPP/Write Protect

Ground

5/46

Page 6

M29W320DT, M29W320DB

Figure 3. TSOP Connections

A15

48 A14 A13 A12 A11 A10 DQ14

A8 A19 A20

W RP NC

M29W320DT M29W320DB

37 36

VPP/WP

A18 A17

A7 A6 A5 A4 A3 A2 A1

24 25

AI90190

A16 BYTE V

DQ15A–1 DQ7

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

E A0

6/46

Page 7

Figure 4. TFBGA63 Connections (Top view through packa ge)

M29W320DT, M29W320DB

654321

(1)

A17

A18

A5 A20

DQ0

DQ8

DQ2

DQ10

A19

DQ5

DQ12

A10

A11

DQ7

DQ14

A13

A12

A14

A15

A16

BYTE

(1)

DQ9

DQ1

(1)

DQ11

DQ3

DQ4

Note: 1. Balls are shorted together via the substrate but not connected to the die.

DQ13

DQ6

DQ15

A–1

(1)

AI05525B

(1)

7/46

Page 8

M29W320DT, M29W320DB

Figure 5. TFBGA48 Connections (Top view through packa ge)

654321

A17

A5 A20

DQ0

DQ8

DQ9

DQ1

A18

DQ2

DQ10

DQ11

DQ3

A19

DQ5

DQ12

DQ4

A10

A11

DQ7

DQ14

DQ13

DQ6

A13

A12

A14

A15

A16

BYTE

DQ15

A–1

AI08084

8/46

Page 9

Figure 6. Block Addresses (x8)

M29W320DT, M29W320DB

M29W320DT

Top Boot Block Addresses (x8)

3FFFFFh

3FC000h 3FBFFFh

3FA000h 3F9FFFh

3F8000h

3F7FFFh

3F0000h

3EFFFFh

3E0000h

01FFFFh

010000h

00FFFFh

000000h

16 KByte

8 KByte

32 KByte

64 KByte

Total of 63

64 KByte Blocks

Bottom Boot Block Addresses (x8)

3FFFFFh

3F0000h

3EFFFFh

3E0000h

01FFFFh

010000h

00FFFFh

008000h

007FFFh

006000h

005FFFh

004000h

003FFFh

000000h

M29W320DB

64 KByte

32 KByte

8 KByte

16 KByte

Total of 63

64 KByte Blocks

Note: Also see APPEN DIX A., Table 19 . and Table 20. for a full listing of the Block Add res ses.

AI90192

9/46

Page 10

M29W320DT, M29W320DB

Figure 7. Block Addresses (x16)

Top Boot Block Addresses (x16)

1FFFFFh

1FE000h

1FDFFFh

1FD000h

1FCFFFh

1FC000h

1FBFFFh

1F8000h

1F7FFFh

1F0000h

00FFFFh

008000h

007FFFh

000000h

M29W320DT

8 KWord

4 KWord

16 KWord

32 KWord

Total of 63

32 KWord Blocks

Bottom Boot Block Addresses (x16)

1FFFFFh

1F8000h

1F7FFFh

1F0000h

00FFFFh

008000h

007FFFh

004000h

003FFFh

003000h

002FFFh

002000h

001FFFh

000000h

M29W320DB

32 KWord

16 KWord

4 KWord

8 KWord

Total of 63

32 KWord Blocks

Note: Also see Appendix APPENDIX A., Table 19. and Table 20. for a full listing of the Block Addresses.

AI90193

10/46

Page 11

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A20). The Address Inputs select the cell s in the memory arra y to access du ring Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal sta te machine.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when B YTE

. When BYTE is Low, VIL, these pins are not

is High,

used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

Data Input/Output o r Address Input (DQ15A –1).

When BYTE

is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

is Low, VIL, this pin behaves as an address

BYTE pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when

is High and ref erences to the Address In-

BYTE puts to include this pin when BYTE

is Low except

when stated explicitly otherwise.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V

Output Enable (G

, all other pins are ignored.

). The Output E nable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a ce .

Write Protect (VPP/WP). The VPP/Write

PP/

Protect

pin provides two functions. The VPP function allo ws the memory to us e an external hi gh volt age power s u pply to r educe th e time req ui red for Unlock Bypass Program operations. The Writ e Pro tec t fu nct io n prov i des a ha rd wa re me thod of protecting the 16 Kbyte Boot Block. The

/Write Protect pin must not be left floating or

unconnected. When V

/Write Protect is Low, VIL, the memo ry

protects the 16 Kbyte Boot Block; Program and Erase operations in this block are ignored while

/Write Protect is Low.

M29W320DT, M29W320DB

When V reverts to the previous protection status of the 16 Kbyte boot block. Program and Erase operations can now modify the data in the 16 Kbyte Boot Block unless the block is protected using Block Protection.

When V ory automatically enters the Unlock Bypass mode. When V mal operation resumes. During Unlock Bypass Program operations the mem ory draws I the pin to supply the programming circuits. See the description of the Unlock Bypass c ommand in the Command Interface section. The transitions from

to VPP and from VPP to VIH must be slower

than t Never raise V

mode except Read m ode, otherwise the memory may be left in an indeterminate state.

A 0.1µF ca pacitor should be connected between the V to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, I

Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have b een protected.

Note that if V outermost boot block will remain protect even if RP is at V

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V t

PLPX

goes High, V Read and Bus Write operations after t t

RHEL

Output section, Table 1 4. and Figure 16., Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from V t

PHPHH

Ready/Busy Output (RB

is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, V pedance during Read mode, Auto Select mode and Erase Suspend mode.

/Write Protect is High, VIH, the memory

/Write Protect is raised to V

/Write Protect returns to VIH or VIL nor-

, see Figure 17..

VHVPP

/Write Protect to VPP from any

/Write Protect pin and the VSS Ground pin

/WP is at VIL, then the 16 KByte

the mem-

from

, for at least

. After Reset/Block Temporary Unprotect

, the memory will be ready for Bus

PHEL

, whichever occurs last. See the Ready/Busy

at VID will temporarily unprotect the

to VID must be slower than

). The Ready/Busy pin

. Ready/Busy is high-im-

11/46

Page 12

M29W320DT, M29W320DB

Note that if VPP/WP is at VIL, then the 16 KByte outermost boot block will remain protect even if RP is at V

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 14. and Figure Figure 16., Reset/Temporary Unprotect AC Characteristics.

The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE

). The

Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, V High, V

, the memory is in x8 mode, when it is

, the memory is in x16 mode.

Supply Voltage (2.7V to 3.6V). VCC pro-

vides the power supply for all operations (Read, Program and Erase).

The Command Interface is disabled when the V

Supply Voltage is less than the L ockout Voltage,

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF ca pacitor should be connected between the V

Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, I

Ground. VSS is the reference for all voltage

CC3

measurements.

12/46

Page 13

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Write, Ou tput Disable, Standby and Automatic Standby. See Figure 8. and Table 2., Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low sig nal, V

, to Chip Enable

and Output Enable and keeping Write Enable High, V

. The Data Inputs/Outputs will output the

value, see Figure 13., Read Mode AC Waveforms, and Table 11., Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desire d address on t he Address Inputs. The Address Inputs are latc hed by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs a re latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V

, during the whole Bus

Write operation. See Figure 14. and Figure 15., Write AC Waveforms, and Table 12. and Table

13., Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . T he Data Inputs/Outputs are in the high impedance s tate when Output Enable is High, V

Standby. When Chip Enable is High, V

, the

memory enters Standby mode and the Data In-

M29W320DT, M29W320DB

puts/Outputs pins are placed in the high-impedance state. To reduce t he Supply Current to the Standby Supply Current, I be held within V

± 0.2V. For the Standby current

level see Table 10., DC Characteristics. During program or erase operations the memory

will continue to use the Program/Erase Supply Current, I

, for Program or Erase operations un-

CC3

til the operation completes. Automatic Standby. If CMOS levels (V

are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, I Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require V

to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying t he signals listed in Figure 8. and Table 2., Bus Operations.

Block Protect and Chip Unprotect.

can be separately protected against accidental Program or Erase. T he whole chip can be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprote ct operations are described in APPENDIX C..

, Chip Enable should

CC2

Each block

± 0.2V)

. The

Figure 8. Bus Operations, BYTE

Operation E G W

Bus Read Bus Write Output Disable X Standby Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

V V

X X X Hi-Z Hi-Z

= V

Address Inputs

DQ15A–1, A0-A20

Cell Address Hi-Z Data Output

Command Address Hi-Z Data Input

X Hi-Z Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or V A0 = VIH, A1 = VIL,

A9 = VID, Others VIL or V

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Hi-Z 20h

Hi-Z

CAh (M29W320DT) CBh (M29W320DB)

13/46

Page 14

M29W320DT, M29W320DB

Table 2. Bus Operations, BYTE = V

Operation E G W

Bus Read Bus Write Output Disable X Standby Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

V V

XXX Hi-Z

Address Inputs

A0-A20

Cell Address Data Output

Command Address Data Input

XHi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others V A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or V

or V

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

0020h

22CAh (M29W320DT) 22CBh (M29W320DB)

14/46

Page 15

COMMAND INTERFACE

All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 3., or Table 4., depending on the configuration that is being used, for a summary of the commands.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in th e Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend.

Auto Select Command. The Auto Select command is used to read the Manufacturer C ode, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select comma nd is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/ Reset commands are accepted in Auto Select mode, all other commands are ignored.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V may be set to either V

and A1 = VIL. The other address bits

or VIH. The Manufa cturer

Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read

operation with A0 = V address bits may be set to e ither V

and A1 = VIL. The other

or VIH. The

Device Code for the M29W320DT is 22CAh and for the M29W320DB is 22CBh.

The B lock Prot ection S tatus of each block c an be read using a Bus Read operation with A0 = V A1 = V

, and A 12 - A20 specify i ng the address of

the bl ock. T he oth er addr ess bit s may b e set t o either V

or VIH. If the ad dress ed bloc k is pro tecte d

then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.

Read CFI Query Command. The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This

M29W320DT, M29W320DB

command is valid when the device is in the Read Array mode, or when the device is i n Autoselected mode.

One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read ope rations read from the Common Flash Interface Memory Area.

The Read/Reset command m ust be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode.

See APPENDIX B., Table 21., Table 22., Table

23., Table 24., Table 25. and T able 26. for details on the information contained in the Common Flash Interface (CFI) memory area.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a pro tected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operat ion the memo ry will ignore all commands. I t is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 5.. Bus Read operations during the program o peration will output the Status Register on the Data Inputs/Outputs. See the section on the S tatus Register for more details.

After the program operation has completed the memory will retu rn to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ’0’ bac k to ’1’. One of the E rase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass

command is used in conjunction with the Unlock Bypass Program command to program the memory. When the cycle time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are requ ired to issue the Unlock Bypass command.

15/46

Page 16

M29W320DT, M29W320DB

Once the Unlock Bypas s command has bee n issued the memory will only accept the Unl ock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

The memory offers accelerated program operations through the V system asserts V

/Write Protect pin. When the

on the VPP/Write Protect pin,

the m emory automa tically enters the Unlock Bypass mode. The system may then write the twocycle Unlock Bypass program command sequence. The memory uses the higher voltage on the V

/Write Protect pin, to accelerate the Unlock

Bypass Program operation. Never raise V

/Write Protect to VPP from any

mode except Read m ode, otherwise the memory may be left in an indeterminate state.

Unlock Bypass Program Command. The Unlock Bypass Prog ram comma nd can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be abort ed, the Status Regi ster is read and protected blocks cannot be programmed. Errors must be reset using the Read/ Reset command, which l eaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.

Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to ret urn to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode.

Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protect e d th e Chip Erase op erat i on appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the erase operation the memory will ignore all commands, including the Erase Suspen d command. It is not possible to i ssue any c ommand t o abort the operation. Typical chip erase times are given in Table 5.. All Bus Read operations du ring the Chip Erase operation will output the Status

After the Chip Erase operation has com pleted the memory will retu rn to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.

Block Erase Command. The Block Erase command can be u sed to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register section for details on how t o identify if the Program/ Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are pro tected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the Block Erase operation the me mory wi ll ignore all commands except the Erase Susp end command. Typical b lock e rase tim es are given in Table 5.. All Bus Read operations during the Block Erase ope ration will out pu t the S t a tus Re gister on the Data Inputs/Outputs. See the sec tion on the Status Register for more details.

After the Block Erase operation has completed the memory will retu rn to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.

Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation.

16/46

Page 17

M29W320DT, M29W320DB

The Program/Erase Controller will sus pend within the Erase Suspend Latency Time (refer to Table 5. for value) of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immedi ately and wi ll start immediately when the Erase Resume Comm and is issued. It is not possible to select any further blocks to erase after the Era se Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condi tion is given. Read-

ing from blocks that are being erased will output the Status Register.

It is also possible t o issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted.

Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller after an Erase Suspend. The device must be in Read Array mode before t he Resume command will be accepted. An erase can be suspended and resumed more than once.

Block Protect and Chip Unprotect Commands.

Each block can be separately protected against accidental Program or E rase. The whol e c hip can be unprotected to allow the data inside the blo cks to be changed.

Block Protect and Chip Unprote ct operations are described in APPENDIX C..

17/46

Page 18

M29W320DT, M29W320DB

Table 3. Commands, 16-bit mode, BYTE = V

Bus Write Operations

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1X F0

Read/Reset

3555 AA2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read CFI Query 1 55 98

Note: X Don’t Care, PA P rogram Addre ss, PD Program Data, BA Any address in the Blo ck . All values in th e table are in hexadecimal.

The Comm and In terf ace o nly uses A– 1, A 0-A1 0 a nd DQ0-D Q7 to v er ify t he co mman ds ; A1 1-A2 0, D Q8- DQ14 a nd DQ 15 ar e D on’t Care. DQ15A–1 is A–1 when BYTE Read/Reset. After a Rea d/Re se t comman d, read th e memor y a s normal until anot her com m and is iss ued . Read /Res et co mmand is ignored during algori t hm execution.

Auto Select. Afte r an Auto Select command, read Manuf ac tu rer ID , Dev ice ID or Block Prote ction Status. Program , Un lock By pass P rogr am, Chip Eras e, Bl ock Er ase. After these commands read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations unt i l T i m eout Bit is set.

Unlock B ypa ss. Af t er the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypas s Reset commands. Unlock B ypa ss Reset. After the Unlock By pass Reset com m and read the memory as normal un til another com m and is issued. Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-

mands on no n-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Era se operatio n resumes, read the Status Registe r until the Program/ Erase Controller completes an d the memor y returns t o Re ad Mode. CFI Query. Comm and is valid when device is ready to read array dat a or when device i s i n autoselecte d m ode.

is VIL or DQ15 when BYTE is VIH.

18/46

Page 19

M29W320DT, M29W320DB

Table 4. Commands, 8-bit mode, BYTE = V

Bus Write Operations

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1X F0 Read/Reset

3 AAA AA 555 55 X F0 Auto Select 3 AAA AA 555 55 AAA 90 Program 4 AAA AA 555 55 AAA A0 PA PD Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read CFI Query 1 AA 98

Note: X Don’t Care, PA P rogram Addre ss, PD Program Data, BA Any address in the Blo ck . All values in th e table are in hexadecimal.

The Comm and In terf ace o nly uses A– 1, A 0-A1 0 a nd DQ0-D Q7 to v er ify t he co mman ds ; A1 1-A2 0, D Q8- DQ14 a nd DQ 15 ar e D on’t Care. DQ15A–1 is A–1 when BYTE

Read/Reset. After a Rea d/Re se t comman d, read th e memor y a s normal until anot her com m and is iss ued . Read /Res et co mmand is ignored during algori t hm execution.

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations unt i l T i m eout Bit is set.

mands on no n-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Era se operatio n resumes, read the Status Registe r until the Pro-

gram/ Erase Controller completes an d the memor y returns t o Re ad Mode. CFI Query. Comm and is valid when device is ready to read array dat a or when device i s i n autoselecte d m ode.

is VIL or DQ15 when BYTE is VIH.

19/46

Page 20

M29W320DT, M29W320DB

Table 5. Program, Erase Times and Progra m , Erase Endu ran ce Cycle s

Parameter Min

Chip Erase 40 Block Erase (64 KBytes) 0.8 Erase Suspend Latency Time 15 Program (Byte or Word) 10 Accelerated Program (Byte or Word) 8 Chip Program (Byte by Byte) 40 Chip Program (Word by Word) 20

Program/Erase Cycles (per Block) 100,000 cycles Data Retention 20 years

Note: 1. Typical values measured at room temperature and nominal volt ages.

2. Sample d, but not 100% tested.

3. Maximum value measured at wors t case conditions for both temperature and V

4. Maximum value measured at wors t case conditions for both temperature and V

CC CC

(1, 2)

Typ

after 100,0 0 program/era s e cycles. .

Max

200

25 200 150 200 100

(4)

(3)

(2)

Unit

µs µs µs

s s

STATUS REGISTER

Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed.

The bits in the Status Register are summari zed in Table 6., Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is out put on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed o utput DQ7, not its complement.

During Er ase ope ratio ns the D ata Pollin g Bit ou tputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation.

Figure Figure 9., Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid

Address is the address being program med or an address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspen d. The Toggle Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’ 1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation.

If any attempt is made to erase a protected bl ock, the operation is abort ed, no error is sig nalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a protected block or a suspended block, the operation is abort ed, no error is signalled and DQ6 toggles for approximately 1µs.

Figure Figure 10., Dat a Toggle Flowchart , gives an example of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit i s set to ’1’ when a P rogram, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Rese t comm and must be issued

20/46

Page 21

M29W320DT, M29W320DB

before other commands are issued. The Error bit is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will s h ow the bit is s ti ll ‘0’. One o f th e Erase commands must b e used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.

Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will ou tput the memory cell data as if in Read mode.

After an Erase operation that c auses the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive B us Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle B it does not change if the addressed block has erased correctly.

Status Register is read.

Table 6. Status Register Bits

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle0––0 Program During Erase

Suspend Program Error Any Address DQ7

Any Address DQ7

Toggle0––0

Toggle1––0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Block Erase before

timeout

Block Erase

Erase Suspend

Erase Error

Note: Unspecified data bits shou ld be i gnored.

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

21/46

Page 22

M29W320DT, M29W320DB

Figure 9. Dat a Po ll i ng Fl o w chart Figure 10. Dat a Toggle Flowc hart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

DQ5

READ DQ7

at VALID ADDRESS

DQ7

DATA

FAIL PASS

= 1

YES

AI90194

START

READ DQ6

READ

DQ5 & DQ6

DQ6

TOGGLE

YES

DQ5

= 1

YES

READ DQ6

TWICE

DQ6

TOGGLE

YES

FAIL PASS

AI01370C

22/46

Page 23

M29W320DT, M29W320DB

MAXIMUM RATING

Stressing the device above the rating listed in the Absolute Maximum Ratings table may c ause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at

Table 7. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

BIAS

STG

Note: 1. Minim um voltage may un dershoot to –2V during transi tion and for les s t han 20ns during transitions.

2. Maximum volta ge m ay overshoot to V

Temperature Under Bias –50 125 °C Storage Temperature –65 150 °C

Input or Output Voltage

(1,2)

Supply Voltage –0.6 4 V Identification Voltage –0.6 13.5 V Program Voltage –0.6 13.5 V

+2V during tra nsition and fo r l ess than 20ns duri ng transitions.

these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevan t quality documents.

–0.6

+0.6

23/46

Page 24

M29W320DT, M29W320DB

DC AND AC PARAMETERS

This section summarizes t he operating m easurement conditions, and the DC and AC characteristics of the device. The parameters in the D C and AC characteristics Tables that follow, are derived from tests performed under the Measurement

Table 8. Operating and AC Measurement Conditions

Conditions summarized in Table 8., Operating and AC Measurement Conditions. Designers should check that the operating cond itions in their circuit match the operating conditions when relying on the quoted parameters.

M29W320D

Parameter

Min Max Min Max

Supply Voltage

3.0 3.6 2.7 3.6 V Ambient Operating Temperature –40 85 –40 85 °C Load Capacitance (C

)

30 30 pF Input Rise and Fall Times 10 10 ns Input Pulse Voltages Input and Output Timing Ref. Voltages

0 to V

VCC/2 VCC/2

0 to V

Figure 11. AC Measurement I/ O Wav eform Figure 12. AC Measurement Lo a d Circuit

VCC/2

AI90196

DEVICE UNDER

TEST

Unit70 90

V V

25kΩ

0.1µF

CL includes JIG capacitance

Table 9. Device Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

Note: Sampled only, not 100% tested.

Input Capacitance Output Capacitance

24/46

OUT

= 0V

6pF

12 pF

25kΩ

AI90197

Page 25

M29W320DT, M29W320DB

Table 10. DC Characteristics

Symbol Parameter Test Condition Min Typ. Max Unit

Input Leakage Current

CC1

CC2

CC3

V V

Note: 1. Sampled only, not 100% tested.

Output Leakage Curren t

Supply Current (Read)

Supply Current (Standby)

Supply Current (Program /

(1)

Erase)

Input Low Voltage –0.5 0.8 V

Input High Voltage

Voltage for V

Program Acceleration Current for V

Program Acceleration Output Low Voltage

Output High Voltage IOH = –100µA

Identification Voltage 11.5 12.5 V

Identification Current

Program/Erase Lockout

LKO

Supply Voltage

/WP

0V ≤ V

= VIL, G = VIH,

f = 6MHz

= VCC ±0.2V,

RP = VCC ±0.2V

Program/

Erase

Controller

active

= 3.0V ±10%

= 1.8mA

A9 = V

OUT

≤ V

VILor V

/WP =

±1 ±1

510mA

35 100

20 mA

0.7V

VCC +0.3

11.5 12.5 V

10 mA

0.45 V

–0.4

100

1.8 2.3 V

µA µA

µA

25/46

Page 26

M29W320DT, M29W320DB

Figure 13. Read Mode AC Waveforms

A0-A20/ A–1

tAVQV tAXQX

tAVAV VALID

tELQV

tELQX tEHQZ

tGLQX tGHQX

tGLQV

DQ0-DQ7/ DQ8-DQ15

tBHQV

BYTE

tELBL/tELBH tBLQZ

Table 11. Read AC Characteristics

Symbol Alt Parameter Test Condition

AVAV

AVQV

(1)

ELQX

ELQV

(1)

GLQX

GLQV

(1)

EHQZ

(1)

GHQZ

EHQX

GHQX

AXQX

ELBL

ELBH

BLQZ

BHQV

Note: 1. Sampled only, not 100% tested.

ACC

OLZ

ELFL

ELFH

FLQZ

FHQV

Address Valid to Next Address Valid

Address Valid to Output Valid

Chip Enable Low to Output Transition Chip Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Output Valid Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Chip Enable, Output Enable or Address Transition to Output Transition

Chip Enable to BYTE Low or High Max 5 5 ns

BYTE Low to Output Hi-Z Max 25 30 ns BYTE High to Output Valid Max 30 40 ns

= VIL,

= V

= VIL,

G = V G

= V

tEHQX

tGHQZ

VALID

AI90198

M29W320D

Unit

70 90

Min 70 90 ns

Max 70 90 ns

Min 0 0 ns

Max 70 90 ns

Min 0 0 ns

Max 30 35 ns Max 25 30 ns

Max 25 30 ns

Min 0 0 ns

26/46

Page 27

Figure 14. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20/ A–1

tAVWL

VALID

M29W320DT, M29W320DB

tWLAX

tWHEH

tELWL

tWLWHtGHWL

tDVWH

DQ0-DQ7/ DQ8-DQ15

tVCHEL

VALID

tWHRL

Table 12. Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter

AVAV

ELWL

WLWH

DVWH

WHDX

WHEH

WHWL

AVWL

WLAX

GHWL

WHGL

(1)

WHRL

VCHEL

Note: 1. Sampled only, not 100% tested.

WPH

OEH

BUSY

VCS

Address Valid to Next Address Valid Min 70 90 ns Chip Enable Low to Write Enable Low Min 0 0 ns Write Enable Low to Write Enable High Min 45 50 ns Input Valid to Write Enable High Min 45 50 ns Write Enable High to Input Transition Min 0 0 ns Write Enable High to Chip Enable High Min 0 0 ns Write Enable High to Write Enable Low Min 30 30 ns Address Valid to Write Enable Low Min 0 0 ns Write Enable Low to Address Transition Min 45 50 ns Output Enable High to Write Enable Low Min 0 0 ns Write Enable High to Output Enable Low Min 0 0 ns Program/Erase Valid to RB Low Max 30 35 ns VCC High to Chip Enable Low

tWHGL

tWHWL

tWHDX

AI90199

M29W320D

Unit

70 90

Min 50 50 µs

27/46

Page 28

M29W320DT, M29W320DB

Figure 15. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20/ A–1

tAVEL

VALID

tELAX

tEHWH

tWLEL

tELEHtGHEL

tDVEH

DQ0-DQ7/ DQ8-DQ15

tVCHWL

VALID

tEHRL

Table 13. Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

AVAV

WLEL

ELEH

DVEH

EHDX

EHWH

EHEL

AVEL

ELAX

GHEL

EHGL

(1)

EHRL

VCHWL

Note: 1. Sampled only, not 100% tested.

CPH

OEH

BUSY

VCS

Address Valid to Next Address Valid Min 70 90 ns Write Enable Low to Chip Enable Low Min 0 0 ns Chip Enable Low to Chip Enable High Min 45 50 ns Input Valid to Chip Enable High Min 45 50 ns Chip Enable High to Input Transition Min 0 0 ns Chip Enable High to Write Enable High Min 0 0 ns Chip Enable High to Chip Enable Low Min 30 30 ns Address Valid to Chip Enable Low Min 0 0 ns Chip Enable Low to Address Transition Min 45 50 ns Output Enable High Chip Enable Low Min 0 0 ns Chip Enable High to Output Enable Low Min 0 0 ns Program/Erase Valid to RB Low Max 30 35 ns VCC High to Write Enable Low

tEHGL

tEHEL

tEHDX

AI90200

M29W320D

Unit

70 90

Min 50 50 µs

28/46

Page 29

Figure 16. Reset/Block Temporary Unprotect AC Waveforms

E, G

tPHWL, tPHEL, tPHGL

tPLPX

tPLYH

Table 14. Reset/Block Temporary Unprotect AC Characteristics

Symbol Alt Parameter

(1)

PHWL

PHEL

(1)

PHGL

(1)

RHWL

(1)

RHEL

(1)

RHGL

PLPX

(1)

PLYH

(1)

PHPHH

(1)

VHVPP

Note: 1. Sampled only, not 100% tested.

READY

VIDR

RP High to Write Enable Low, Chip Enable Low,

Output Enable Low

RB High to Write Enable Low, Chip Enable Low,

Output Enable Low

RP Pulse Width Min 500 500 ns

RP Low to Read Mode Max 10 10 µs RP Rise Time to V

VPP Rise and Fall Time

M29W320DT, M29W320DB

tRHWL, tRHEL, tRHGL

tPHPHH

AI02931B

M29W320D

Unit

70 90

Min 50 50 ns

Min 0 0 ns

Min 500 500 ns Min 250 250 ns

Figure 17. Accelerated Program Timing Wavefo rms

VPP/WP

or V

tVHVPP

AI90202

29/46

Page 30

M29W320DT, M29W320DB

PACKAGE MECHANICAL

Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Bottom View Packag e Outline

DIE

LA1 α

Note: Drawing not to scale.

Table 15. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm , Packag e Mechani cal D ata

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

millimeters inches

TSOP-G

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083 CP 0.080 0.0031 D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – – L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

α 305305

30/46

Page 31

M29W320DT, M29W320DB

Figure 19. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitc h, Package Ou tline

Note: Drawing is not to scale.

BALL "A1"

BGA-Z33

ddd

Table 16. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mech anical Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472 A1 0.250 0.0098 A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 7.000 6.900 7.100 0.2756 0.2717 0.2795

millimeters inches

D1 5.600 – – 0.2205 – –

ddd – – 0.100 – – 0.0039

E 11.000 10.900 11.100 0.4331 0.4291 0.4370 E1 8.800 – – 0.3465 – –

e 0.800 – – 0.0315 – –

FD 0.700 – – 0.0276 – – FE 1.100 – – 0.0433 – – SD 0.400 – – 0.0157 – – SE 0.400 – – 0.0157 – –

31/46

Page 32

M29W320DT, M29W320DB

Figure 20. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline

BALL "A1"

E1E

BGA-Z32

Note: Drawing not to scale.

Table 17. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mech anical Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472 A1 0.260 0.0102

millimeters inches

ddd

A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 8.000 7.900 8.100 0.3150 0.3110 0.3189 E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

FD 1.000 – – 0.0394 – – FE 1.200 – – 0.0472 – – SD 0.400 – – 0.0157 – – SE 0.400 – – 0.0157 – –

32/46

Page 33

M29W320DT, M29W320DB

PART NUMBERING

Table 18. Ordering Information Scheme

Example: M29W320DB 90 N 1 T

Device Type

M29

Operating Voltage

W = V

Device Function

320D = 32 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot B = Bottom Boot

Speed

70 = 70 ns 90 = 90 ns

= 2.7 to 3.6V

Package

N = TSOP48: 12 x 20 mm ZA = TFBGA63: 7x11mm, 0.80 mm pitch ZE = TFBGA48: 6 x 8mm, 0.8mm pitch

Temperature Rang e

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

Blank = Standard Packing T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Pac kage, et c...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.

33/46

Page 34

M29W320DT, M29W320DB

APPENDIX A. BLOCK ADDRESS TABLE

Table 19. Top Boot Block Addresses, M29W320DT

Size

(KByte/ KWord)

66 16/8 3FC000h-3FFFFFh 1FE000h-1FFFFFh 65 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh 64 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh 63 32/16 3F0000h-3F7FFFh 1F8000h-1FBFFFh 62 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh 61 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh 60 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh 59 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh 58 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh 57 64/32 390000h-39FFFFh 1C8000h-1CFFFFh 56 64/32 380000h-18FFFFh 1C0000h-1C7FFFh 55 64/32 370000h-37FFFFh 1B8000h-1BFFFFh 54 64/32 360000h-36FFFFh 1B0000h-1B7FFFh 53 64/32 350000h-35FFFFh 1A8000h-1AFFFFh 52 64/32 340000h-34FFFFh 1A0000h-1A7FFFh 51 64/32 330000h-33FFFFh 198000h-19FFFFh 50 64/32 320000h-32FFFFh 190000h-197FFFh 49 64/32 310000h-31FFFFh 188000h-18FFFFh 48 64/32 300000h-30FFFFh 180000h-187FFFh 47 64/32 2F0000h-2FFFFFh 178000h-17FFFFh 46 64/32 2E0000h-2EFFFFh 170000h-177FFFh 45 64/32 2D0000h-2DFFFFh 168000h-16FFFFh 44 64/32 2C0000h-2CFFFFh 160000h-167FFFh 43 64/32 2B0000h-2BFFFFh 158000h-15FFFFh 42 64/32 2A0000h-2AFFFFh 150000h-157FFFh 41 64/32 290000h-29FFFFh 148000h-14FFFFh 40 64/32 280000h-28FFFFh 140000h-147FFFh 39 64/32 270000h-27FFFFh 138000h-13FFFFh 38 64/32 260000h-26FFFFh 130000h-137FFFh 37 64/32 250000h-25FFFFh 128000h-12FFFFh 36 64/32 240000h-24FFFFh 120000h-127FFFh 35 64/32 230000h-23FFFFh 118000h-11FFFFh

Address Ran ge

(x8)

Address R ange

(x16)

34 64/32 220000h-22FFFFh 110000h-117FFFh 33 64/32 210000h-21FFFFh 108000h-10FFFFh 32 64/32 200000h-20FFFFh 100000h-107FFFh 31 64/32 1F0000h-1FFFFFh 0F8000h-0FBFFFh 30 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh 29 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh 28 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh 27 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh 26 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh 25 64/32 190000h-19FFFFh 0C8000h-0CFFFFh 24 64/32 180000h-18FFFFh 0C0000h-0C7FFFh 23 64/32 170000h-17FFFFh 0B8000h-0BFFFFh 22 64/32 160000h-16FFFFh 0B0000h-0B7FFFh 21 64/32 150000h-15FFFFh 0A8000h-0AFFFFh 20 64/32 140000h-14FFFFh 0A0000h-0A7FFFh 19 64/32 130000h-13FFFFh 098000h-09FFFFh 18 64/32 120000h-12FFFFh 090000h-097FFFh 17 64/32 110000h-11FFFFh 088000h-08FFFFh 16 64/32 100000h-10FFFFh 080000h-087FFFh 15 64/32 0F0000h-0FFFFFh 078000h-07FFFFh 14 64/32 0E0000h-0EFFFFh 070000h-077FFFh 13 64/32 0D0000h-0DFFFFh 068000h-06FFFFh 12 64/32 0C0000h-0CFFFFh 060000h-067FFFh 11 64/32 0B0000h-0BFFFFh 058000h-05FFFFh 10 64/32 0A0000h-0AFFFFh 050000h-057FFFh

9 64/32 090000h-09FFFFh 048000h-04FFFFh 8 64/32 080000h-08FFFFh 040000h-047FFFh 7 64/32 070000h-07FFFFh 038000h-03FFFFh 6 64/32 060000h-06FFFFh 030000h-037FFFh 5 64/32 050000h-05FFFFh 028000h-02FFFFh 4 64/32 040000h-04FFFFh 020000h-027FFFh 3 64/32 030000h-03FFFFh 018000h-01FFFFh 2 64/32 020000h-02FFFFh 010000h-017FFFh 1 64/32 010000h-01FFFFh 008000h-00FFFFh 0 64/32 000000h-00FFFFh 000000h-007FFFh

34/46

Page 35

M29W320DT, M29W320DB

Table 20. Bottom Boot Block Addresses, M29W320DB

Size

(KByte/ KWord)

66 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh 65 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh 64 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh 63 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh 62 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh 61 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh 60 64/32 390000h-39FFFFh 1C8000h-1CFFFFh 59 64/32 380000h-18FFFFh 1C0000h-1C7FFFh 58 64/32 370000h-37FFFFh 1B8000h-1BFFFFh 57 64/32 360000h-36FFFFh 1B0000h-1B7FFFh 56 64/32 350000h-35FFFFh 1A8000h-1AFFFFh 55 64/32 340000h-34FFFFh 1A0000h-1A7FFFh 54 64/32 330000h-33FFFFh 198000h-19FFFFh 53 64/32 320000h-32FFFFh 190000h-197FFFh 52 64/32 310000h-31FFFFh 188000h-18FFFFh 51 64/32 300000h-30FFFFh 180000h-187FFFh 50 64/32 2F0000h-2FFFFFh 178000h-17FFFFh 49 64/32 2E0000h-2EFFFFh 170000h-177FFFh 48 64/32 2D0000h-2DFFFFh 168000h-16FFFFh 47 64/32 2C0000h-2CFFFFh 160000h-167FFFh 46 64/32 2B0000h-2BFFFFh 158000h-15FFFFh 45 64/32 2A0000h-2AFFFFh 150000h-157FFFh 44 64/32 290000h-29FFFFh 148000h-14FFFFh 43 64/32 280000h-28FFFFh 140000h-147FFFh 42 64/32 270000h-27FFFFh 138000h-13FFFFh 41 64/32 260000h-26FFFFh 130000h-137FFFh 40 64/32 250000h-25FFFFh 128000h-12FFFFh 39 64/32 240000h-24FFFFh 120000h-127FFFh 38 64/32 230000h-23FFFFh 118000h-11FFFFh 37 64/32 220000h-22FFFFh 110000h-117FFFh 36 64/32 210000h-21FFFFh 108000h-10FFFFh 35 64/32 200000h-20FFFFh 100000h-107FFFh

Address Ran ge

(x8)

Address R ange

(x16)

34 64/32 1F0000h-1FFFFFh 0F8000h-0FBFFFh 33 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh 32 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh 31 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh 30 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh 29 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh 28 64/32 190000h-19FFFFh 0C8000h-0CFFFFh 27 64/32 180000h-18FFFFh 0C0000h-0C7FFFh 26 64/32 170000h-17FFFFh 0B8000h-0BFFFFh 25 64/32 160000h-16FFFFh 0B0000h-0B7FFFh 24 64/32 150000h-15FFFFh 0A8000h-0AFFFFh 23 64/32 140000h-14FFFFh 0A0000h-0A7FFFh 22 64/32 130000h-13FFFFh 098000h-09FFFFh 21 64/32 120000h-12FFFFh 090000h-097FFFh 20 64/32 110000h-11FFFFh 088000h-08FFFFh 19 64/32 100000h-10FFFFh 080000h-087FFFh 18 64/32 0F0000h-0FFFFFh 078000h-07FFFFh 17 64/32 0E0000h-0EFFFFh 070000h-077FFFh 16 64/32 0D0000h-0DFFFFh 068000h-06FFFFh 15 64/32 0C0000h-0CFFFFh 060000h-067FFFh 14 64/32 0B0000h-0BFFFFh 058000h-05FFFFh 13 64/32 0A0000h-0AFFFFh 050000h-057FFFh 12 64/32 090000h-09FFFFh 048000h-04FFFFh 11 64/32 080000h-08FFFFh 040000h-047FFFh 10 64/32 070000h-07FFFFh 038000h-03FFFFh

9 64/32 060000h-06FFFFh 030000h-037FFFh 8 64/32 050000h-05FFFFh 028000h-02FFFFh 7 64/32 040000h-04FFFFh 020000h-027FFFh 6 64/32 030000h-03FFFFh 018000h-01FFFFh 5 64/32 020000h-02FFFFh 010000h-017FFFh 4 64/32 010000h-01FFFFh 008000h-00FFFFh 3 32/16 008000h-00FFFFh 004000h-007FFFh 2 8/4 006000h-007FFFh 003000h-003FFFh 1 8/4 004000h-005FFFh 002000h-002FFFh 0 16/8 000000h-003FFFh 000000h-001FFFh

35/46

Page 36

M29W320DT, M29W320DB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to det ermine various electrical and timing p arameters, density information and functions su pported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary.

When the CFI Query Command is issued the device enters CFI Query mode and the data structure

Table 21. Query Structure Overview

Address

x16 x8

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

40h 80h

61h C2h Security Code Area 64 bit unique device number

Note: Query dat a ar e al ways pr esente d on t h e l owest or der data ou t pu t s.

Primary Algorithm-specific Extended Query table

Sub-section Name Description

is read from the memory. Table 21., Table 22., Table 23., Table 24., Table 25. and Tab le 26. show the addresses used to retrieve the data.

The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 26., Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security num ber after it has been written by ST. Issue a Read command to return to Read mode.

Additional information specific to the Primary Algorithm (optional)

Table 22. CFI Query Identification String

Address

x16 x8

10h 20h 0051h “Q” 11h 22h 0052h Query Unique ASCII String "QRY" "R" 12h 24h 0059h "Y" 13h 26h 0002h 14h 28h 0000h 15h 2Ah 0040h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 0000h 19h 32h 0000h

1Ah 34h 0000h

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Data Description Value

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 24.) P = 40h

Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table

AMD

Compatible

36/46

Page 37

Table 23. CFI Query System Interface Information

Address

x16 x8

1Bh 36h 0027h

1Ch 38h 0036h

1Dh 3Ah 00B5h

1Eh 3Ch 00C5h

1Fh 3Eh 0004h 20h 40h 0000h 21h 42h 000Ah 22h 44h 0000h 23h 46h 0005h 24h 48h 0000h 25h 4Ah 0004h 26h 4Ch 0000h

Data Description Value

Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV

Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV Typical timeout per single byte/word program = 2 Typical timeout for minimum size write buffer program = 2 Typical timeout per individual block erase = 2 Typical timeout for full chip erase = 2 Maximum timeout for byte/word program = 2 Maximum timeout for write buffer program = 2 Maximum timeout per individual block erase = 2 Maximum timeout for chip erase = 2

M29W320DT, M29W320DB

times typical

µs

times typical

µs

2.7V

3.6V

11.5V

12.5V

16µs

512µs

16s

Table 24. Device Geometry Definition

Address

x16 x8

27h 4Eh 0016h 28h

29h 2Ah

2Bh

50h 52h

54h 56h

2Ch 58h 0004h

2Dh 2Eh

2Fh 30h

31h 32h

33h 34h

5Ah

5Ch 5Eh

60h 62h

64h 66h

68h

Data Description Value

Device Size = 2

0002h 0000h

0000h 0000h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2 Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous Erase Blocks of the same size.

0000h 0000h

0040h 0000h

0001h 0000h

0020h 0000h

Region 1 Information Number of identical size erase block = 0000h+1

Region 1 Information Block size in Region 1 = 0040h * 256 byte

Region 2 Information Number of identical size erase block = 0001h+1

Region 2 Information Block size in Region 2 = 0020h * 256 byte

in number of bytes

4 MByte

x8, x16

Async.

16 Kbyte

8 Kbyte

37/46

Page 38

M29W320DT, M29W320DB

Address

x16 x8

35h 36h

37h 38h

39h 3Ah

3Bh 3Ch

6Ah 6Ch

6Eh

70h 72h

74h 76h

78h

Data Description Value

0000h 0000h

0080h 0000h

003Eh 0000h

0000h 0001h

Region 3 Information Number of identical size erase block = 0000h+1

Region 3 Information Block size in Region 3 = 0080h * 256 byte

Region 4 Information Number of identical-size erase block = 003Eh+1

Region 4 Information Block size in Region 4 = 0100h * 256 byte

Table 25. Primary Algorithm-Specific Extended Qu ery Ta ble

Address

x16 x8

40h 80h 0050h 41h 82h 0052h "R" 42h 84h 0049h "I" 43h 86h 00 31h M ajor versio n number, ASCII "1" 44h 88h 00 30h M inor versio n number, ASCII "0" 45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)

46h 8Ch 0002h Erase Suspend

47h 8Eh 0001h Block Protection

48h 90h 0001h Temporary Block Unprotect

49h 92h 0004h Block Protect /Unprotect

4Ah 94h 0000h Simultaneous Operations, 00 = not supported No

Data Description Value

Primary Algorithm extended Query table unique ASCII string “PRI”

00 = required, 01= not required Silicon Revision Number (bits 7 to 2)

00 = not supported, 01 = Read only, 02 = Read and Write

00 = not supported, x = number of blocks in per group

00 = not supported, 01 = supported

04 = M29W400B

32 Kbyte

64 Kbyte

"P"

Yes

4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No 4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No 4Dh 9Ah 00B5h V

4Eh 9Ch 00C5h V

4Fh 9Eh 000xh Top/Bo ttom Boot Block Flag

38/46

Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

02h = Bottom Boot device, 03h = Top Boot device

11.5V

12.5V

–

Page 39

Table 26. Security Code Area

Address

x16 x8

61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX

M29W320DT, M29W320DB

Data Description

64 bit: unique device number

39/46

Page 40

M29W320DT, M29W320DB

APPENDIX C. BLOCK PROTECTION

Block protection can be used to prevent any operation from modifying the data s tored in the Flash. Each Block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data.

There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP scriptions section.

Unlike the Command Interface of the Program/ Erase Controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example , the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when changing drivers for one part to work on another.

Programm er Te chnique

The Programmer techniq ue uses high (V age levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended on ly for use in Programming Equipment.

To protect a block follow the flowch art in Figure Figure 21., Programmer Equipment Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. To unprotect the chip follow Figure Figure 22., Programmer Equipment Chip Unprotect Flowchart. Table 27. ,

; this is described in the Signal De-

) volt-

Programmer Technique B us Operations, gives a summary of each operation.

The timing on these flowcharts is critical. Care should be taken t o ensure t hat, where a pause is specified, it is followed as closely as possible. Do not abort the procedure be fore reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.

In-System Technique

The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP

. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the Flash has been fitted to the system.

To protect a block follow the flowch art in Figure Figure 23., In-System Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks f ir st, th en all th e blocks can be un protected at the same time. To unprotect the chip follow Figure Figure 24., In-System Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care should be taken t o ensure t hat, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to serv ice interrupts that will upset the timing and do not abort the procedure before reaching t he end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.

Table 27. Programmer Technique Bus Op erati ons, BYTE

Operation E G W

Block Protect

Chip Unprotect

Block Protection Verify

Block Unprotection Verify

40/46

IDVIDVIL

VIDVIL Pulse

Pulse

A9 = V

A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,

A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

Address Inputs

A0-A20

, A12-A20 Block Address

Others = X

A9 = V

, A12 = VIH, A15 = VIH

Others = X

A12-A20 Block Address

Others = X

A12-A20 Block Address

Others = X

= VIH or V

Data Inputs/Outputs

DQ15A–1, DQ14 -DQ0

Pass = XX01h

Retry = XX00h

Retry = XX01h

Pass = XX00h

Page 41

Figure 21. Programmer Equ ip m e nt B l ock P rot ect Flowchart

START

ADDRESS = BLOCK ADDRESS

W = V

n = 0

G, A9 = VID,

E = V

Wait 4µs

W = V

Wait 100µs

M29W320DT, M29W320DB

Verify Protect Set-upEnd

W = V

E, G = VIH,

A0, A6 = VIL,

A1 = V

E = V

Wait 4µs

G = V

Wait 60ns

Read DATA

DATA

01h

YES

A9 = V

E, G = V

PASS

++n

= 25

A9 = V

E, G = V

YES

FAIL

AI03469

41/46

Page 42

M29W320DT, M29W320DB

Figure 22. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

n = 0

CURRENT BLOCK = 0

Verify Unprotect Set-upEnd

A6, A12, A15 = V

E, G, A9 = V

Wait 4µs

W = V

Wait 10ms

W = V

E, G = V

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = V

E = V

Wait 4µs

G = V

Wait 60ns

Read DATA

(1)

INCREMENT

CURRENT BLOCK

42/46

00h

YESNO

DATA

++n

= 1000

YES

A9 = V

E, G = V

FAIL PASS

LAST

BLOCK

A9 = V

E, G = V

YES

AI03470

Page 43

Figure 23. In-System Equipment Block Protect Flowchart

START

n = 0

RP = V

M29W320DT, M29W320DB

Verify Protect Set-upEnd

ADDRESS = BLOCK ADDRESS

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

Wait 100µs

WRITE 40h

A0 = VIL, A1 = VIH, A6 = V

Wait 4µs

READ DATA

A0 = VIL, A1 = VIH, A6 = V

DATA

RP = V

01h

YES

++n

= 25

ISSUE READ/RESET

COMMAND

PASS

YES

RP = V

ISSUE READ/RESET

COMMAND

FAIL

AI03471

43/46

Page 44

M29W320DT, M29W320DB

Figure 24. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

n = 0

CURRENT BLOCK = 0

RP = V

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

Verify Unprotect Set-upEnd

ADDRESS = CURRENT BLOCK ADDRESS

++n

= 1000

YES

RP = V

ISSUE READ/RESET

COMMAND

Wait 10ms

WRITE 40h

A0 = VIL, A1 = VIH, A6 = V

Wait 4µs

READ DATA

A0 = VIL, A1 = VIH, A6 = V

DATA

00h

YESNO

ISSUE READ/RESET

CURRENT BLOCK

LAST

BLOCK

YES

RP = V

COMMAND

INCREMENT

44/46

FAIL

PASS

AI03472

Page 45

REVISION HIST ORY

Table 28. Document Revision History

Date Version Revision Details

March-2001 -01 First Issue (Brief Data)

08-Jun-2001 -02 Document expanded to full Product Preview

22-Jun-2001 -03

27-Jul-2001 -04

05-Oct-2001 -05

07-Feb-2002 -06 TFBGA package changed from 48 ball to 63 ball

Minor text corrections to Read/Reset and Read CFI commands and Status Register Error and Toggle Bits.

Document type: from Product Preview to Preliminary Data TFBGA connections and Block Addresses (x16) diagrams clarification Write Protect and Block Unprotect clarification CFI Primary Algorithm table, Block Protection change

Added Block Protection Appendix “Write Protect/V

” pin renamed to “VPP/Write Protect” to be consistent with abbreviation.

Changes to the VPP/WP pin description, Figure Figure 17. and Table 14.. IPP added to Table 10. and I Command section. Added V

clarified. Modified description of VPP/WP operation in Unlock Bypass

CC3

/WP decoupling capacitor to Figure Figure 12..

Clarified Read/Reset operation during Erase Suspend.

M29W320DT, M29W320DB

05-Apr-2002 -07

Clarified allowable commands during block erase Clarified the mode the device returns to in the CFI Read Query command section

Erase Suspend Latency Time (typical and maximum) added to Program, Erase Times and Program, Erase Endurance Cycles table. Typical values added for Icc1 and Icc2 in DC characteristics table.

Description of Ready/Busy signal clarified (and Figure 16 modified)

19-Nov-2002 7.1

Logic Diagram and Data Toggle Flowchart corrected. Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 07 equals 7.0). Document promoted to full datasheet.

Data Retention added to Table 5., Program, Erase Times and Program, Erase Endurance

26-May-2003 7.2

Cycles, and Typical after 100k W/E Cycles column removed. TSOP48 package mechanical updated. Lead-free package options E and F added to Table 18., Ordering Information Scheme.

16-Aug-2005 8.0 TFBGA48 package added throughout document.

45/46

Page 46

M29W320DT, M29W320DB

Information furnished i s believed t o be accurate and reliab le. However, STMicr oelectronics assumes no respons ibili ty for the consequence s of use of such information nor f or any infri ngement of patents or other r ights of third parties which may result f rom its use. No l icense is granted by implicati on or otherwis e under any patent or pat en t ri ghts of STMic roelec tronic s. Specifi cat ions m entio ned i n thi s publ icat ion ar e s ubj ect to change without notice. This publication supersedes and r eplace s all i nfor mati on pr eviousl y suppli ed. STMi croel ectr onics p roduc ts are not authori zed f or use a s criti cal components in li fe s uppor t

Australia - Belgium - Brazil - Canada - China - Czech Repub lic - Finland - France - Germany - Hong Kong - India - Isra el - Italy - Japan - Malaysia - Malta

- Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

www.st.com

46/46

Datasheet M29W320DT, M29W320DB Datasheet (ST)

Specifications and Main Features

Frequently Asked Questions

User Manual