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PRELIMINARY DATA
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M29W200BT
M29W200BB
2 Mbit (256Kb x8 or 128Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory
■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 55ns
■ PROGRAMMING TIME
–10µs per Byte/Word typical
■ 7 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 4 Main Blocks
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ LOW POWERCONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLESper
BLOCK
■ 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W200BT: 0051h
– Bottom Device Code: M29W200BB 0057h
44
1
TSOP48 (N)
12 x 20mm
SO44 (M)
Figure 1. Logic Diagram
AI02948
17
A0-A16
W
DQ0-DQ14
V
CC
M29W200BT
M29W200BB
E
V
SS
15
G
RP
DQ15A–1
BYTE
RB
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M29W200BT, M29W200BB
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Figure 2. TSOP Connections
DQ3
DQ9
DQ2
A6
DQ0
W
A3
RB
DQ6
A8
A9
DQ13
NC
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
V
CC
DQ4
DQ5
A7
DQ7
NC
NC
AI02944
M29W200BT
M29W200BB
12
1
13
24 25
36
37
48
DQ8
NC
NC
A1
NC
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14
V
SS
E
A0
RP
V
SS
Figure 3. SO Connections
G
DQ0
DQ8
A3
A0
E
V
SS
A2
A1
A13
V
SS
A14
A15
DQ7
A12
A16
BYTE
DQ15A–1
DQ5DQ2
DQ3
V
CC
DQ11
DQ4
DQ14
A9
WRB
A4
NC RP
A7
AI02945
M29W200BT
M29W200BB
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
2322
20
19
18
17DQ1
DQ9
A6
A5
DQ6
DQ13
44
39
38
37
36
35
34
33
A11
A10
DQ10
21
DQ12
40
43
1
42
41
NC A8
Table 1. Signal Names
A0-A16 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
V
CC
Supply Voltage
V
SS
Ground
NC Not Connected Internally
SUMMARY DESCRIPTION
The M29W200B is a 2 Mbit (256Kb x8 or 128Kb
x16) non-volatile memorythat canbe read,erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read inthe same way
as a ROM or EPROM. The M29W200B is fully
backward compatible with the M29W200.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while olddata is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands arewritten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasingthe memoryby
taking care of all of the specialoperations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
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M29W200BT, M29W200BB
The blocks in the memory are asymmetrically arranged, seeTables 3 and 4,Block Addresses.The
first or last 64 Kbytes have been divided into four
additional blocks. The16 Kbyte Boot Block can be
used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
Chip Enable, Output Enableand Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device atthese or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periodsmay affect device reliability. Referalso tothe STMicroelectronics SUREProgram and other relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for lessthan 20ns during transitions.
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature (TemperatureRange Option 1) 0 to 70 °C
Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
T
BIAS
Temperature Under Bias –50 to 125 °C
T
STG
Storage Temperature –65 to 150 °C
V
IO
(2)
Input or Output Voltage –0.6 to 4 V
V
CC
Supply Voltage –0.6 to 4 V
V
ID
Identification Voltage –0.6 to 13.5 V
Table 3. Top Boot Block Addresses
M29W200BT
#
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
6 16 3C000h-3FFFFh 1E000h-1FFFFh
5 8 3A000h-3BFFFh 1D000h-1DFFFh
4 8 38000h-39FFFh 1C000h-1CFFFh
3 32 30000h-37FFFh 18000h-1BFFFh
2 64 20000h-2FFFFh 10000h-17FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh
0 64 00000h-0FFFFh 00000h-07FFFh
Table 4. Bottom Boot Block Addresses
M29W200BB
#
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 20000h-2FFFFh 10000h-17FFFh
4 64 10000h-1FFFFh 08000h-0FFFFh
3 32 08000h-0FFFFh 04000h-07FFFh
2 8 06000h-07FFFh 03000h-03FFFh
1 8 04000h-05FFFh 02000h-02FFFh
0 16 00000h-03FFFh 00000h-01FFFh
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M29W200BT, M29W200BB
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SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, fora brief overview ofthesignals connected to this device.
Address Inputs (A0-A16). The Address Inputs
select the cells in the memoryarray to access during Bus Read operations. During BusWrite operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs outputthe datastored at the selected
address during a Bus Readoperation. DuringBus
Write operations they represent the commands
sent tothe Command Interface of theinternal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs outputthe datastored at the selected
address during a Bus Readoperation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and arehigh impedance.During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves asan address
pin; DQ15A–1 Low willselect the LSB of the Word
on the other addresses, DQ15A–1 Highwill select
the MSB. Throughout thetext consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory,allowing BusRead and Bus Writeoperations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Reset/BlockTemporaryUnprotect(RP). The Reset/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or totemporarily unprotect all Blocks that have been protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High,VIH, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whicheveroccurs last. See the Ready/Busy
Output section, Table 17 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at VIDwill temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition fromVIHtoVIDmustbe slower than
t
PHPHH
.
Ready/Busy Output (RB). The Ready/Busy pin
is anopen-drain output that can beused to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode,Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 17 and Figure
11, Reset/Temporary Unprotect AC Characteristics.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use ofan open-drain output allowsthe Ready/
Busy pins fromseveral memories tobe connected
to asingle pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/WordOrganizationSelect(BYTE). The Byte/
Word OrganizationSelect pinis used to switch between the 8-bitand 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low,
VIL, the memory is in 8-bit mode, when it is High,
VIH, the memory is in 16-bit mode.
VCCSupply Voltage. The VCCSupply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabledwhen the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. Thisprevents Bus Write operationsfrom accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming orerasing during
this time thenthe operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCCSupply Voltage pin and the VSSGround
pin to decouplethe current surges from the power
supply. The PCB track widthsmust be sufficient to
carry the currents required during program and
erase operations, I
CC3
.
VSSGround. The VSSGroundis thereference for
all voltage measurements.
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M29W200BT, M29W200BB
Table 5. Bus Operations, BYTE = V
IL
Note: X = VILor VIH.
Table 6. Bus Operations, BYTE = V
IH
Note: X = VILor VIH.
Operation E G W
Address Inputs
DQ15A–1, A0-A16
Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Bus Read
V
IL
V
IL
V
IH
Cell Address Hi-Z Data Output
Bus Write
V
IL
V
IH
V
IL
Command Address Hi-Z Data Input
Output Disable X
V
IH
V
IH
X Hi-Z Hi-Z
Standby
V
IH
X X X Hi-Z Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
IH
A0 = VIL,A1=VIL,A9=VID,
Others V
IL
or V
IH
Hi-Z 20h
Read Device Code V
IL
V
IL
V
IH
A0 = VIH,A1=VIL,A9=VID,
Others V
IL
or V
IH
Hi-Z
51h (M29W200BT)
57h (M29W200BB)
Operation E G W
Address Inputs
A0-A16
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read
V
IL
V
IL
V
IH
Cell Address Data Output
Bus Write
V
IL
V
IH
V
IL
Command Address Data Input
Output Disable X
V
IH
V
IH
X Hi-Z
Standby
V
IH
X X X Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
IH
A0 = VIL,A1=VIL,A9=VID,
Others V
IL
or V
IH
0020h
Read Device Code
V
IL
V
IL
V
IH
A0 = VIH,A1=VIL,A9=VID,
Others V
IL
or V
IH
0051h (M29W200BT)
0057h (M29W200BB)
BUS OPERATIONS
There are five standardbusoperations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or WriteEnable areignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desiredaddress on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the CommandInterface on the falling edgeof Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or Write Enable,whichever occursfirst.OutputEnable must remain High, VIH, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
be held within VCC± 0.2V. For the Standby current
level see Table 13, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
, for Program orErase operationsun-
til the operation completes.
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M29W200BT, M29W200BB
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AutomaticStandby. If CMOSlevels (VCC± 0.2V)
are usedto drive thebus and the busis inactivefor
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VIDto be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 5 and 6, Bus Operations.
Block Protection andBlocksUnprotection. Each
block can be separately protected against accidental Program or Erase.Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commandschanges depending on whether the memory is in 16-bit or 8bit mode. See either Table 7, or 8, depending on
the configurationthat isbeing used, for a summary
of the commands.
Read/Reset Command. The Read/Reset command returns the memory toits Read modewhere
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Eraseoperation or followinga Programming
or Eraseerror then the memory will takeup to10µs
to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VILandA1 = VIL. The otheraddress bits
may be set to either VILor VIH. The Manufacturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIHand A1 = VIL. The other
address bits may be set to either VILor VIH. The
Device Code for the M29W200BT is0051h and for
the M29W200BB is 0057h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12-A16 specifying the address of
the block. The other address bits may be set toeither VILor VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires four Bus Write operations,the final write operation latches theaddress and data inthe internal
state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register isnever read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abortor pause the operation. Typical
program timesare givenin Table 9. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note thatthe Program command cannotchange a
bit set at ’0’ back to ’1’. One of the Erase Commands mustbe used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
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M29W200BT, M29W200BB
Table 7. Commands, 16-bit mode, BYTE = V
IH
Table 8. Commands, 8-bit mode, BYTE = V
IL
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is V
IL
or DQ15when BYTE is VIH.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, readManufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, BlockErase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until Timeout Bit isset.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory asnormal until another command is issued.
Erase Suspend. After the EraseSuspend command readnon-erasing memory blocks as normal, issue AutoSelect and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
1X F0
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program
2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
Program
2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
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M29W200BT, M29W200BB
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Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command toprogram the memory. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program commandbehaves identically to theProgram operation using the Program command. A
protected block cannot be programmed; the operation cannot be aborted and theStatus Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock Bypass Mode.See the Programcommand for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two BusWrite operations are required to issuethe
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase command canbeused to erase the entire chip. SixBus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the ChipErase operation appears tostart but will terminatewithinabout 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operationthe memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 9. All Bus Read operations during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
TheChip Erase Command setsall of the bits in unprotected blocks of thememory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase command can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last BusWrite operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks.Each additional block must therefore
be selectedwithin 50µsof the lastblock. The50µs
timer restarts when an additionalblock is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocksare protected thenthese are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving thedata unchanged.No error condition is givenwhen protected blocks are ignored.
During the Block Erase operation the memorywill
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 9. All Bus Read operations during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completedthe
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
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M29W200BT, M29W200BB
Erase Suspend Command. The Erase Suspend
Command may beused to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller willsuspend within
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memorywill be set to Read mode and
the Erasewill be suspended. Ifthe Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspendedimmediately and will start immediately when the Erase Resume Command is
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. Reading from blocks that
are being erased willoutput the Status Register. It
is alsopossible toenter the Auto Selectmode: the
memorywill behaveas in the Auto Selectmode on
all blocks until aRead/Reset commandreturnsthe
memory to Erase Suspend mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Table 9. Program, Erase Times and Program, Erase EnduranceCycles
(TA= 0 to 70°C or –40 to 85°C)
Note: 1. TA=25°C, VCC= 3.3V.
Parameter Min
Typ
(1)
Typical after
100k W/E Cycles
(1)
Max Unit
Chip Erase (All bits in the memory set to ‘0’) 1.3 1.3 sec
Chip Erase 3 3 18 sec
Block Erase (64 Kbytes) 0.8 0.8 6 sec
Program (Byte or Word) 10 10 200 µs
Chip Program (Byte by Byte) 2.8 2.8 15 sec
Chip Program (Word by Word) 1.4 1.4 8 sec
Program/Erase Cycles (per Block) 100,000 cycles
Page 10
M29W200BT, M29W200BB
10/22
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It isalso read during Erase Suspend whenanaddress within a block beingerased
is accessed.
The bits in the Status Register are summarized in
Table 10, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read modeand BusRead operationsfrom theaddress just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successfulcompletion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an example of how touse theData Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whetherthe Program/Erase Controllerhas
successfully completed its operation or if ithas responded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After
successful completion of the operation thememory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output whenaddressing a cellwithin a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, BlockErase or Chip Erase operationfails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output onDQ5 whenthe Status Registeris read.
Note thatthe Program command cannotchange a
bit setat ’0’back to ’1’ andattempting to dosomay
or may not set DQ5at ’1’. In both cases, a successive BusRead operationwill showthe bit is still ’0’.
One of theErase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
Table 10. Status Register Bits
Note: Unspecified data bits should be ignored.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0
Program During Erase
Suspend
Any Address DQ7 Toggle 0 – – 0
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout
Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase
Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend
Erasing Block 1 No Toggle 0 – Toggle 1
Non-Erasing Block Data read as normal 1
Erase Error
Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
Page 11
11/22
M29W200BT, M29W200BB
Figure 4. Data Polling Flowchart
READ DQ5 &
DQ7
at VALID ADDRESS
START
READ
DQ7
at VALID ADDRESS
FAIL PASS
AI03598
DQ7
=
DATA
YES
NO
YES
NO
DQ5
=1
DQ7
=
DATA
YES
NO
Figure 5. Data Toggle Flowchart
READ DQ6
START
READ
DQ6
TWICE
FAIL PASS
AI01370B
DQ6
=
TOGGLE
NO
NO
YES
YES
DQ5
=1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 &DQ6
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the EraseTimer Bit is set to ’1’. Beforethe
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During ChipErase andBlock Eraseoperations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocksbeing erased. Oncethe operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be setthe Alternative Toggle Bit can be used to
identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change ifthe addressed block haserased correctly.
Page 12
M29W200BT, M29W200BB
12/22
Figure 6. AC Testing Input Output Waveform
AI01417
3V
0V
1.5V
Figure 7. AC Testing Load Circuit
AI02762
0.8V
OUT
CL= 30pF or 100pF
CLincludes JIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table 12. Capacitance
(TA=25°C, f =1 MHz)
Note: Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
C
IN
Input Capacitance
V
IN
=0V
6pF
C
OUT
Output Capacitance V
OUT
=0V 12 pF
Table 11. AC Measurement Conditions
Parameter
M29W200B
55 70 90 / 120
V
CC
Supply Voltage
3.0 to 3.6V 2.7 to 3.6V 2.7 to3.6V
Load Capacitance (C
L
) 30pF 30pF 100pF
Input Rise and Fall Times ≤ 10ns ≤ 10ns ≤ 10ns
Input Pulse Voltages 0 to 3V 0 to 3V 0 to 3V
Input and Output Timing Ref. Voltages 1.5V 1.5V 1.5V
Page 13
13/22
M29W200BT, M29W200BB
Table 13. DC Characteristics
(TA= 0 to 70°C or –40 to 85°C)
Note: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
I
LI
Input Leakage Current
0V ≤ V
IN
≤ V
CC
±1 µA
I
LO
Output Leakage Current
0V ≤ V
OUT
≤ V
CC
±1
µA
I
CC1
Supply Current (Read)
E=V
IL
,G=VIH,f=6MHz
10 mA
I
CC2
Supply Current (Standby)
E=V
CC
± 0.2V
100
µA
I
CC3
(1)
Supply Current (Program/Erase)
Program/Erase
Controller active
20 mA
V
IL
Input Low Voltage –0.5 0.8 V
V
IH
Input High Voltage 0.7V
CC
VCC+ 0.3 V
V
OL
Output Low Voltage
I
OL
= 1.8mA
0.45 V
V
OH
Output High Voltage IOH= –100µA
V
CC
– 0.4
V
V
ID
Identification Voltage 11.5 12.5 V
I
ID
Identification Current
A9 = V
ID
100
µA
V
LKO
(1)
Program/Erase Lockout Supply
Voltage
1.8 2.3 V
Page 14
M29W200BT, M29W200BB
14/22
Figure 8. Read Mode AC Waveforms
AI02915
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A16/
A–1
G
DQ0-DQ7/
DQ8-DQ15
E
tELQV tEHQX
tGHQZ
VALID
tBHQV
tELBL/tELBH tBLQZ
BYTE
Table 14. Read AC Characteristics
(TA= 0 to 70°C or –40 to 85°C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter Test Condition
M29W200B
Unit
55 70 90 / 120
t
AVAV
t
RC
Address Validto NextAddress Valid
E=V
IL
,
G=V
IL
Min 55 70 90 ns
t
AVQV
t
ACC
Address Valid to Output Valid
E=V
IL
,
G=V
IL
Max 55 70 90 ns
t
ELQX
(1)
t
LZ
Chip Enable Low to Output
Transition
G=V
IL
Min 0 0 0 ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G=V
IL
Max 55 70 90 ns
t
GLQX
(1)
t
OLZ
Output Enable Low to Output
Transition
E=V
IL
Min 0 0 0 ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E=V
IL
Max 30 30 35 ns
t
EHQZ
(1)
t
HZ
Chip Enable High to Output Hi-Z
G=V
IL
Max 20 25 30 ns
t
GHQZ
(1)
t
DF
Output Enable High to Output Hi-Z
E=V
IL
Max 20 25 30 ns
t
EHQX
t
GHQX
t
AXQX
t
OH
Chip Enable, Output Enable or
Address Transition to Output
Transition
Min 0 0 0 ns
t
ELBL
t
ELBH
t
ELFL
t
ELFH
Chip Enable to BYTE Low or High Max 5 5 5 ns
t
BLQZ
t
FLQZ
BYTE Low to Output Hi-Z Max 25 25 30 ns
t
BHQV
t
FHQV
BYTE High to Output Valid Max 30 30 40 ns
Page 15
15/22
M29W200BT, M29W200BB
Figure 9. Write AC Waveforms, Write Enable Controlled
AI01991
E
G
W
A0-A16/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
V
CC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
Table 15. Write AC Characteristics, Write Enable Controlled
(TA= 0 to 70°C or –40 to 85°C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter
M29W200B
Unit
55 70 90 / 120
t
AVAV
t
WC
Address Valid toNext Address Valid Min 55 70 90 ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low Min 0 0 0 ns
t
WLWH
t
WP
Write Enable Low to Write Enable High Min 40 45 45 ns
t
DVWH
t
DS
Input Valid to Write Enable High Min 25 30 45 ns
t
WHDX
t
DH
Write Enable High to Input Transition Min 0 0 0 ns
t
WHEH
t
CH
Write Enable High to Chip Enable High Min 0 0 0 ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low Min 30 30 30 ns
t
AVWL
t
AS
Address Valid toWrite Enable Low Min 0 0 0 ns
t
WLAX
t
AH
Write Enable Low to Address Transition Min 40 45 45 ns
t
GHWL
Output Enable High to Write Enable Low Min 0 0 0 ns
t
WHGL
t
OEH
Write Enable High to Output Enable Low Min 0 0 0 ns
t
WHRL
(1)
t
BUSY
Program/Erase Valid to RB Low Max 30 30 35 ns
t
VCHEL
t
VCS
VCCHigh to Chip Enable Low
Min 50 50 50 µs
Page 16
M29W200BT, M29W200BB
16/22
Table 16. Write AC Characteristics, Chip Enable Controlled
(TA= 0 to 70°C or –40 to 85°C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter
M29W200B
Unit
55 70 90 / 120
t
AVAV
t
WC
Address Valid toNext Address Valid Min 55 70 90 ns
t
WLEL
t
WS
Write Enable Low to Chip Enable Low Min 0 0 0 ns
t
ELEH
t
CP
Chip Enable Low to Chip Enable High Min 40 45 45 ns
t
DVEH
t
DS
Input Valid to Chip Enable High Min 25 30 45 ns
t
EHDX
t
DH
Chip Enable High to Input Transition Min 0 0 0 ns
t
EHWH
t
WH
Chip Enable High to Write Enable High Min 0 0 0 ns
t
EHEL
t
CPH
Chip Enable High to Chip EnableLow Min 30 30 30 ns
t
AVEL
t
AS
Address Valid toChip Enable Low Min 0 0 0 ns
t
ELAX
t
AH
Chip Enable Low to Address Transition Min 40 45 45 ns
t
GHEL
Output Enable High Chip Enable Low Min 0 0 0 ns
t
EHGL
t
OEH
Chip Enable High to Output Enable Low Min 0 0 0 ns
t
EHRL
(1)
t
BUSY
Program/Erase Valid to RB Low Max 30 30 35 ns
t
VCHWL
t
VCS
VCCHigh to Write Enable Low
Min 50 50 50 µs
Figure 10. Write AC Waveforms, Chip Enable Controlled
AI01992
E
G
W
A0-A16/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
V
CC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
Page 17
17/22
M29W200BT, M29W200BB
Table 17. Reset/Block Temporary Unprotect AC Characteristics
(TA= 0 to 70°C or –40 to 85°C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter
M29W200B
Unit
55 70 90 / 120
t
PHWL
(1)
t
PHEL
t
PHGL
(1)
t
RH
RP High to Write Enable Low,Chip Enable
Low, Output Enable Low
Min 50 50 50 ns
t
RHWL
(1)
t
RHEL
(1)
t
RHGL
(1)
t
RB
RB High to Write Enable Low,Chip Enable
Low, Output Enable Low
Min 0 0 0 ns
t
PLPX
t
RP
RP Pulse Width Min 500 500 500 ns
t
PLYH
(1)
t
READY
RP Low to Read Mode Max 10 10 10 µs
t
PHPHH
(1)
t
VIDR
RP Rise Timeto V
ID
Min 500 500 500 ns
Figure 11. Reset/Block Temporary Unprotect AC Waveforms
AI02931
RB
W,
RP
tPLPX
tPHWL, tPHEL, tPHGL
tPLYH
tPHPHH
E, G
tRHWL, tRHEL, tRHGL
Page 18
M29W200BT, M29W200BB
18/22
Table 18. OrderingInformation Scheme
Note: The last twocharacters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with thememory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on anyaspect of this device, please contact the ST Sales Office nearest to you.
Example: M29W200BB 55 N 1 T
Device Type
M29
Operating Voltage
W=V
CC
= 2.7 to 3.6V
Device Function
200B = 2 Mbit (256Kb x8 or 128Kb x16), BootBlock
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
120 = 120 ns
Package
N = TSOP48: 12 x 20 mm
M = SO44
Temperature Range
1=0to70°C
6=–40to85°C
Option
T = Tape & Reel Packing
Page 19
19/22
M29W200BT, M29W200BB
Table 19. Revision History
Date Revision Details
July 1999 First Issue
03/30/00
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 4)
Data ToggleFlowchart diagram change (Figure 5)
Program/Erase Times Maximum specification added (Table 9)
Page 20
M29W200BT, M29W200BB
20/22
Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol
mm inches
Typ Min Max Typ Min Max
A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413
B 0.17 0.27 0.0067 0.0106
C 0.10 0.21 0.0039 0.0083
D 19.80 20.20 0.7795 0.7953
D1 18.30 18.50 0.7205 0.7283
E 11.90 12.10 0.4685 0.4764
e 0.50 – – 0.0197 – –
L 0.50 0.70 0.0197 0.0279
α 0° 5° 0° 5°
N48 48
CP 0.10 0.0039
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
Drawing is not to scale.
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
Page 21
21/22
M29W200BT, M29W200BB
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
Drawing is not to scale.
SO-b
E
N
CP
B
e
A2
D
C
LA1 α
H
A
1
Table 21. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
Symbol
mm inches
Typ Min Max Typ Min Max
A 2.42 2.62 0.0953 0.1031
A1 0.22 0.23 0.0087 0.0091
A2 2.25 2.35 0.0886 0.0925
B 0.50 0.0197
C 0.10 0.25 0.0039 0.0098
D 28.10 28.30 1.1063 1.1142
E 13.20 13.40 0.5197 0.5276
e 1.27 – – 0.0500 – –
H 15.90 16.10 0.6260 0.6339
L 0.80 – – 0.0315 – –
α 3° ––3°––
N44 44
CP 0.10 0.0039
Page 22
M29W200BT, M29W200BB
22/22
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of useofsuch information nor for any infringement ofpatents orother rights of third partieswhich may result from itsuse. Nolicense is granted
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