Datasheet M29W160DT, M29W160DB Datasheet (ST)

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Page 1

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FEATURES SUMMARY

■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 70ns

■ PROGRAMMING TIME

–10µs per Byte/Word typical

■ 35 MEMORYBLOCKS

– 1 Boot Block (Top or Bottom Location) – 2 Parameter and 32 Main Blocks

■ PROGRAM/ERASE CONTROLLER

– Embedded Program and Erase algorithms

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCKBYPASS PROGRAM COMMAND

– FasterProduction/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ SECURITY MEMORY BLOCK

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h – Top Device Code M29W160DT: 22C4h – Bottom Device Code M29W160DB: 2249h

M29W160DT

M29W160DB

16 Mbit (2Mb x8 or 1Mb x16, Boot Block)

3V Supply Flash Memory

PRELIMINARY DATA

Figure 1. Packages

TSOP48 (N)

12 x 20mm

LFBGA48 (ZA)

8 x 6 solder balls

SO44 (M)

FBGA

January 2001

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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M29W160DT, M29W160DB

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . ...................................................5

Logic Diagram . .................................................................5

Signal Names . .................................................................5

TSOP Connections . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............6

SO Connections . . . . . . . . . .......................................................6

LFBGA Connections (Top view through package) . . . . . . . ...............................7

Table 2. Top Boot Block Addresses, M29W160DT. . ....................................8

Table 3. Bottom Boot Block Addresses, M29W160DB . . . . . . . . . . . . . . . . . . . . ...............8

SIGNAL DESCRIPTIONS . . ..........................................................9

Address Inputs (A0-A19). . . . . . . ...................................................9

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . .....................................9

Data Input/Output or Address Input (DQ15A-1). . . . .....................................9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............................9

Output Enable (G). . . . . . . . . . . . . . . . ...............................................9

Write Enable (W). . . . . . . . . . . . . ...................................................9

Reset/Block Temporary Unprotect (RP).. . ............................................9

Ready/Busy Output (RB). . . . . . . ...................................................9

Byte/Word Organization Select (BYTE). . . . . . . . . ......................................9

Supply Voltage. . . . . . . . . . . . . . . . . . ............................................9

Vss Ground.. . ..................................................................9

BUS OPERATIONS. . . . . . . . . . . . . . ..................................................10

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . ...........................................10

Bus Write. ....................................................................10

Output Disable. . . ..............................................................10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................10

Special Bus Operations. .........................................................10

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protection and Blocks Unprotection. ...........................................10

Table 4. Bus Operations, BYTE = VIL...............................................10

Table 5. Bus Operations, BYTE = VIH...............................................11

COMMAND INTERFACE . . . . . . . . . . . . . . . . ...........................................11

Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . ....................................11

Auto Select Command. . . . .......................................................11

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . ...................................11

Unlock Bypass Command. . . . . . ..................................................12

Unlock Bypass Program Command. . . . . . . . . . . . . . . . .................................12

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . .................................12

Chip Erase Command. . . . . ......................................................12

Block Erase Command.. .........................................................12

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M29W160DT, M29W160DB

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................12

Erase Resume Command. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........13

Security Data Command. . . . . . . . . . . . . . ...........................................13

Table 6. Security Memory Block Addresses . . . .......................................13

Table 7. Commands, 16-bit mode, BYTE = VIH.......................................14

Table 8. Commands, 8-bit mode, BYTE = VIL.........................................15

Table 9. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 16

STATUS REGISTER . . . . . . . . . . . . . ..................................................16

Data Polling Bit (DQ7). . . . . ......................................................16

Toggle Bit (DQ6).. . . . . . .........................................................16

Error Bit (DQ5). . . ..............................................................16

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . .................................17

Alternative Toggle Bit (DQ2).. . . ...................................................17

Table 10. Status Register Bits. . . . . . . . . . . . . . . . . . ...................................17

Figure 6. Data Polling Flowchart . ..................................................18

Figure 7. Data Toggle Flowchart. . . . .. . . ...........................................18

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . ...........................................18

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . .................................18

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................19

Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

AC Measurement I/O Waveform . ..................................................19

AC Measurement Load Circuit . . ..................................................19

Capacitance. . . . . . . . . . . . .......................................................19

DC Characteristics. . . . . . . . . . . . . . . . . . . ...........................................20

Read Mode AC Waveforms. ......................................................21

Read AC Characteristics .........................................................21

Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........22

Write AC Characteristics, Write Enable Controlled . . ...................................22

Write AC Waveforms, Chip Enable Controlled . . . . ....................................23

Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . .......................23

Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . ..............24

Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . ..................24

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . ...........25

TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . . . . . . . . . 25

SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . . . . . ....26

LFBGA48 - 8 x 6 balls, 0.80 mm pitch, Bottom View Package Outline......................27

LFBGA48 - 8 x 6 balls, 0.80mm pitch, Package Mechanical Data . . . ......................27

PART NUMBERING . . . . . . . . . ......................................................28

Ordering Information Scheme . . . . . . . . . . . . . . . . . ....................................28

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M29W160DT, M29W160DB

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................28

Document Revision History .......................................................28

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SUMMARY DESCRIPTION

The M29W160D is a 16 Mbit (2Mb x8 or 1Mbx16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process ofprogramming or erasing the memory by taking care of all of the specialoperations that are required to update the memory contents.

The end of a program or erase operation can be detected and any error conditions identified. The

M29W160DT, M29W160DB

command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory are asymmetrically arranged,see Tables2 and3, BlockAddresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for smallinitialization code to startthe microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored.

Chip Enable, Output Enableand Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm), SO44 and LFBGA48 (0.8mm pitch) packages and it is supplied with all the bits erased (set to ’1’).

Figure 2. Logic Diagram

A0-A19

E G

Note: RB not available on SO44 package.

M29W160DT M29W160DB

DQ0-DQ14

DQ15A–1 BYTE RB

AI03843

Table 1. Signal Names

A0-A19 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect

BYTE Byte/Word Organization Select V

NC Not Connected Internally DU Don’t Use as internally connected

Ready/Busy Output (Not available on SO44 package)

Supply Voltage Ground

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M29W160DT, M29W160DB

Figure 3. TSOP Connections Figure 4. SO Connections

A15 A14 A13 A12 A11 A10 DQ14

A19

RP NC NC

A18 A17

A9 A8

M29W160DT M29W160DB

A7 A6 A5 A4 A3 A2 A1

24 25

AI03844

37 36

A16 BYTE V

DQ15A–1 DQ7

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

E A0

RP A18 A17 A8

A7 A6 A5 A4 A3 A2 A1 A0

DQ0 DQ8

1 2 3 4 5 6 7 8 9 10 11

M29W160DT

M29W160DB

12 13

14 15 16 17DQ1

DQ9

18 19

DQ10

DQ3

20 21

DQ11

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 2322

AI03845

W A19

A9 A10 A11 A12 A13 A14 A15 A16 BYTE V

DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5DQ2 DQ12 DQ4 V

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Figure 5. LFBGA Connections (Top view through package)

M29W160DT, M29W160DB

654321

A17

DQ0

DQ8

DQ9

DQ1

A18

DQ2

DQ10

DQ11

DQ3

A19

DQ5

DQ12

DQ4

A10

A11

DQ7

DQ14

DQ13

DQ6

A13

A12

A14

A15

A16

BYTE

DQ15

A–1

AI02985B

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M29W160DT, M29W160DB

Table 2. Top Boot Block Addresses, M29W160DT

Size

(Kby t es)

34 16 1FC000h-1FFFFFh FE000h-FFFFFh 33 8 1FA000h-1FBFFFh FD000h-FDFFFh 32 8 1F8000h-1F9FFFh FC000h-FCFFFh 31 32 1F0000h-1F7FFFh F8000h-FBFFFh 30 64 1E0000h-1EFFFFh F0000h-F7FFFh 29 64 1D0000h-1DFFFFh E8000h-EFFFFh 28 64 1C0000h-1CFFFFh E0000h-E7FFFh 27 64 1B0000h-1BFFFFh D8000h-DFFFFh 26 64 1A0000h-1AFFFFh D0000h-D7FFFh 25 64 190000h-19FFFFh C8000h-CFFFFh 24 64 180000h-18FFFFh C0000h-C7FFFh 23 64 170000h-17FFFFh B8000h-BFFFFh 22 64 160000h-16FFFFh B0000h-B7FFFh 21 64 150000h-15FFFFh A8000h-AFFFFh 20 64 140000h-14FFFFh A0000h-A7FFFh 19 64 130000h-13FFFFh 98000h-9FFFFh 18 64 120000h-12FFFFh 90000h-97FFFh 17 64 110000h-11FFFFh 88000h-8FFFFh 16 64 100000h-10FFFFh 80000h-87FFFh 15 64 0F0000h-0FFFFFh 78000h-7FFFFh 14 64 0E0000h-0EFFFFh 70000h-77FFFh 13 64 0D0000h-0DFFFFh 68000h-6FFFFh 12 64 0C0000h-0CFFFFh 60000h-67FFFh 11 64 0B0000h-0BFFFFh 58000h-5FFFFh 10 64 0A0000h-0AFFFFh 50000h-57FFFh

9 64 090000h-09FFFFh 48000h-4FFFFh 8 64 080000h-08FFFFh 40000h-47FFFh 7 64 070000h-07FFFFh 38000h-3FFFFh 6 64 060000h-06FFFFh 30000h-37FFFh 5 64 050000h-05FFFFh 28000h-2FFFFh 4 64 040000h-04FFFFh 20000h-27FFFh 3 64 030000h-03FFFFh 18000h-1FFFFh 2 64 020000h-02FFFFh 10000h-17FFFh 1 64 010000h-01FFFFh 08000h-0FFFFh 0 64 000000h-00FFFFh 00000h-07FFFh

AddressRange

(x8)

Addres sRange

(x16)

Table 3. Bottom Boot Block Addresses, M29W160DB

Size

(Kbytes)

34 64 1F0000h-1FFFFFh F8000h-FFFFFh 33 64 1E0000h-1EFFFFh F0000h-F7FFFh 32 64 1D0000h-1DFFFFh E8000h-EFFFFh 31 64 1C0000h-1CFFFFh E0000h-E7FFFh 30 64 1B0000h-1BFFFFh D8000h-DFFFFh 29 64 1A0000h-1AFFFFh D0000h-D7FFFh 28 64 190000h-19FFFFh C8000h-CFFFFh 27 64 180000h-18FFFFh C0000h-C7FFFh 26 64 170000h-17FFFFh B8000h-BFFFFh 25 64 160000h-16FFFFh B0000h-B7FFFh 24 64 150000h-15FFFFh A8000h-AFFFFh 23 64 140000h-14FFFFh A0000h-A7FFFh 22 64 130000h-13FFFFh 98000h-9FFFFh 21 64 120000h-12FFFFh 90000h-97FFFh 20 64 110000h-11FFFFh 88000h-8FFFFh 19 64 100000h-10FFFFh 80000h-87FFFh 18 64 0F0000h-0FFFFFh 78000h-7FFFFh 17 64 0E0000h-0EFFFFh 70000h-77FFFh 16 64 0D0000h-0DFFFFh 68000h-6FFFFh 15 64 0C0000h-0CFFFFh 60000h-67FFFh 14 64 0B0000h-0BFFFFh 58000h-5FFFFh 13 64 0A0000h-0AFFFFh 50000h-57FFFh 12 64 090000h-09FFFFh 48000h-4FFFFh 11 64 080000h-08FFFFh 40000h-47FFFh 10 64 070000h-07FFFFh 38000h-3FFFFh

9 64 060000h-06FFFFh 30000h-37FFFh 8 64 050000h-05FFFFh 28000h-2FFFFh 7 64 040000h-04FFFFh 20000h-27FFFh 6 64 030000h-03FFFFh 18000h-1FFFFh 5 64 020000h-02FFFFh 10000h-17FFFh 4 64 010000h-01FFFFh 08000h-0FFFFh 3 32 008000h-00FFFFh 04000h-07FFFh 2 8 006000h-007FFFh 03000h-03FFFh 1 8 004000h-005FFFh 02000h-02FFFh 0 16 000000h-003FFFh 00000h-01FFFh

Address Range

(x8)

Address Range

(x16)

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SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Signal Names, fora brief overview ofthesignals connected to this device.

Address Inputs (A0-A19).

The Address Inputs select the cells in the memoryarray to access during Bus Read operations. During BusWrite operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7).

The Data Inputs/Outputs outputthe datastored at the selected address during a Bus Readoperation. DuringBus Write operations they represent the commands sent tothe Command Interface of theinternal state machine.

Data Inputs/Outputs (DQ8-DQ14).

The Data Inputs/Outputs outputthe datastored at the selected address during a Bus Read operation when BYTE is High, V

. When BYTE is Low, VIL, these pins

are not used and arehigh impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves asan address pin; DQ15A–1 Low willselect the LSB of the Word on the other addresses, DQ15A–1 Highwill select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates the memory,allowing BusRead and Bus Writeoperations to be performed. When Chip Enable is High, V

, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Resetto the memory or to temporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V t

. After Reset/Block Temporary Unprotect

PLPX

, for at least

goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after t

PHEL

M29W160DT, M29W160DB

, whicheveroccurs last. See the Ready/Busy

RHEL

Output section, Table 18 and Figure 13, Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP at VIDwill temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIHtoVIDmustbe slower than t

Ready/Busy Output (RB).

is anopen-drain output that canbe used toidentify when the memory array can be read. Ready/Busy is high-impedance during Read mode,Auto Select mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 18 and Figure 13, Reset/Temporary Unprotect AC Characteristics.

During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.

The use ofan open-drain output allowsthe Ready/ Busy pins from several memories to be connected to asingle pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select isLow, V it is High, VIH, the memory is in 16-bit mode.

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabledwhen the V Supply Voltage is less than the Lockout Voltage, V cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming orerasing during this time thenthe operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor should be connected between the VCCSupply Voltage pin and the VSSGround pin to decouplethe current surges from the power supply. The PCB track widthsmust be sufficient to carry the currents required during program and erase operations, I

Vss Ground. The VSSGround is the reference for all voltage measurements.

PHPHH

The Ready/Busy pin

, the memory is in 8-bit mode, when

Supply Voltage. The VCCSupply Voltage

. Thisprevents Bus Write operationsfrom ac-

LKO

CC3

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Page 10

M29W160DT, M29W160DB

BUS OPERATIONS

There are five standardbusoperations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 4 and 5, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or WriteEnable areignored by the memory and do not affect bus operations.

Bus Read.

memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desiredaddress on the Address Inputs, applying a Low signal, V and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 10, Read Mode AC Waveforms, and Table 15, Read AC Characteristics, for details of when the output becomes valid.

Bus Write.

Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the CommandInterface on the falling edgeof Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by theCommand Interface on the rising edge of Chip Enable or WriteEnable, whichever occursfirst.Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 11 and 12, Write AC Waveforms, and Tables 16 and 17, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V

Standby. When Chip Enable is High, V memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the

Bus Read operations read from the

, to Chip Enable

Bus Write operations write to the

, the

Standby Supply Current, I be held within VCC±

0.2V.For theStandby current

, Chip Enable should

CC2

level see Table 14, DC Characteristics. During program or erase operations the memory

will continue to use the Program/Erase Supply Current, I

, for Program orErase operationsun-

CC3

til the operation completes.

Automatic Standby.

If CMOSlevels (VCC±

0.2V) are used todrive thebus andthe busis inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, I

CC2

. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations.

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VIDto be applied to some pins.

Electronic Signature.

The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 4 and 5, Bus Operations.

Block Protection and BlocksUnprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.

Table 4. Bus Operations, BYTE = V

Operation E G W

Bus Read V Bus Write Output Disable X Standby Read Manufacturer

Code

Read Device Code

Note: X = VILor VIH.

10/29

X X X Hi-Z Hi-Z

Address Inputs

DQ15A–1, A0-A19

Cell Address Hi-Z Data Output

Command Address Hi-Z Data Input

X Hi-Z Hi-Z

A0 = VIL,A1=VIL,A9=VID,

Others V A0 = VIH,A1=VIL,A9=VID,

Others V

or V

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Hi-Z 20h

Hi-Z

C4h (M29W160DT) 49h (M29W160DB)

Page 11

M29W160DT, M29W160DB

Table 5. Bus Operations, BYTE = V

Operation E G W

Bus Read Bus Write Output Disable X Standby Read Manufacturer

Code

Read Device Code V

Note: X = VILor VIH.

X X X Hi-Z

Cell Address Data Output

Command Address Data Input

X Hi-Z

A0 = VIL,A1=VIL,A9=VID,

Others V A0 = VIH,A1=VIL,A9=VID,

Others V

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The address used for the commandschanges depending on whether the memory is in 16-bit or 8bit mode. See either Table 7, or 8, depending on the configurationthat isbeing used, for a summary of the commands.

Read/Reset Command. The Read/Reset command returns the memory toits Read modewhere it behaves like a ROM or EPROM, unless stated otherwise (see Security Data command). It also resets the errors in the Status Register. Either one or threeBus Write operationscan beused to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Eraseoperation or followinga Programming or Erase error then the memory will takeupto 10µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VILand A1 = VIL. The otheraddress bits

Address Inputs

A0-A19

or V

may be set to either V

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

0020h

22C4h (M29W160DT)

2249h (M29W160DB)

or VIH. The Manufacturer

Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read

operation with A0 = VIHand A1 = VIL. The other address bits may be set to either VILor VIH. The Device Code for the M29W160DT is 22C4h and for the M29W160DB is 2249h.

The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A19 specifying the address of the block. The other address bits may be set toeither VILor VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations,the final write operation latches theaddress and data inthe internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register isnever read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program timesare given in Table 9. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis-

11/29

Page 12

M29W160DT, M29W160DB

ter. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannotchange a bit set at ’0’ back to ’1’. One of the Erase Commands must beused to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Unlock Bypass Command.

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

Unlock Bypass Program Command.

The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass Program commandbehaves identically to theProgram operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and theStatus Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode.See the Programcommand for details on the behavior.

Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two BusWrite operations are required to issuethe Unlock Bypass Reset command.

Chip Erase Command. The Chip Erase command canbeused to erase the entire chip. SixBus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the ChipErase operation appears tostart but will terminatewithinabout 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the erase operationthe memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 9. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.

TheChip Erase Command setsall of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.

Block Erase Command.

The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last BusWrite operation. Once the Program/Erase Controller starts it is not possible to select any more blocks.Each additional block must therefore be selectedwithin 50µs ofthe last block. The 50µs timer restarts when an additionalblock is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation.

If any selected blocksare protected thenthese are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving thedata unchanged.No error condition is givenwhen protected blocks are ignored.

During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 9. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the Block Erase operation has completedthe memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.

Erase Suspend Command. The Erase Suspend

Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus

12/29

Page 13

M29W160DT, M29W160DB

Write operation. During Erase Suspend the reset command is ignored.

The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memorywill be set to Read mode and the Erasewill be suspended. Ifthe Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspendedimmediately and will start immediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory willbehave asin the Auto Selectmode on all blocksuntil a Read/Reset commandreturns the memory to Erase Suspend mode.

Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.

Security Data Command.

The Security Data command can be used toread the Security Memory Block. The Security Memory Block is a block of 256 words that is usually undefined. Volume customers can request that a unique security code is pre-programmed by ST into each part. One Bus Write operation is required to issue the Security Data command. Oncethe SecurityData command is issued Bus Read operations read from the Security Memory Block instead of the memory array, until another command is issued.

After issuing the Security Data command from Auto Select modea Read/Reset command will return to Auto Select mode. An invalid command will return to Read mode.

Valid addresses forthe Security Memory Blockare given in Table 6, Security Memory Block Addresses. Although the address for the Security Data command is Don’t Care, it is necessary to choose an address outside theSecurity Memory Block for correct operation.

Table 6. Security Memory Block Addresses

Size

(words)

256 000000h-0001FFh 000000h-0000FFh

Address Range

(x8)

Address Range

(x16)

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Page 14

M29W160DT, M29W160DB

Table 7. Commands, 16-bit mode, BYTE = V

Bus Write Operations

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1X F0

Read/Reset

3 555 AA 2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Security Data 1 X B8

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is V

Read/Reset. After aRead/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID,Device ID or Block Protection Status. Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command withadditional Bus Write Operations until Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. Erase Suspend. After the Erase Suspend command read non-erasing memory blocksas normal, issue Auto Selectand Program com-

mands on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read theStatus Register until the Pro-

gram/Erase Controller completes and the memory returns to Read Mode. Security Data. After theSecurity Data command read theSecurity Memory Block. Use an address outside theSecurity Memory Block

when issuing the command.

or DQ15 when BYTE is VIH.

14/29

Page 15

M29W160DT, M29W160DB

Table 8. Commands, 8-bit mode, BYTE = V

Bus Write Operations

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1X F0 Read/Reset

3 AAA AA 555 55 X F0 Auto Select 3 AAA AA 555 55 AAA 90 Program 4 AAA AA 555 55 AAA A0 PA PD Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Security Data 1 X B8

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command withadditional Bus Write Operations until Timeout Bit is set.

mands on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read theStatus Register until the Pro-

gram/Erase Controller completes and the memory returns to Read Mode. Security Data. After theSecurity Data command read theSecurity Memory Block. Use an address outside theSecurity Memory Block

when issuing the command.

or DQ15 when BYTE is VIH.

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Page 16

M29W160DT, M29W160DB

Table 9. Program, Erase Times and Program, Erase Endurance Cycles

Parameter Min

Chip Erase (All bits in the memory set to ‘0’) 12 sec Chip Erase 25 25 120 sec Block Erase (64 Kbytes) 0.8 6 sec Program (Byte or Word) 10 200 µs Chip Program (Byte by Byte) 25 120 sec Chip Program (Word by Word) 12 60 sec Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. TA=25°C, VCC= 3.3V.

Typ

(1)

STATUS REGISTER

Bus Read operations from any address always read the Status Register during Program and Erase operations. It isalso read during Erase Suspend whenanaddress within a block beingerased is accessed.

The bits in the Status Register are summarized in Table 10, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read modeand BusRead operationsfrom theaddress just programmed output DQ7, not its complement.

During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successfulcompletion of the Erase operation the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation.

Figure 6, Data Polling Flowchart, gives an example of how touse the Data Polling Bit. A Valid Address is the address being programmed or an

Toggle Bit (DQ6).

identify whetherthe Program/Erase Controllerhas successfully completed its operation or if ithas responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation thememory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output whenaddressing a cellwithin a block being erased. The Toggle Bit will stoptoggling when the Program/Erase Controller has suspended the Erase operation.

Figure 7, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, BlockErase or Chip Erase operationfails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output onDQ5 whenthe Status Register is read.

Note thatthe Program command cannotchange a bit setat ’0’back to ’1’ andattempting to dosomay or may not set DQ5at ‘1’. In both cases, a successive BusRead operationwill showthe bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

address within the block being erased.

Typical after

100k W/E Cycles

The Toggle Bit can be used to

(1)

Max Unit

16/29

Page 17

M29W160DT, M29W160DB

Erase Timer Bit (DQ3).

be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the EraseTimer Bit is set to ’1’. Beforethe Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.

Alternative Toggle Bit (DQ2).

Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.

During ChipErase andBlock Eraseoperations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

The Erase Timer Bit can

The Alternative

within the blocksbeing erased. Once the operation completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit to be setthe Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change ifthe addressed block haserased correctly.

successive Bus Read operations from addresses

Table 10. Status Register Bits

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2

Program Any Address DQ7 Toggle 0 – – 0 Program During Erase

Suspend Program Error Any Address DQ7 Toggle 1 – – 0 Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before timeout

Block Erase

Erase Suspend

Erase Error

Note: Unspecified data bits should be ignored.

Any Address DQ7 Toggle 0 – – 0

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

17/29

Page 18

M29W160DT, M29W160DB

Figure 6. Data Polling Flowchart Figure 7. Data Toggle Flowchart

START

READ DQ5 &

at VALID ADDRESS

READ

at VALID ADDRESS

DQ7

DATA

DQ5

DQ7

DATA

FAIL PASS

YES

DQ7

YES

AI03598

START

READ

DQ5 & DQ6

READ DQ6

DQ6

TOGGLE

YES

DQ5

YES

DQ6

READ

TWICE

DQ6

TOGGLE

YES

FAIL PASS

AI01370B

MAXIMUM RATING

Stressing the device above the rating listed in the Absolute Maximum Ratings” tablemay cause permanent damage to the device. These are stress ratings only and operationof the device atthese or any other conditions above those indicated in the

plied. Exposureto Absolute MaximumRating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

Operating sections of this specification is not im-

Table 11. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(1)

Note: 1. Minimum Voltage may undershoot to –2V during transition and for lessthan 20ns during transitions.

18/29

Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage –0.6 to 4 V Supply Voltage –0.6 to 4 V

Identification Voltage –0.6 to 13.5 V

Page 19

M29W160DT, M29W160DB

DC AND AC PARAMETERS

This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement

Table 12. Operating and AC Measurement Conditions

Parameter

Supply Voltage (V Ambient Operating Temperature (T Load Capacitance (C

)

Input Rise and Fall Times ≤ 10 ≤ 10 ns Input Pulse Voltages 0 to 3 0 to 3 V Input and Output Timing Ref. Voltages 1.5 1.5 V

Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit

Conditions summarized in Table 12, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.

M29W160D

70 90

3.0 to 3.6 2.7 to 3.6 V –40 to 85 –40 to 85 °C

30 30 pF

Unit

0.8V

1.5V

AI01417

DEVICE UNDER

TEST

CLincludes JIG capacitance

1N914

3.3kΩ

CL= 30pF

Table 13. Capacitance

Symbol Parameter TestCondition Min Max Unit

OUT

Note: Sampled only, not 100% tested.

Input Capacitance Output Capacitance

OUT

=0V

6pF

12 pF

OUT

AI03846

19/29

Page 20

M29W160DT, M29W160DB

Table 14. DC Characteristics

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

CC3

LKO

Note: Sampled only, not 100% tested.

Input Leakage Current Output Leakage Current 0V ≤ V

Supply Current (Read)

Supply Current (Standby)

(1)

Supply Current (Program/Erase)

Input Low Voltage –0.5 0.8 V

Input High Voltage Output Low Voltage Output High Voltage IOH= –100µA Identification Voltage 11.5 12.5 V Identification Current Program/Erase Lockout Supply

(1)

Voltage

0V ≤ V

E=V

≤ V

OUT

,G=VIH,

f = 6MHz

E=V

RP = V

± 0.2V,

± 0.2V

Program/Erase

Controller active

= 1.8mA

A9 = V

±1 ±1

10 mA

100

20 mA

0.7V

VCC+ 0.3

0.45 V

– 0.4

100 µA

1.8 2.3 V

µA µA

µA

20/29

Page 21

Figure 10. Read Mode AC Waveforms

A0-A19/ A–1

tAVQV tAXQX

DQ0-DQ7/ DQ8-DQ15

tBHQV

BYTE

M29W160DT, M29W160DB

tAVAV VALID

tELQV tEHQX

tELQX tEHQZ

tGLQX tGHQX

tGLQV

tGHQZ

VALID

tELBL/tELBH tBLQZ

Table 15. Read AC Characteristics

Symbol Alt Parameter Test Condition

E=V

AVAV

AVQV

(1)

ELQX

ELQV

(1)

GLQX

GLQV

(1)

EHQZ

(1)

GHQZ

EHQX

GHQX

AXQX

ELBL

ELBH

BLQZ

BHQV

Note: Sampled only, not 100% tested.

ACC

OLZ

ELFL

ELFH

FLQZ

FHQV

Address Valid toNext Address Valid

Address Valid toOutput Valid

Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid E = V Chip Enable High to Output Hi-Z G = V

Output Enable High to Output Hi-Z

Chip Enable, Output Enableor Address Transition to Output Transition

Chip Enable to BYTE Low or High Max 5 5 ns

BYTE Low to Output Hi-Z Max 25 30 ns BYTE High to Output Valid Max 30 40 ns

G=V

E=V

G=V G=V G=V E=V

E=V

M29W160D

70 90

Min 70 90 ns

Max 70 90 ns

Min 0 0 ns

Max 70 90 ns

Min 0 0 ns Max 30 35 ns Max 25 30 ns

Max 25 30 ns

Min 0 0 ns

AI02922

Unit

21/29

Page 22

M29W160DT, M29W160DB

Figure 11. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A19/ A–1

tAVWL

VALID

tWLAX

tWHEH

tELWL

tWLWHtGHWL

tDVWH

DQ0-DQ7/ DQ8-DQ15

tVCHEL

VALID

tWHRL

Table 16. Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter

AVAV

ELWL

WLWH

DVWH

WHDX

WHEH

WHWL

AVWL

WLAX

GHWL

WHGL

(1)

WHRL

VCHEL

Note: Sampled only, not 100% tested.

WPH

OEH

BUSY

VCS

Address Valid to Next Address Valid Min 70 90 ns Chip Enable Low to Write Enable Low Min 0 0 ns Write Enable Low to Write Enable High Min 45 50 ns Input Valid to Write Enable High Min 45 50 ns Write Enable High to Input Transition Min 0 0 ns Write Enable High to Chip Enable High Min 0 0 ns Write Enable High to Write Enable Low Min 30 30 ns Address Valid to Write Enable Low Min 0 0 ns Write Enable Low to Address Transition Min 45 50 ns Output Enable High to Write Enable Low Min 0 0 ns Write Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 35 ns VCCHigh to Chip Enable Low

tWHGL

tWHWL

tWHDX

AI02923

M29W160D

Unit

70 90

Min 50 50 µs

22/29

Page 23

Figure 12. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A19/ A–1

tAVEL

VALID

tELAX

M29W160DT, M29W160DB

tEHWH

tWLEL

tELEHtGHEL

tDVEH

DQ0-DQ7/ DQ8-DQ15

tVCHWL

VALID

tEHRL

Table 17. Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

AVAV

WLEL

ELEH

DVEH

EHDX

EHWH

EHEL

AVEL

ELAX

GHEL

EHGL

(1)

EHRL

VCHWL

Note: Sampled only, not 100% tested.

CPH

OEH

BUSY

VCS

Address Valid to Next Address Valid Min 70 90 ns Write Enable Low to Chip Enable Low Min 0 0 ns Chip Enable High to Chip Enable High Min 45 50 ns Input Valid to Chip Enable High Min 45 50 ns Chip Enable High to Input Transition Min 0 0 ns Chip Enable High to Write Enable High Min 0 0 ns Chip Enable Low to Chip Enable Low Min 30 30 ns Address Valid to Chip Enable Low Min 0 0 ns Chip Enable Low to Address Transition Min 45 50 ns Output Enable High Chip Enable Low Min 0 0 ns Chip Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 35 ns VCCHigh to Write Enable Low

tEHGL

tEHEL

tEHDX

AI02924

M29W160D

Unit

70 90

Min 50 50 µs

23/29

Page 24

M29W160DT, M29W160DB

Figure 13. Reset/Block Temporary Unprotect AC Waveforms

E, G

tPHWL, tPHEL, tPHGL

Table 18. Reset/Block Temporary Unprotect AC Characteristics

Symbol Alt Parameter

(1)

PHWL

PHEL

(1)

PHGL

(1)

RHWL

(1)

RHEL

(1)

RHGL

PLPX

(1)

PLYH

(1)

PHPHH

Note: Sampled only, not 100% tested.

READY

VIDR

tPLPX

tPLYH

RP High to Write Enable Low,Chip Enable Low, Output Enable Low

RB High to Write Enable Low,Chip Enable Low, Output Enable Low

RP Pulse Width Min 500 500 ns RP Low to Read Mode Max 10 10 µs

RP Rise Time to V

tRHWL, tRHEL, tRHGL

tPHPHH

AI02931

M29W160D

Unit

70 90

Min 50 50 ns

Min 0 0 ns

Min 500 500 ns

24/29

Page 25

M29W160DT, M29W160DB

PACKAGE MECHANICAL

Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

LA1 α

Table 19. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276

α 0° 5° 0° 5°

N48 48

CP 0.10 0.0039

millimeters inches

25/29

Page 26

M29W160DT, M29W160DB

Figure 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

LA1

SO-b

Note: Drawing is not to scale.

Table 20. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

millimeters inches

A 2.42 2.62 0.0953 0.1031 A1 0.22 0.23 0.0087 0.0091 A2 2.25 2.35 0.0886 0.0925

B 0.50 0.0197

C 0.10 0.25 0.0039 0.0098

D 28.10 28.30 1.1063 1.1142

E 13.20 13.40 0.5197 0.5276

e 1.27 – – 0.0500 – –

H 15.90 16.10 0.6260 0.6339

L 0.80 – – 0.0315 – –

α 3° ––3°––

N44 44

CP 0.10 0.0039

26/29

Page 27

M29W160DT, M29W160DB

Figure 16. LFBGA48 - 8 x 6 balls, 0.80 mm pitch, Bottom View Package Outline

E1E

BALL ”A1”

Note: Drawing is not to scale.

ddd

BGA-Z14

Table 21. LFBGA48 - 8 x 6 balls, 0.80mm pitch, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.350 0.0531 A1 0.300 0.200 0.350 0.0118 0.0079 0.0138 A2 1.000 0.0394

b 0.300 0.550 0.0118 0.0217

D 8.000 – – 0.3150 – –

millimeters inches

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

e 0.800 – – 0.0315 – –

E 9.000 – – 0.3543 – – E1 5.600 – – 0.2205 – – FD 2.000 – – 0.0787 – – FE 1.700 – – 0.0669 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

27/29

Page 28

M29W160DT, M29W160DB

PART NUMBERING

Table 22. Ordering Information Scheme

Example: M29W160DB 90 N 1 T

Device Type

M29

Operating Voltage

W=V

Device Function

160D = 16 Mbit (2Mb x8 or 1Mb x16), Boot Block

Array Matrix

T = Top Boot B = Bottom Boot

Speed

70 = 70 ns 90 = 90 ns

= 2.7 to 3.6V

Package

N = TSOP48: 12 x 20 mm M = SO44 ZA = LFBGA48: 0.80mm pitch

Temperature Range

1=0to70°C 6=–40to85°C

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.

REVISION HISTORY

Table 23. Document Revision History

Date Version Revision Details

July 2000 -01 First Issue

1/12/01 -02 Document type: from Product Preview to Preliminary Data

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M29W160DT, M29W160DB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of useofsuch information nor for any infringement ofpatents orother rights of third partieswhich may result from itsuse. Nolicense is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces allinformation previously supplied. STMicroelectronics products are not authorized for use as critical components in lifesupport devices or systems without express written approval of STMicroelectronics.

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Datasheet M29W160DT, M29W160DB Datasheet (ST)

Specifications and Main Features

Frequently Asked Questions

User Manual