Datasheet M29W102BT, M29W102BB Datasheet (SGS Thomson Microelectronics)

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Page 1

Low Voltage Single Supply Flash Memory

■ SINGLE 2.7 to 3.6V SU PPL Y VO LT AG E fo r

PROGRAM, ERAS E and READ O PER AT IONS

■ ACCESS TIME: 50ns

■ PROGRAMMING TIME

– 10µs per Word typical

■ 5 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location) – 2 Parameter and 2 Main Blocks

■ PROGRAM/ERA SE CON T ROL LER

– Embedded Word Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ER ASE CYCL ES per

BLOCK

■ M28F102 COMPATIBLE

– Pin-out and Read Mode

■ 20 YEARS DATA RETENTI ON

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h – Top Device Code M29W102BT: 0099h – Bottom Device Code M29W102BB: 0098h

M29W102BT

M29W102BB

1 Mbit (64Kb x16, Boot Block)

TSOP40 (N)

10 x 14mm

Figure 1. Logic Diagram

A0-A15

M29W102BT M29W102BB

DQ0-DQ15

AI02785

1/20March 2000

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M29W102BT, M29W102BB

Figure 2. TSOP Connection s

A9 A10 A11 A12 A13 A14 A15

CC RP

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8

M29W102BT M29W102BB

20 21

Table 1. Signal Names

A0-A15 Address Inputs DQ0-DQ15 Data Inputs/Outputs E

Chip Enable

31 30

AI02786

A8 A7 A6 A5 A4 A3 A2 A1 A0 G DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 V

SUMMARY DESCRIPTION

The M29W102B is a 1 Mbit (64Kb x 16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is pos sible to pres erve valid data while old data is erased. Each block can be protected independently to prev ent accidental Program or Erase commands from modifying the memory. Program and Erase com m ands are wri tten to the Command Interface of t he memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase op eration can be de tected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 32 Kwords have been divided into four additional blocks. The 8 Kword Boot Block can be used for small initialization code to start the microprocessor , the two 4 Kword Paramet er Blocks can be used for parameter storage and the rem aining 16 Kwords are a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple conne ction to most microprocessors, often without additional logic.

The memory is offered in a TSOP40 (10 x 14mm) package and it is supplied with all the bits eras ed

(set to ’1’).

G W RP V

NC Not Connected Internally

2/20

Output Enable Write Enable Reset/Block Temporary Unprotect Supply Voltage Ground

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M29W102BT, M29W102BB

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C

BIAS

STG

(2)

Note: 1. Except for the ratin g " Operati ng Temperat ure Range" , stresses above th ose liste d i n t he Table " A bsolute M aximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in the Operating sections of this s pecification is not impli ed. Exposure to A bsolute M aximum Rating conditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Mini m um Voltage ma y undershoot to –2V duri ng transit i on and for less t han 20ns duri ng transit io ns.

Table 3. Top Boot Block Addresses M29W102BT

(KWords)

4 8 E000h-FFFFh 3 4 D000h-DFFFh 2 4 C000h-CFFFh 1 16 8000h-BFFFh 0 32 0000h-7FFFh

Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage –0.6 to 4 V Supply Voltage –0.6 to 4 V Identification Voltage –0.6 to 13.5 V

Table 4. Bottom Boot Block Addresses M29W102BB

Size

Address Range

4 32 8000h-FFFFh 3 16 4000h-7FFFh 2 4 3000h-3FFFh 1 4 2000h-2FFFh 0 8 0000h-1FFFh

Size

(KWords)

Address Range

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M29W102BT, M29W102BB

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Sign al Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A15). The Address Inputs select the cells i n the memory array to a ccess during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ15). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations DQ0-DQ7 represent the commands sent to the Command Interface of the internal state machine; the Command Interface does not use DQ8-DQ15 to decode the commands.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V

Output Enable (G

, all other pins are ignored.

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a c e .

Reset/Block Temporary Unprotect (RP

). The Re-

set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V

, for at least

. After Reset/Block Temporary Unprotect

PLPX

goes High, V Read and Bus Write operations after t or t

, whichever occurs last. See Table 15 and

PLYH

, the memory will be ready for Bus

PHEL

Figure 10, Reset/Temporary Unprotect AC Characteristics for more details.

Holding RP

at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from V t

PHPHH

to VID must be slower than

Reset/Block Temporary Unprotect can be left unconnected. A weak internal pull-up resistor ensures that the memory always operates correctly.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the L ockout Voltage, V

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power-up, power-down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor should be connected between the V

Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I

Ground. The VSS Ground is the reference for

CC3

all voltage measurements.

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M29W102BT, M29W102BB

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Wri te, Output Disable, Standby and Automatic Standby. See Table 5, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enabl e o r Write Enable are ignored by t he mem ory and do not a ffect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low sig nal, V

, to Chip Enable

and Output Enable and keeping Write Enable High, V

. The Data Inputs/Outputs will output the

value, see Figure 7, Rea d Mode AC Wav eforms, and Table 12, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desire d address on t he Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs a re latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V

, during the whole Bus

Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 13 and 14, Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . The Data Inputs/Outputs are in the high impedance s tate when Output Enable is High, V

Standby. When Chip Enable is High, V

, the

memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-

ance state. To reduce the S upply Current to the Standby Supply Current, I be held within V

± 0.2V. For the Standby current

, Chip Enable should

CC2

level see Table 11, DC Characteristics. During program or erase operations the memory

will continue to use the Program/Erase Supply Current, I

, for Program or Erase operations un-

CC3

til the operation completes. Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, I

CC2

. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protec tion. These bus operations are intended for use by programming equipment and are not usually used in applications. They require V

to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying t he signals listed in Table 5, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying P rotection and Unp rotection to M29 Series Flash.

Table 5. Bus Operations

Operation E G W Address Inputs

Bus Read Bus Write Output Disable Standby Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

X X X Hi-Z

Data

Inputs/Outp uts

V V V

Cell Address Data Output

Command Address Data Input

X Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others V A0 = VIH, A1 = VIL, A9 = VID,

Others V

or V

0099h (M29W102BT)

0098h (M29W102BB)

0020h

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M29W102BT, M29W102BB

COMMAND INTERFACE

All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The commands are summarized in Table 6, Commands. Refer to Table 6 in conjunction with the text descriptions below.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be u sed to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10

µs

to abort. During the abort period no valid data can be read from the mem ory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Man ufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select comma nd is issued the memory remains in Auto Select mode unt il another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V may be set to either V

and A1 = VIL. The other address bits

or VIH. The Manufa cturer

Code for STMicroelectronics is 0020h. The Device Code can be read using a B us Read

operation with A0 = V address bits may be set to e ither V

and A1 = VIL. The other

or VIH. The

Device Code for the M29W102BT is 0099h and the M29W102BB is 0098h.

The Block Protecti on St at us of e ac h bl ock can be read using a Bus Rea d operation with A0 = V A1 = V

, and A12-A15 specifying the add ress of

the block. The other address bits may be set to either V

or VIH. If the addressed block is protected

then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal

state machine and starts the Program/Erase Controller.

If the address falls in a pro tected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operat ion the memo ry will ignore all commands. I t is n ot poss ible t o iss ue any command to abort or pause the operation. Typical program times are given in Table 7. Bus Read operations during the program o peration will output the Status Register on the Data Inputs/Outputs. See the section on the S tatus Register for more details.

After the program operation has completed the memory will return to the Read mode, unle ss an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ bac k to ’1’. One of the E rase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are requ ired to issue the Unlock Bypass command.

Once the Unlock Bypas s command has bee n issued the memory will only accept the Unloc k Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

Unlock Bypass Program Command. The Unlock Bypass Prog ram comma nd can be used to program one address in memory at a time. The command requires two B us Write operations, the final write operation latches the address and data in the internal stat e machine and starts th e Program/Erase Controller.

The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Re set command, which l eaves the d evice in Unlo ck Bypass Mode. See the Program command for details on the behavior.

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M29W102BT, M29W102BB

Table 6. Commands

Bus Write Operations

Command

Read/Reset

Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass

Program Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal. The Com m and Inter fa ce only uses addr ess bits A0-A10 and DQ 0-DQ7 to v erify the comma nds, the upper address bits and t he upper data

bits are Do n’ t Care.

Read/Re set. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Sel ect comma nd, read Manuf acturer ID, Device ID or Block Protec tion Status. Program, Unlock Bypa ss Program, Ch ip Erase, Block Eras e. After t hese co mmands read th e Stat us Regis ter unt il the Progra m/Eras e

Controller complet e s a nd the memory returns to Read Mode. Add additio nal Blocks during Block E rase Command with add i tional Bus Write Operation s until the Timeout Bit is s et.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands

on non-era sing block s as normal. Erase Resume. After th e Er ase R esum e c omm and the s uspe nde d Eras e ope rati on re su mes , re ad th e Statu s Reg ist er u nti l the Pr ogram /

Erase Cont roller com pl etes and th e m e m ory retur ns to Read Mo de.

1X F0 3 555 AA 2AA 55 X F0

2X A0PAPD

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Unlock Bypass Reset Command. The Unlock

Bypass Reset command can be used to return t o Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.

Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protect e d th e Chip Erase op erat i on ap-

pears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 7. All Bus Read operations during the Chip E rase operation will output the Status Register on the Data Inputs/Outputs. See the section on the S tatus Register for more details.

After the Chip Erase operation has completed t he memory will return to the Read Mode, unle ss an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.

7/20

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M29W102BT, M29W102BB

Block Erase Command. The Block Erase com-

mand can be use d to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts

the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are p rotected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the Block Erase operation the me mory wi ll ignore all commands except the Erase Susp end and Read/Reset commands. Typical block erase times are given in Table 7. All Bus Read operations during the B lock E rase o peration will ou tput the Status Register on the Data Inputs/Outputs. See the section on the S tatus Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode, unle ss an error has occurred. When an error occurs the memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to reset the error condition and return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.

Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation.

The Program/Erase Controller will sus pend within 15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediate ly and wi ll start immediately when the Erase Resume Comm and is issued. It will not be possible to select any further blocks for erasure after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode.

Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.

Table 7. Program, Erase Times and Progra m , Erase Endurance Cycles

= 0 to 70°C or –40 to 85°C)

Parameter Min

Chip Erase (All bits in the memory set to ‘0’) 0.7 0.7 sec Chip Erase 1.5 1.5 9 sec Block Erase (32 Kwords) 0.8 0.8 6 sec Program 10 10 200 µs Chip Program 0.7 0.7 4 sec Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. TA = 25°C, VCC = 3.3V.

8/20

Typ

(1)

Typical after

100k W/E Cycles

(1)

Max Unit

Page 9

M29W102BT, M29W102BB

STATUS REGISTER

Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed.

The bits in the Status Register are summarized in Table 8, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed o utput DQ7, not its complement.

During Er ase ope rations the Data Polling Bit ou t-

puts ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation.

Figure 3, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.

Toggle Bit (DQ6). The Togg le Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspen d. The Toggle Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’ 1’ to ’ 0’, et c., with su ccessive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation.

Figure 4, Data Toggle Flowchart, g ives an example of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error B it is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Rese t command must be issued before other commands are issued. The E rror bit is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so may or may not set DQ5 at ’1’. In both cases, a successive Bus Read operation will show the bit is still ’0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Table 8. Status Register Bits

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2

Program Any Address DQ7

Program During Erase Suspend Any Address DQ7 Program Error Any Address DQ7 Chip Erase Any Address 0 Toggle 0 1 Toggle

Erasing Block 0 Toggle 0 0 Toggle

Block Erase before timeout

Non-Erasing Block 0 Toggle 0 0 No Toggle

Erasing Block 0 Toggle 0 1 Toggle

Block Erase

Non-Erasing Block 0 Toggle 0 1 No Toggle

Erasing Block 1 No Toggle 0 – Toggle

Erase Suspend

Non-Erasing Block Data read as normal

Good Block Address 0 Toggle 1 1 No Toggle

Erase Error

Faulty Block Address 0 Toggle 1 1 Toggle

Note: Unspecified data bi ts should be i gnored.

Toggle 0 ––

Toggle 0 – – Toggle 1 – –

9/20

Page 10

M29W102BT, M29W102BB

Figure 3. Dat a Po ll i ng Fl o wc h a rt

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

DQ5

READ DQ7

at VALID ADDRESS

DQ7

DATA

FAIL PASS

= 1

YES

AI03598

Figure 4. Dat a Toggle Flow c hart

START

READ

DQ5 & DQ6

READ DQ6

DQ6

TOGGLE

DQ5

= 1

READ DQ6

TWICE

DQ6

TOGGLE

FAIL PASS

YES

AI01370B

Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional block s to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.

Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses

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within the blocks being erased. Once t he operatio n completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will ou tput the memory cell data as if in Read mode.

After an Erase operation that c auses t he Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Re ad Operations from addresses within blocks that have not erased correctly. The Alternative Togg le Bit does not change if the addressed block has erased correctly.

Page 11

Table 9. AC Measurement Conditions

Parameter

Supply Voltage

M29W102BT, M29W102BB

M29W102B

50 70 / 90

3.0 to 3.6V 2.7 to 3.6V Load Capacitance (C Input Rise and Fall Times

)

30pF 30pF

10ns

≤

Input Pulse Voltages 0 to 3V 0 to 3V Input and Output Timing Ref. Voltages 1.5V 1.5V

Figure 5. AC Testing Input Output Waveform

1.5V

AI01417

Figure 6. AC Testing Load Circuit

0.8V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL = 30pF

10ns

OUT

CL includes JIG capacitance

Table 10. Capacitance (T

= 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit

OUT

= 0V

6pF

12 pF

OUT

Note: Sampled only, not 100% tested.

Input Capacitance Output Capacitance

AI02978

11/20

Page 12

M29W102BT, M29W102BB

Table 11. DC Characteristics

= 0 to 70°C or –40 to 85°C)

Symbol Parameter Test Condition Min

(1)

LR1

LR2

CC1

CC2

(2)

CC3

Input Leakage Current

RP Leakage Current High RP Leakage Current Low Output Leakage Current

Supply Current (Read)

Supply Current (Standby)

Supply Current (Program/Erase)

0V ≤ V

≤ V

= V

≤ V

OUT

= VIL, G = VIH,

f = 6MHz

= VCC ± 0.2V

Program/Erase

Controller active

Typ

(3)

Max Unit

±1 µA ±1 µA

–0.2 –10 µA

±1 µA

410mA

30 100 µA

20 mA

V V

LKO

Note: 1. Excludi ng the RP input.

2. Sampled only, not 100% tested.

3. T

Input Low Voltage –0.5 0.8 V

Input High Voltage

Output Low Voltage Output High Voltage Identification Voltage 11.5 12.5 V

Identification Current Program/Erase Lockout Supply

(2)

Voltage

= 25°C, VCC = 3.3V

0.7V

= 1.8mA

= –100µA VCC – 0.4

A9 = V

+ 0.3

0.45 V

100 µA

1.8 2.3 V

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Page 13

Table 12. Read AC Characteristics

= 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter Test Condition

ELQX

AVAV

AVQV

Address Valid to Next Address Valid

(1)

Address Valid to Output Valid

ACC

Chip Enable Low to Output

Transition

= VIL,

= V

= VIL,

= V

M29W102BT, M29W102BB

M29W102B

Unit

50 70 90

Min 50 70 90 ns

Max 50 70 90 ns

Min 0 0 0 ns

Chip Enable Low to Output Valid

OLZ

t t

Output Enable Low to Output Transi tion

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Chip Enable, Output Enable or Address Transition to Output

Transition

ELQV

(1)

GLQX

GLQV

(1)

EHQZ

(1)

GHQZ

EHQX

GHQX

AXQX

Note: 1. Sampled only, not 100% tested.

Figure 7. Read Mode AC Waveforms

A0-A15

tAVQV tAXQX

tAVAV

VALID

= V

= V = V

= V

Max 50 70 90 ns

Min 0 0 0 ns

Max 25 30 35 ns

Max 20 25 30 ns

Min 0 0 0 ns

DQ0-DQ15

tELQV tEHQX

tELQX tEHQZ

tGLQX tGHQX

tGLQV

tGHQZ

VALID

AI02980

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Page 14

M29W102BT, M29W102BB

Table 13. Write AC Characteristics, Write Enable Controlled

= 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter

AVAV

ELWL

WLWH

DVWH

WHDX

WHEH

WHWL

AVWL

WLAX

GHWL

WHGL

VCHEL

t t

t t t

WPH

OEH

VCS

Address Valid to Next Address Valid Min 50 70 90 ns Chip Enable Low to Write Enable Low Min 0 0 0 ns

Write Enable Low to Write Enable High Min 40 45 45 ns Input Valid to Write Enable High Min 25 30 45 ns

Write Enable High to Input Transition Min 0 0 0 ns

Write Enable High to Chip Enable High Min 0 0 0 ns

Write Enable High to Write Enable Low Min 30 30 30 ns Address Valid to Write Enable Low Min 0 0 0 ns

Write Enable Low to Address Transition Min 40 45 45 ns

Output Enable High to Write Enable Low Min 0 0 0 ns Write Enable High to Output Enable Low Min 0 0 0 ns VCC High to Chip Enable Low

M29W102B

Unit

50 70 90

Min 50 50 50 µs

Figure 8. Write AC Waveforms, Write Enable Control led

tAVAV

A0-A15

DQ0-DQ15

tAVWL

tELWL

tVCHEL

VALID

tWLWHtGHWL

tDVWH

tWLAX

tWHEH

tWHGL

tWHWL

tWHDX

VALID

AI02119

14/20

Page 15

Table 14. Write AC Characteristics, Chip Enable Controlled

= 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter

AVAV

WLEL

ELEH

DVEH

EHDX

EHWH

EHEL

AVEL

ELAX

GHEL

EHGL

VCHWL

CPH

OEH

VCS

Address Valid to Next Address Valid Min 50 70 90 ns Write Enable Low to Chip Enable Low Min 0 0 0 ns Chip Enable Low to Chip Enable High Min 40 45 45 ns Input Valid to Chip Enable High Min 25 30 45 ns Chip Enable High to Input Transition Min 0 0 0 ns Chip Enable High to Write Enable High Min 0 0 0 ns Chip Enable High to Chip Enable Low Min 30 30 30 ns Address Valid to Chip Enable Low Min 0 0 0 ns Chip Enable Low to Address Transition Min 40 45 45 ns Output Enable High Chip Enable Low Min 0 0 0 ns Chip Enable High to Output Enable Low Min 0 0 0 ns VCC High to Write Enable Low

M29W102BT, M29W102BB

M29W102B

Unit

50 70 90

Min 50 50 50 µs

Figure 9. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A15

DQ0-DQ15

tAVEL

tWLEL

tVCHWL

VALID

tELEHtGHEL

tDVEH

tELAX

tEHWH

tEHGL

tEHEL

tEHDX

VALID

AI02120

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Page 16

M29W102BT, M29W102BB

Table 15. Reset/Block Temporary Unprotect AC Characteristics

= 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter

(1)

PHWL

PHEL

(1)

PHGL

PLPX

(1)

PLYH

(1)

PHPHH

Note: 1. Sampled only, not 100% tested.

READY

VIDR

Figure 10. Reset/Block Temporary Unprotect AC Waveforms

RP High to Write Enable Low, Chip Enable

Low, Output Enable Low

RP Pulse Width Min 500 500 500 ns

Min 50 50 50 ns

RP Low to Read Mode Max 10 10 10 µs

RP Rise Time to V

Min 500 500 500 ns

M29W102B

Unit

50 70 90

E, G

tPHWL, tPHEL, tPHGL

tPLPX

tPHPHH

tPLYH

AI02943

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Page 17

M29W102BT, M29W102BB

Table 16. Ordering Information Scheme

Example: M29W102BB 70 NZ 1 T

Device Type

M29

Operating Voltage

W = V

Device Function

102B = 1 Mbit (64Kb x16), Boot Block

Array Matrix

T = Top Boot B = Bottom Boot

Speed

50 = 50 ns 70 = 70 ns 90 = 90 ns

Package

N = TSOP40: 10 x 14mm

= 2.7 to 3.6V

Temperature Range

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Note: The last two characters o f the ordering code m ay be replaced by a letter code f or preprogram m ed parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this device, please contact the ST Sales Office nearest to you.

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Page 18

M29W102BT, M29W102BB

Table 17. Revision History

Date Revision Details

August 1999 First Issue

03/09/00

Status Register bit DQ5 clarification Data Polling Flowchart diagram change (Figure 3) Data Toggle Flowchart diagram change (Figure 4)

18/20

Page 19

M29W102BT, M29W102BB

Table 18. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0 .0106

C 0.10 0.21 0.0039 0.0083

D 13.80 14.20 0.5433 0.5591 D1 12.30 12.50 0.4843 0.4921

E 9.90 10.1 0 0.3898 0.3976

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276

mm inches

N40 40 CP 0.10 0.0039

0° 5° 0° 5°

Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Outline

1 N

N/2

TSOP-a

Drawing is not to scale.

DIE

LA1 α

19/20

Page 20

M29W102BT, M29W102BB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or o therwise under any patent or patent rights of STMicroelectronics. Specifications menti oned in th i s publicati on ar e subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as c ri t i cal components in life support dev i ces or systems without express writ t en approval of STMicro el ectronics.

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