Datasheet M29W017D Datasheet (SGS Thomson Microelectronics)

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V

2.7V to 3.6V for Program, Erase and

CC =

Read

■ ACCESS TIME: 70, 90ns

■ PROGRAMMING TIME

– 10µs per Byte typical

■ 32 UNIFORM 64 KByte MEMORY BLOCKS

■ PROGRAM/ERA SE CON T ROL LER

– Embedded Byte Program algorithms

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programm ing

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ER ASE CYCL ES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: C8h

M29W017D

16 Mbit (2Mb x8, Uniform Block)

3V Supply Fl ash Me m ory

PRELIMINARY DATA

Figure 1. Packages

TSOP40 (N)

10 x 20mm

FBGA

TFBGA48 (ZA)
6 x 8 ball array

April 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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M29W017D

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 16. Block Addresses, M29W017D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

V

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SS

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Suspend Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2/36

M29W017D

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 24

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mecha nical Data . . . . . . . . 24

TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Bottom View Packag e Outline . . . . . . 25

TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Package Mec hanical Data . . . . . . . . . 25

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3/36

M29W017D

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16. Block Addresses, M29W017D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 18. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 19. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 21. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. Programmer Technique Bus Operations, BYTE = V

Figure 14. Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 16. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

or VIL . . . . . . . . . . . . . . . . . . . . . 31

IH

4/36

SUMMARY DESCRIPTION

The M29W017D is a 16 Mbit (2Mb x8) non-volatile
memory that can be read, erased and repro­grammed. These operations can be performed us­ing a single low voltage (2.7 to 3 .6V) supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.

The memory is divided into 32 blocks of 64KBytes
(see Table 16, Block Addresses) that can be
erased independently so it is pos sible to pres erve
valid data while old data is erased. Each block can
be protected independently to prev ent accidental
Program or Erase commands from modifying the
memory. Program and Erase com m ands are wri t­ten to the Command Interface of t he memory. An

process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase op eration can be de tected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.

Chip Enable, Output Enable and Write Enable sig­nals control the bus operation of the memory.
They allow simple conne ction to most m icropro­cessors, often without additional logic.

The memory is offer ed in TSOP40 (10 x 20mm) and
TFBGA48 (0.8mm pitch) pac kages. The memory is

supplied with all the bi ts erased (se t t o ’ 1’).

on-chip Program/Erase Controller simplifies the

Figure 2. Logi c D iag ram Table 1. Si gn a l Nam es

A0-A20 Address Inputs

M29W017D

A0-A20

W

RP

V

CC

21

E

G

M29W017D

V

SS

8

DQ0-DQ7

RB

AI04186

DQ0-DQ7 Data Inputs/Outputs
E
G
W
RP
RB
V

CC

V

SS

NC Not Connected Internally

Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
Ground

5/36

M29W017D

Figure 3. TSOP Connections

A16
A15
A14
A13
A12

1

40

A17
V

SS

A20
A19
A10

A11 DQ7

31
30

21

DQ6
DQ5
DQ4
V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0
G
V

SS
E
A0

A9
A8

W
RP
NC

RB

A18

A7
A6
A5
A4
A3
A2
A1

10
11

20

M29W017D

AI04187

6/36

Figure 4. TFBGA Connections (Top view through package)

M29W017D

654321

A

B

C

D

E

F

G

H

A3

A4

A2

A1

A0

E

G

V

SS

A7

A18

A6

A5 NC

DQ0

NC

NC

DQ1

RB

NC

NC

DQ2

DQ3

V

CC

NC

W

RP

NC

NC

DQ5

NC

V

CC

DQ4

A9

A8

A11

A12

A19

A10

DQ6

DQ7

A14

A13

A15

A16

A17

NC

A20

V

SS

AI04188

7/36

M29W017D

Figure 5. Block Addresses

M29W017D

Block Addresses

1FFFFFh

1F0000h

1EFFFFh

1E0000h

1DFFFFh

1D0000h

1CFFFFh

02FFFFh

020000h

01FFFFh

010000h

00FFFFh

000000h

64 KByte

64 KByte

64 KByte

Total of 32

64 KByte Blocks

64 KByte

64 KByte

64 KByte

AI05429

8/36

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Sign al
Names, for a brief overview of the signals connect­ed to this device.

Address Inputs (A0-A20). The Address Inputs
select the cells i n the memory array to a ccess dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the
Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma­chine.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op­erations to be performed. When Chip Enable is
High, V

Output Enable (G

, all other pins are ignored.

IH

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Com­mand Interf a c e.

Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that hav e b een
protected.

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

. After Reset/Block Temporary Unprotect

t

PLPX

goes High, V

, the memory will be ready for Bus

IH

Read and Bus Write operations after t
t

, whichever occurs last. See the Ready/Busy

RHEL

, for at least

IL

PHEL

or

Output section, Table 13 and Figure 13, Reset/
Temporary Unprotect AC Characteristics for more
details.

Holding RP

at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.

M29W017D

The transition from V
t

PHPHH

.

Ready/Busy Output (RB

is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
pedance during Read mode, Auto Select mode
and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be­comes high-impedance. See Tabl e 13 and Figure
13, Reset/Temporary Unprotect AC Characteris­tics .

The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.

Supply Voltage (2.7V to 3.6V). VCC pro-

V

CC

vides the power supply for all operations (Read,
Program and Erase).

The Command Interface is disabled when the V
Supply Voltage is less than the L ockout Voltage,
V

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo­ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between
the V

Supply Voltage pin and the VSS Ground

CC

pin to decouple the current surges from the power
supply. See Figure 10, AC Measurement Load Cir­cuit. T he PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I

Ground. VSS is the reference for all voltage

V

SS

measurements.

to VID must be slower than

IH

). The Ready/Busy pin

. Ready/Busy is high-im-

OL

.

CC3

CC

9/36

M29W017D

BUS OPERATIONS

There are five standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out­put Disable, Standby and Automatic Standby. See
Tables 2, Bus Operations, for a summary. Typical­ly glitches of less than 5ns on Chip Enable or Write
Enable are ignored by t he mem ory and do not a f­fect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address
Inputs, applying a Low sig nal, V
and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

IH

value, see Figure 10, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.

Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desire d address on t he Ad­dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs a re latched by the Com­mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En­able must remain High, V

IH

Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing require­ments.

Output Disa bl e . The Data Inputs/Outputs are in
the high impedance s tate when Output Enable is
High, V

.

IH

Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In­puts/Outputs pins are placed in the high-imped-

, to Chip Enable

IL

, during the whole Bus

, the

IH

ance state. To reduce the S upply Current to the
Standby Supply Current, I
be held within V

± 0.2V. For the Standby current

CC

, Chip Enable should

CC2

level see Table 9, DC Characteristics.
During program or erase operations the memory

will continue to use the Program/Erase Supply
Current, I

, for Program or Erase operations un-

CC3

til the operation completes.
Automatic Standby. If CMOS levels (V

± 0.2V)

CC

are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re­duced to the Standby Supply Current, I

CC2

. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protec tio n. These bus opera­tions are intended for use by programming equip­ment and are not usually used in applications.
They require V

to be applied to some pins.

ID

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying t he signals
listed in Tables 2, Bus Operations.

Block Protection and Blocks Unprotection.

Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.

There are two methods available for protecting
and unprotecting the blocks, one for use on pro­gramming equipment and the other for in-system
use. Block Protect and Chip Unprot ec t operat ions
are described in Appendix C.

Table 2. Bus Operations

Operation E G W

Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

10/36

V

IL

V

IL

V

IH

V

IL

V

IL

Address Inputs

A0-A20

V

IL

V

IH

V

IH

X X X Hi-Z

V

IL

V

IL

V

Cell Address Data Output

IH

V

Command Address Data Input

IL

V

X Hi-Z

IH

A0 = VIL, A1 = VIL, A9 = VID,

V

IH

Others V
A0 = VIH, A1 = VIL,

V

IH

A9 = V

or V

IL

IH

, Others VIL or V

ID

IH

Data Inputs/Outputs

DQ7-DQ0

C8h

20h

COMMAND INTERFACE

All Bus Write operations t o the me mory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return­ing to Read mode. The long command sequences
are imposed to maximize data security.

Refer to Table 3, Commands, in conjunc tion with
the following text descriptions.

Read/Reset Command. The Read/Reset com­mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other­wise stated. It also resets t he errors in the S tatus
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, be­tween Bus Write cycles before the start of a pro­gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.

Auto Select Command. The Auto Select com­mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re­quired to issue the Auto Select command. Once
the Auto Select comma nd is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.

From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V

and A1 = VIL. The other address bits

IL

or VIH. The Manufa cturer

IL

Code for STMicroelectronics is 20h.
The Device Code can be read using a B us Read

operation with A0 = V
address bits may be set to e ither V

and A1 = VIL. The other

IH

or VIH. The

IL

Device Code for the M29W017D is C8h.
The Bl ock Protection Status of each block can be

read using a Bus Read operation with A0 = V
A1 = V

, and A 16 -A 20 spec ify i n g t he address of

IH

IL

the bl ock. The oth er addr ess bit s may b e set t o ei­ther V

or VIH. If t h e ad dr ess ed b loc k is pro tec te d

IL

then 01h is output on Data Inputs/Outputs DQ0­DQ7, otherwise 00h is output.

Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re­quires four Bus Write operations, the final write op­eration latches the address and data in the internal
state machine and starts the Program/Erase Con­troller.

M29W017D

If the address falls in a pro tected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.

During the program operat ion the memo ry will ig­nore all commands. I t is n ot poss ible t o iss ue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read op­erations during the program o peration will output
the Status Register on the Data Inputs/Outputs.
See the section on the S tatus Register for more
details.

After the program operation has completed the
memory will return to the Read mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ bac k to ’1’. One of the E rase Com­mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo­ry. When the cycle time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com­mands. Three Bus Write operations are requ ired
to issue the Unlock Bypass command.

Once the Unlock Bypas s command has bee n is­sued the memory will only accept the Unloc k By­pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.

Unlock Bypass Program Command. The Un­lock Bypass Prog ra m command can be u sed to
program one address in the memory array at a
time. The command requires two Bus Write oper­ations, the final write operation latches the ad­dress and data in the internal state machine and
starts the Program/Erase Controller.

The Program operation using the Unlock Bypass

,

Program command behaves identically to the Pro­gram operation using the Program command. A
protected block cannot be programmed; the oper­ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Re set
command, which l eaves the d evice in Unlo ck By­pass Mode. See the Program command for details
on the behavior.

Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return t o
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset

11/36

M29W017D

command does not exit from Unlock Bypass
Mode.

Chip Erase Command. The Chip Erase com­mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.

If any blocks are protected th en these are ignored
and all the other blocks are erased. If all of the
blocks are protect e d th e Chip Erase op erat i on ap-

pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.

During the erase operation the memory will ignore
all commands, including the Erase Suspen d com­mand. It is not possible to i ssue any c ommand t o
abort the operation. Typical chip erase tim es are
given in Table 4. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec­tion on the Status Register for more details.

After the Chip Erase operation has completed t he
memory will return to the Read Mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un­protected blocks of the memory to ’1’. All previous
data is lost.

Block Erase Command. The Block Erase com­mand can be use d to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register sec­tion for details o n how to identify if the Program/
Erase Controller has started the Block Erase oper­ation.

If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are p rotected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un­changed. No error condition is given when protect­ed blocks are ignored.

During the Block Erase operation the me mory wi ll
ignore all commands except the Erase Susp end

command. Typical b lock era se times a re g iven in
Table 4. All Bus Read operations during the Block
Erase ope ra tion will outp ut the S t atus R e gister on
the Data Inputs/Outputs. See the section on the
Status Register for more details.

After the Block Erase operation has completed the
memory will return to the Read Mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.

Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.

The Program/Erase Controller will sus pend within
15µs of the Erase Suspend Command being is­sued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediate ly and wi ll start im­mediately when the Erase Resume Comm and is
issued. It is not possible to select any further
blocks to erase after the Erase Resume. During
Erase Suspend it is possible to Read and Program
cells in blocks that are not being erased; both
Read and Program operations beh ave as normal
on these blocks. If any attempt i s made to progra m
in a protected block or in the suspended block then
the Program command is ignored and the data re­mains unchanged. The Status Register is not read
and no error condition is given. Reading from
blocks that ar e bei n g era se d will output the Status
Register.

It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac­cepte d.

Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller after an Erase Suspend. The de­vice must be in Read Array mode before t he Re­sume command will be accepted. An erase can be
suspended and resumed more than once.

Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device i s in the Read

12/36

M29W017D

Array mode, or when the device is in Autoselected
mode.

One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is­sued subsequent Bus Read ope rations read from
the Common Flash Interface Memory Area.

The Read/Reset command m ust be issued to re­turn the device to the previous mode (the Read Ar­ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is

See Appendix B, Tables 17, 18, 19, 20, 21 and 22
for details on the information contained in the
Common Flash Interface (CFI) memory area.

Block Protect and Chip Unprot ect Commands.

Each block can be separately protected against
accidental Program or E ras e. The whole chip can
be unprotected to allow the data inside t he blo cks
to be changed.

Block Protect and Chip Unprote ct operations are
described in Appendix C.

to be put in the Read Array mode from Autoselect­ed mode.

Table 3. Commands

Bus Write Operations

Command

Read/Reset

Auto Select 3 x AA x 55 x 90
Program 4 x AA x 55 x A0 PA PD
Unlock Bypass 3 x AA x 55 x 20
Unlock Bypass

Program
Unlock Bypass Reset 2 x 90 x 00
Chip Erase 6 x AA x 55 x 80 x AA x 55 x 10
Block Erase 6+ x AA x 55 x 80 x AA x 55 BA 30

1x F0
3 x AA x 55 x F0

2x A0PAPD

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Erase Suspend 1 x B0
Erase Resume 1 x 30
Read CFI Query 1 55 98

Note: x Don’t Care, PA Progr am A ddress, PD P rogram Data, BA Any addres s in the Block. All values in the table are in hexadecim al .

13/36

M29W017D

Table 4. Program, Erase Times and Progra m, Erase Endu ran ce Cycle s

Parameter Min

Chip Erase 25 25 120 s
Block Erase (64 KBytes) 0.8 6 s
Program (Byte) 10 200 µs

Chip Program (Byte by Byte) 25 120 s
Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. TA = 25°C, VCC = 3.3V.

Typ

(1)

STATUS REGISTER

Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus­pend when an address within a block being erased
is accessed.

The bits in the Status Register are summarized in
Table 5, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera­tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.

During Program operations the Data Polling Bit
outputs the complement of the bit being pro­grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad­dress just programmed o utput DQ7, not its com­plement.

During Er ase ope rations the Data Polling Bit ou t-

puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op­eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.

Figure 6, Data Polling Flowchart, gives an exam­ple of how to use the Data Polling Bit. A Valid Ad­dress is the address being programmed or an
address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re­sponded to an Erase Suspen d. The Toggle Bit is
output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle
Bit changes from ’0’ to ’ 1’ to ’ 0’, et c., with su cces-

sive Bus Read operations at any address. After
successful completion of the operation the memo­ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.

If any attempt is made to erase a protected bl ock,
the operation is abort ed, no error is sig nalle d and
DQ6 toggles for approximately 100µs. If any at­tempt is made to program a protected block or a
suspended block, the operation is abort ed, no er­ror is signalled and DQ6 toggles for approximately
1µs.

Figure 7, Data Toggle Flowchart, g ives an exam­ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error B it is set to ’1’ when a Pro­gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Rese t command must be iss ued
before other commands are issued. The E rror bit
is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad­dress will s h ow the bit is s ti ll ‘0’. One o f t he E r as e
commands must b e used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com­mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional block s to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.

Typical after

100k W/E Cycles

(1)

Max Unit

14/36

M29W017D

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al­ternative Toggle Bit is output on DQ2 when the
Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.

During Erase Suspend the Alternative Toggle Bit

Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad­dresses within blocks not being erased will ou tput
the memory cell data as if in Read mode.

After an Erase operation that c auses t he Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er­ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Re ad Opera­tions from addresses within blocks that have not
erased correctly. The Alternative Togg le Bit does
not change if the addressed block has erased cor­rectly.

changes from ’0’ to ’1’ to ’0’, etc. with successive

Table 5. Status Register Bits

Operation Addre ss DQ7 DQ6 D Q5 DQ3 DQ2

Program Any Address DQ7 Toggle 0 ––0
Program During Erase

Suspend
Program Error Any Address DQ7
Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before
timeout

Block Erase

Erase Suspend

Any Address DQ7

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Toggle 0 – – 0

Toggle 1 – – 0

RB

Erase Error

Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

Note: Unspecif ied data bit s should be ignored.

15/36

M29W017D

Figure 6. Dat a Po ll i ng Fl o wc h a rt Figure 7. Dat a Toggle Flow c hart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

NO

DQ5

READ DQ7

at VALID ADDRESS

DQ7

DATA

FAIL PASS

= 1

YES

=

NO

YES

YES

=

NO

AI05252

START

READ

DQ5 & DQ6

READ DQ6

DQ6

=

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

TWICE

DQ6

=

TOGGLE

YES

FAIL PASS

NO

NO

AI05253

16/36

MAXIMUM RATIN G

Stressing the device ab ove the rating listed in t he
Absolute Maximum Ratings table may cause per­manent damage to the device. Exposure to Abso­lute Maximum Rating conditions for extended
periods may affect device reliability. These are

these or any other conditions above those indicat­ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and ot her relevant quality docu­ments.

stress ratings only and operation of the dev ice at

Table 6. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

T

BIAS

T

STG

V

IO

V

CC

V

ID

Note: 1. Minimum voltage ma y undershoo t t o –2V during transition and for less than 20ns during transitions.

2. Max imum voltage m ay oversho ot to V

Temperature Under Bias –50 125 °C
Storage Temperature
Input or Output Voltage

Supply Voltage –0.6 4 V
Identification Voltage –0.6 13.5 V

(1,2)

+2V during transition and less than 20ns during transitions.

CC

–65 150 °C

V

–0.6

CC

+0.6

M29W017D

V

17/36

M29W017D

DC AND AC PARAMETERS

This section summarizes t he operating m easure­ment conditions, and the DC and AC characteris­tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement

Table 7. Operating and AC Measurement Conditions

Parameter

Min Max Min Max

V

Supply Voltage

CC

Ambient Operating Temperature –40 85 –40 85 °C

Conditions summarized in Table 7, Operating and
AC Measurement Conditions. Designers should
check that the operating cond itions in their circuit
match the operating conditions when relying on
the quoted parameters.

M29W017D

3.0 3.6 2.7 3.6 V

Unit70 90

Load Capacitance (C

)

L

30 100 pF

Input Rise and Fall Times 10 10 ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages

0 to V

CC

V

/2 VCC/2

CC

0 to V

CC

Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit

V

CC

V

CC

VCC/2

0V

AI05254

CL includes JIG capacitance

DEVICE
UNDER

TEST

0.1µF

V

CC

C

L

V
V

25kΩ

25kΩ

AI05255

Table 8. Device Capacitance

Symbol Parameter Test Condition Min Max Unit

V

V

IN

OUT

= 0V

= 0V

6pF

12 pF

C

IN

C

OUT

Note: Sampled only, not 10 0% tested.

Input Capacitance
Output Capacitance

18/36

M29W017D

Table 9. DC Characteristics

Symbol Parameter Test Condition Min Max Unit

I

LI

I

LO

I

CC1

I

CC2

I

CC3

V

IL

V

IH

V

OL

V

OH

V

ID

I

ID

V

LKO

Note: 1. Sampled only, not 100% tested.

Input Leakage Current
Output Leakage Current

Supply Current (Read)

Supply Current (Standby)

(1)

Supply Current (Program/Erase)

Input Low Voltage –0.5 0.8 V

Input High Voltage
Output Low Voltage
Output High Voltage IOH = –100µA
Identification Voltage 11.5 12.5 V
Identification Current

Program/Erase Lockout Supply
Voltage

0V ≤ V

0V ≤ V

E

≤ V

IN

CC

≤ V

OUT

= VIL, G = VIH,

f = 6MHz

E

= VCC ±0.2V,

RP

= VCC ±0.2V

Program/Erase

Controller active

I

= 1.8mA

OL

A9 = V

ID

CC

±1
±1

10 mA

100

20 mA

0.7V

CC

VCC +0.3

0.45 V

V

–0.4

CC

100

1.8 2.3 V

µA
µA

µA

V

V

µA

19/36

M29W017D

Figure 10. Read AC Waveforms

A0-A20

E

G

DQ0-DQ7

tAVAV
VALID

tAVQV tAXQX

tELQV tEHQX

tELQX tEHQZ

tGLQX tGHQX

tGLQV

tGHQZ

VALID

AI05248

Table 10. Read AC Characteristics

Symbol Alt Parameter Test Condition

E

t

AVAV

t

AVQV

(1)

t

ELQX

t

ELQV

(1)

t

GLQX

t

GLQV

(1)

t

EHQZ

(1)

t

GHQZ

t

EHQX

t

GHQX

t

AXQX

Note: 1. Sampled only, not 100% tested.

t

t

ACC

t
t

t

OLZ

t
t

t

t

Address Valid to Next Address Valid

RC

Address Valid to Output Valid

Chip Enable Low to Output Transition

LZ

Chip Enable Low to Output Valid

CE

Output Enable Low to Output
Transition

Output Enable Low to Output Valid

OE

Chip Enable High to Output Hi-Z

HZ

Output Enable High to Output Hi-Z

DF

Chip Enable, Output Enable or

OH

Address Transition to Output Transition

= VIL,

G

= V

E

= VIL,

G

= V

G

= V

G

= V

= V

E

E

= V

G

= V

E

= V

IL

IL

IL

IL

IL

IL

IL

IL

M29W017D

Unit

70 90

Min 70 90 ns

Max 70 90 ns

Min 0 0 ns

Max 70 90 ns

Min 0 0 ns

Max 30 35 ns
Max 25 30 ns

Max 25 30 ns

Min 0 0 ns

20/36

Figure 11. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20

tAVWL

E

VALID

M29W017D

tWLAX

tWHEH

tELWL

G

tWLWHtGHWL

W

tDVWH

DQ0-DQ7

V

CC

RB

tVCHEL

VALID

tWHRL

Table 11. Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter

t

AVAV

t

ELWL

t

WLWH

t

DVWH

t

WHDX

t

WHEH

t

WHWL

t

AVWL

t

WLAX

t

GHWL

t

WHGL

(1)

t

WHRL

t

VCHEL

Note: 1. Sampled only, not 100% tested.

t

WC

t

t

WP

t
t

DH

t

CH

t

WPH

t
t

t

OEH

t

BUSY

t

VCS

Address Valid to Next Address Valid Min 70 90 ns
Chip Enable Low to Write Enable Low Min 0 0 ns

CS

Write Enable Low to Write Enable High Min 45 50 ns
Input Valid to Write Enable High Min 45 50 ns

DS

Write Enable High to Input Transition Min 0 0 ns
Write Enable High to Chip Enable High Min 0 0 ns
Write Enable High to Write Enable Low Min 30 30 ns
Address Valid to Write Enable Low Min 0 0 ns

AS

Write Enable Low to Address Transition Min 45 50 ns

AH

Output Enable High to Write Enable Low Min 0 0 ns
Write Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 35 ns
VCC High to Chip Enable Low

tWHGL

tWHWL

tWHDX

AI05249

M29W017D

Unit

70 90

Min 50 50 µs

21/36

M29W017D

Figure 12. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20

tAVEL

W

VALID

tELAX

tEHWH

tWLEL

G

tELEHtGHEL

E

tDVEH

DQ0-DQ7

V

CC

RB

tVCHWL

VALID

tEHRL

Table 12. Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

t

AVAV

t

WLEL

t

ELEH

t

DVEH

t

EHDX

t

EHWH

t

EHEL

t

AVEL

t

ELAX

t

GHEL

t

EHGL

(1)

t

EHRL

t

VCHWL

Note: 1. Sampled only, not 100% tested.

t

WC

t

WS

t
t
t

DH

t

WH

t

CPH

t
t

t

OEH

t

BUSY

t

VCS

Address Valid to Next Address Valid Min 70 90 ns
Write Enable Low to Chip Enable Low Min 0 0 ns
Chip Enable Low to Chip Enable High Min 45 50 ns

CP

Input Valid to Chip Enable High Min 45 50 ns

DS

Chip Enable High to Input Transition Min 0 0 ns
Chip Enable High to Write Enable High Min 0 0 ns
Chip Enable High to Chip Enable Low Min 30 30 ns
Address Valid to Chip Enable Low Min 0 0 ns

AS

Chip Enable Low to Address Transition Min 45 50 ns

AH

Output Enable High Chip Enable Low Min 0 0 ns
Chip Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 35 ns
VCC High to Write Enable Low

tEHGL

tEHEL

tEHDX

AI05250

M29W017D

Unit

70 90

Min 50 50 µs

22/36

Figure 13. Reset/Block Temporary Unprotect AC Wavefo rms

E, G

W,

tPHWL, tPHEL, tPHGL

RB

RP

tPLPX

tPLYH

Table 13. Reset/Block Temporary Unprotect AC Characteristics

Symbol Alt Parameter

(1)

t

PHWL

t

PHEL

(1)

t

PHGL

(1)

t

RHWL

(1)

t

RHEL

(1)

t

RHGL

t

PLPX

(1)

t

PLYH

(1)

t

PHPHH

Note: 1. Sampled only, not 100% tested.

t

t

t

t

READY

t

VIDR

RP High to Write Enable Low, Chip Enable Low,

RH

Output Enable Low

RB High to Write Enable Low, Chip Enable Low,

RB

Output Enable Low

RP Pulse Width Min 500 500 ns

RP

RP Low to Read Mode Max 10 10 µs

RP Rise Time to V

ID

M29W017D

tRHWL, tRHEL, tRHGL

tPHPHH

AI02931B

M29W017D

Unit

70 90

Min 50 50 ns

Min 0 0 ns

Min 500 500 ns

23/36

M29W017D

PACKAGE MECHANICAL

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

A2

Note: Drawing is not to scale.

1 N

N/2

TSOP-a

D1

DIE

E

A

D

C

e

B

CP

LA1 α

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechan ic al Data

Symbol

Typ Min Max Typ M in Max

A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413

millimeters inches

B 0.170 0.270 0.0067 0.0106

C 0.100 0.21 0 0.0039 0.0083

D 1 9.800 20.200 0.7795 0.7953
D1 18.30 0 18.500 0.7205 0.7283

E 9.900 10.100 0.3898 0.3976

e 0 .500 – – 0.0197 – –

L 0.500 0.70 0 0.0197 0.0276

α

0° 5° 0° 5°

N40 40

CP 0.100 0.0039

24/36

M29W017D

TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Bottom View Package Ou tline

D

FD

FE

D1

SD

SE

ddd

A2

A1

BGA-Z14

BALL "A1"

Note: Drawing is not to scale.

E1E

eb

A

TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Pack age Mechan i cal Data

Symbol

Typ Min Max Typ Min Max

A 1.350 0.0531
A1 0 .300 0.200 0.350 0.0118 0.0079 0.0138
A2 1.000 0.0394

b 0.30 0 0.550 0.0118 0.0217

D 8.000 7.900 8 .100 0.3150 0.3110 0.3189

millimeters inches

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

e 0.800 – – 0.031 5 – –

E 9 .000 8.900 9.100 0.3543 0.3504 0.3583
E1 5 .600 – – 0.2205 – –

FD 2.000 – – 0.0787 – –
FE 1.700 – – 0.0669 – –
SD 0 .400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –

25/36

M29W017D

PART NUMBERING

Table 14. Ordering Information Scheme

Example: M29W017D 90 N 1 T

Device Type

M29

Operating Voltage

W = V

Device Function

017D = 16 Mbit (x8), Uniform Block

Speed

70 = 70 ns
90 = 90 ns

Package

N = TSOP40: 10 x 20 mm
ZA = TFBGA48: 0.80mm pitch

= 2.7 to 3.6V

CC

Temperature Range

1 = 0 to 70 °C
6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the ST Sales Office nearest to you.

REVISION HIST ORY

Table 15. Document Revision History

Date Version Revision Details

May-2001 -01 First Issue (Brief Data)

18-Jun-2001 -02 Document expanded to full Product Preview, TFBGA Package Mechanical changed.

26-Jul-2001 -03 Document type: from Product Preview to Preliminary Data

03-Dec-2001 -04 Block Protection Appendix added, Read/Reset operation during Erase Suspend clarified .

05-Apr-2002 -05

Description of Ready/Busy signal clarified (and Figure 13 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section

26/36

APPENDIX A. BLOCK ADDRESS TABLE

M29W017D

Table 16. Block Addresses, M29W017D

#

31 64 1F0000h-1FFFFFh
30 64 1E0000h-1EFFFFh
29 64 1D0000h-1DFFFFh
28 64 1C0000h-1CFFFFh
27 64 1B0000h-1BFFFFh
26 64 1A0000h-1AFFFFh
25 64 190000h-19FFFFh
24 64 180000h-18FFFFh
23 64 170000h-17FFFFh
22 64 160000h-16FFFFh
21 64 150000h-15FFFFh
20 64 140000h-14FFFFh
19 64 130000h-13FFFFh
18 64 120000h-12FFFFh
17 64 110000h-11FFFFh
16 64 100000h-10FFFFh

Size

(KBytes)

Address Range

#

15 64 0F0000h-0FFFFFh
14 64 0E0000h-0EFFFFh
13 64 0D0000h-0DFFFFh
12 64 0C0000h-0CFFFFh
11 64 0B0000h-0BFFFFh
10 64 0A0000h-0AFFFFh

9 64 090000h-09FFFFh
8 64 080000h-08FFFFh
7 64 070000h-07FFFFh
6 64 060000h-06FFFFh
5 64 050000h-05FFFFh
4 64 040000h-04FFFFh
3 64 030000h-03FFFFh
2 64 020000h-02FFFFh
1 64 010000h-01FFFFh
0 64 000000h-00FFFFh

Size

(KBytes)

Address Range

27/36

M29W017D

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap­proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to det ermine
various electrical and t iming parameters, density
information and functions supported by the mem­ory. The system can interface easily with the de­vice, enabling the software to upgrade itself when
necessary.

When the CFI Query Command is issued the de­vice enters CFI Query mode and the data structure

Table 17. Query Structure Overvi ew

Address Sub-section Name Description

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

is read from the memory. Tables 17, 18, 19, 20, 21
and 22 show the address es used to retrieve the
data.

The CFI data structure also contains a security
area where a 64 bit unique security number is writ­ten (see Table 22, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change t he secu rity num­ber after it has been written by ST. Issue a Read/
Reset command to return to Re ad mode.

40h

61h Security Code Area 64 bit unique device number

Note: Query data are always presented on the lowest order data outputs.

Primary Algorithm-specific Extended Query
table

Additional information specific to the Primary
Algorithm (optio nal)

Table 18. CFI Query Identification String

Address Data Description Value

10h 51h "Q"
11h 52h Query Unique ASCII String "QRY" "R"
12h 59h "Y"
13h 02h
14h 00h
15h 40h
16h 00h
17h 00h
18h 00h
19h 00h

1Ah 00h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 20) P = 40h

Alternate Vendor Command Set and Control Interface ID Code second vendor

- specified algorithm supported

Address for Alternate Algorithm extended Query table

AMD

Compatible

NA

NA

28/36

M29W017D

Table 19. CFI Query System Interface Information

Address Data Description Value

V

Logic Supply Minimum Program/Erase voltage

1Bh 27h

1Ch 36h

1Dh 00h

1Eh 00h
1Fh 04h

20h 00h
21h 0Ah
22h 00h
23h 04h
24h 00h
25h 03h
26h 00h

CC

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV

Logic Supply Maximum Program/Erase voltage

V

CC

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV

V

[Programming] Supply Minimum Program/Erase voltage

PP

V

[Programming] Supply Maximum Program/Erase voltage

PP

n

Typical timeout per single byte/word program = 2

µs

Typical timeout for minimum size write buffer program = 2

ms

n

ms

n

times typical

n

times typical

n

times typical

Typical timeout per individual block erase = 2
Typical timeout for full chip erase = 2

n

Maximum timeout for byte/word program = 2
Maximum timeout for write buffer program = 2
Maximum timeout per individual block erase = 2
Maximum timeout for chip erase = 2

n

times typical

n

µs

2.7V

3.6V

NA
NA

16µs

NA

1s

NA

256µs

NA

8s

NA

Table 20. Device Geometry Definition

Address Data Description Value

27h 15h
28h

29h

2Ah
2Bh

00h
00h

00h
00h

2Ch 01h

2Dh
2Eh

2Fh
30h

1Fh
00h

00h
01h

n

Device Size = 2

in number of bytes

Flash Device Interface Code description

n

Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.

Region 1 Information
Number of identical size erase block = 001Fh+1

Region 1 Information
Block size in Region 1 = 0100h * 256 byte

2 MByte

Async.

64 KByte

x8

NA

1

32

29/36

M29W017D

Table 21. Primary Algorithm-Sp ecific Extend ed Qu ery Ta ble

Address Data Description Valu e

40h 50h

"P"
41h 52h "R"
42h 49h "I"
43h 31h Major version number, ASCII "1"
44h 30h Minor version number, ASCII "0"
45h 01h Address Sensitive Unlock (bits 1 to 0)

46h 02h Erase Suspend

47h 01h Block Protection

48h 01h Temporary Block Unprotect

49h 04h Block Protect /Unprotect

4Ah 00h Simultan eous Operati ons, 00 = not supporte d No
4Bh 00h Burst Mode, 00 = not supported, 01 = supported No
4Ch 00h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No

Primary Algorithm extended Query table unique ASCII string “PRI”

00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)

00 = not supported, 01 = Read only, 02 = Read and Write

00 = not supported, x = number of blocks per group

00 = not supported, 01 = supported

04 = M29W400B mode

Table 22. Security Code Area

Address Data Description

61h XX
62h XX
63h XX
64h XX
65h XX
66h XX
67h XX
68h XX

64 bit: unique device number

No

2

1

Yes

4

30/36

APPENDIX C. BLOCK PROTECTION

Block protection can be used to prevent any oper­ation from modifying the data s tored in the Flash.
Each Block can be protected individually. Once
protected, Program and Erase operations on the
block fail to change the data.

There are three techniques that can be used to
control Block Protection, these are the Program­mer technique, the In-System technique and Tem­porary Unprotection. Temporary Unprotection is
controlled by the Reset/B lock Temporary Unpro­tection pin, RP

; this is described in the Signal De-

scriptions section.
Unlike the Command Interface of the Program/

Erase Controller, the techniques for protecting and
unprotecting blocks change between different
Flash memory suppliers. For example , the tech­niques for AMD parts will not work on STMicro­electronics parts. Care should be taken when
changing drivers for one part to work on another.

Programm er Technique

The Programmer techniq ue uses high (V

) volt-

ID

age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended on ly for
use in Programming Equipment.

To protect a block follow the flowchart in Figure 14,
Programmer Equipment Block Prot ect Flowchart.
To unprotect the whole chip it is necessary to pro­tect all of the blocks f irst, then all blocks can be un­protected at the same time. To unprotect the chip
follow Figure 15, Programmer Equipment Chip
Unprotect Flowchart. Table 23, Programmer

M29W017D

Technique Bus Operations, gives a summary of
each operation.

The timing on these flowcharts is critical. Care
should be taken to en sure that, where a pau se is
specified, it is followed as closely as possible. Do
not abort the procedure be fore reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.

In-System Technique

The In-System technique requires a high volt age
level on the Reset/Blocks Temporary Unprotect
pin, RP
maximum ratings of the components on the micro­processor bus, therefore this technique is suitable
for use after the Flash has been fitted to the sys­tem.

To protect a block follow the flowchart in Figure 16,
In-System Block Protect Flowchart. To unprotect
the whole chip it is ne cessary to protect all of the
blocks first, then all the blocks can be unprotected
at the same time. To unprotect the chip follow Fig­ure 17, In-System Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care
should be taken to en sure that, where a pau se is
specified, it is followed as closely as possible. Do
not allow the microprocessor to s ervice interrupts
that will upset the timing and do not abort the pro­cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.

. This can be achieved without violating the

Table 23. Programmer Technique Bus Op erati ons , BYTE

Operation E G W

Block Protect

Chip Unprotect

Block Protection
Verify

Block Unprotection
Verify

V

IL

V

IDVIDVIL

V

IL

V

IL

VIDVIL Pulse

Pulse

V

V

V

IL

IL

IH

V

IH

A9 = V

A0 = VIL, A1 = VIH, A6 = VIL, A9=VID,

A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

Address Inputs

A0-A20

, A12-A20 Block Address

ID

Others = X

A9 = V

, A12 = VIH, A15 = VIH

ID

Others = X

A12-A20 Block Address

Others = X

A12-A20 Block Address

Others = X

= VIH or V

IL

Data Inputs/Outputs

DQ15A–1, DQ14 -DQ0

X

X

Pass = XX01h

Retry = XX00h

Retry = XX01h

Pass = XX00h

31/36

M29W017D

Figure 14. Programmer Equipment Block Protect Flowchart

START

ADDRESS = BLOCK ADDRESS

W = V

IH

n = 0

G, A9 = VID,

E = V

IL

Wait 4µs

W = V

IL

Wait 100µs

Verify Protect Set-upEnd

W = V

IH

E, G = VIH,

A0, A6 = VIL,

A1 = V

IH

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

YES

A9 = V

IH

E, G = V

IH

PASS

NO

++n
= 25

A9 = V

E, G = V

NO

YES

IH

IH

32/36

FAIL

AI03469

Figure 15. Programmer Equipme nt Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

M29W017D

CURRENT BLOCK = 0

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = V

n = 0

A6, A12, A15 = V

E, G, A9 = V

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

E = V

IL

Wait 4µs

(1)

IH

ID

IH

Verify Unprotect Set-upEnd

G = V

IL

Wait 60ns

Read DATA

=

00h

YESNO

DATA

++n

NO

= 1000

YES

A9 = V

IH

E, G = V

IH

FAIL PASS

CURRENT BLOCK

LAST

BLOCK

YES

A9 = V

IH

E, G = V

IH

INCREMENT

NO

AI03470

33/36

M29W017D

Figure 16. In-System Equipment Block Protect Flowchart

START

n = 0

RP = V

ID

Verify Protect Set-upEnd

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

Wait 100µs

WRITE 40h

A0 = VIL, A1 = VIH, A6 = V

Wait 4µs

READ DATA

DATA

RP = V

=

01h

NO

YES

IH

IL

IL

IL

IL

++n

= 25

NO

34/36

ISSUE READ/RESET

COMMAND

PASS

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

AI03471

Figure 17. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

M29W017D

Verify Unprotect Set-upEnd

CURRENT BLOCK = 0

A0 = VIL, A1 = VIH, A6 = V

A0 = VIL, A1 = VIH, A6 = V

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = V

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = V

n = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

WRITE 60h

ANY ADDRESS WITH

Wait 10ms

WRITE 40h

Wait 4µs

READ DATA

IH

IH

IH

IH

INCREMENT

CURRENT BLOCK

++n

NO

= 1000

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

DATA

=

00h

YESNO

LAST

BLOCK

RP = V

ISSUE READ/RESET

COMMAND

PASS

NO

YES

IH

AI03472

35/36

M29W017D

Information furnished is believed to be ac curate and reli able. Howev er, STMicroel ectronics assumes no responsibilit y for the consequence s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout express written ap proval of STMi croelect ro nics.

The ST log o i s registered trademark of STMicroelectronics
All other nam es are the pro perty of their respective owners

© 2002 STMicroelectronics - All Rights Reserved

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36/36