Datasheet M29W008AT120N1, M29W008AT, M29W008AB120N6T, M29W008AB120N6, M29W008AB120N1 Datasheet (SGS Thomson Microelectronics)

1/30March 2000

M29W008AT

M29W008AB

8 Mbit (1Mb x8, Boot Block)

Low Voltage Single Supply Flash Memory

■ 2.7V to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERAS E and READ O PER AT IONS

■ ACCESS TIME: 80ns

■ PROGRAMMING TIME: 10µs typical

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output

■ SECURITY PROTECTION MEMORY AREA

■ INSTRUCTIONS ADDRESS CODING: 3 digits

■ MEMORY BLOCKS

– Boot Block (Top or Bottom location)
– Parameter and Main blocks

■ BLOCK, MULTI-BLOCK and CHIP ERASE

■ MULTI BLOCK PROTECTION/TEMPO R ARY

UNPROTECTION MODES

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ LOW POWER CONSUMPTION

– Stand-by and Automatic Stand-by

■ 100,000 PROGRAM/ER ASE CYCL ES per

BLOCK

■ 20 YEARS DATA RETENTI ON

– Defectivity below 1ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Top Device Code, M29W008AT: D2h
– Bottom Device Code, M29W008AB: DCh

Figure 1. Logic Diagram

AI02716

20

A0-A19

W

DQ0-DQ7

V

CC

M29W008AT
M29W008AB

E

V

SS

8

G

RP

RB

TSOP40 (N)

10 x 20mm

M29W008AT, M29W008AB

2/30

Figure 2. TSOP Connection s

V

SS

DQ1

DQ2A7

A1

E

A4
A3

A11

A17

A14

A15

DQ7

A9

A16

G

NC

DQ5

DQ3

NC

V

CC

DQ4

DQ6

A8

W

RB

A18

NC

RP

AI02717

M29W008AT
M29W008AB

10

1

11

20 21

30

31

40

A0

A12

A13

A19
A10

A5

A6

V

CC

DQ0

V

SS

A2

Table 1. Signal Names

A0-A19 Address Inputs

DQ0-DQ7 Data Input/Outputs, Command Inputs
E

Chip Enable

G

Output Enable

W

Write Enable

RP

Reset/Block Temporary Unprotect

RB

Ready/Busy Output

V

CC

Supply Voltage

V

SS

Ground

NC Not Connected Internally

Organisation

The M29W008A is organised as 1Mb x8. The
memory uses the addre ss inputs A0-A 19 and the
Data Input/Outputs DQ0-DQ7. Memory c ontrol is
provided by Chip Enable E

, Output Enable G and

Write Enable W

inputs.

A Reset/Block Temporary Unprotection RP

tri-lev­el input provides a hardware reset when pulled
Low, and when held High (at V

ID

) temporarily un­protects bl ocks previo usly protecte d allowin g them
to be programed an d eras ed. E ras e and P rogram
operations are controlled by an internal Program/
Erase Controller (P/E.C.). Status Register data
output on DQ7 provides a Data Polling signal, and
DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C opera tions. A Ready/Busy
RB

output indicates the completion of the internal

algorithms.

Memory Blocks

The devices feature asymmetrically blocked archi­tecture providing system memory integration. Both
M29W008AT and M29W0 08AB devices have an
array of 19 blocks, one Boot Block of 16 Kbytes,
two Parameter Blocks of 8 Kbytes, one Main Block
of 32 Kbytes and fifteen Main Blocks of 64 Kbytes.
The M29W008AT has the Boot Block at the top of
the memory address space and the M29W008AB
locates the Boot Block s tar ting at t he bot tom. The
memory maps are showed i n Tables 3, 4. Each
block can be e rased sepa rately, any combi nation
of blocks can be specified for mult i-block erase or
the entire chip may be erased . The Erase opera­tions are managed automatically by the P/E.C.

DESCRIPTION

The M29W008A is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V V

CC

supply. For
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.

The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Bl ocks can be pro tected a gainst pro ­graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.

Instructions for Read/Reset, Auto Select for read­ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase,
Erase Suspend and Resume are written to the de­vice in cycles of comm ands to a Command Inter­face using standard microprocessor write timings.
The device is offered in TSOP40 (10 x 20mm)
package.

3/30

M29W008AT, M29W008AB

Instructions

Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signa­ture or Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and Erase Re­sume. The internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Regist er Data Poll­ing, Toggle, Error bits and the RB

output may be
read at any time, during programming or erase, to
monitor the progress of the operation.

Instructi ons a re co mpose d of up to si x cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in­structions (s ee Tab le 9). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In or­der to give additional data protection, the instruc­ti ons f or Pr ogram an d Block or Chip Eras e requir e
further command inputs. For a Program instruc­tion, the fourth command cycle inputs the address
and data to be programmed. For an Erase instruc­tion (Block or Chip), the fourth and fifth cycles in­put a further Coded sequence before the Erase
confirm command on the sixt h cy cle. Erasure of a
memory block may be suspended, in order to read
data from another block or to program d ata in an­other block, and then resumed.

When power is first applied or if V

CC

falls below V

L-

KO

, the command interface is reset to Read Array.

The block erase operation can be s uspended in
order to read from or program to any block not be­ing erased, and then resumed.

Block protection provides additional data security.
Each block can be s eparately prot ec ted or unpro­tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.

Bus Operations

The following operations can be performed using
the appropriate bus cycles: Read (Array, Electron­ic Signature, Block Protection Status ), W rite com­mand, Output Disable, Stand-by, Reset, Block
Protection, Unprotection, Protection Verify, Unpro­tection Verify and Block Temporary Un protection.
See Tables 5 and 6.

Command Interface

Instructions, made up of commands wri tten in cy­cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded c ycles to the
C.I. This Coded sequence is the same for all Pro­gram/Erase Controller instructions. The ’Com­mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se­quence will reset the device to Read Array mode.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating "Operating Temperature Range", s tresses above thos e l i sted in the Table "A bsolute M aximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in the Operating sections of this s pecification is not impli ed. Exposure to A bsolute M aximum Rating condi­tions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ­ity docum en ts .

2. Mini m um Voltage ma y undershoot to –2V duri ng transit i on and for less t han 20ns duri ng transit io ns.

3. Depends on range.

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature

(3)

–40 to 85 °C

T

BIAS

Temperature Under Bias –50 to 125 °C

T

STG

Storage Temperature –65 to 150 °C

V

IO

(2)

Input or Output Voltage –0.6 to 5 V

V

CC

Supply Voltage –0.6 to 5 V

V

(A9, E , G, RP)

(2)

A9, E, G, RP Voltage –0.6 to 13.5 V

M29W008AT, M29W008AB

4/30

Table 3. Top Boot Block Addresses,
M29W008AT

#

Size

(Kbytes)

Address Range

18 16 FC000h-FFFFFh
17 8 FA000h-FBFFFh
16 8 F8000h-F9FFFh
15 32 F0000h-F7FFFh
14 64 E0000h-EFFFFh
13 64 D0000h-DFFFFh
12 64 C0000h-CFFFFh
11 64 B0000h-BFFFFh
10 64 A0000h-AFFFFh

9 64 90000h-9FFFFh
8 64 80000h-8FFFFh
7 64 70000h-7FFFFh
6 64 60000h-6FFFFh
5 64 50000h-5FFFFh
4 64 40000h-4FFFFh
3 64 30000h-3FFFFh
2 64 20000h-2FFFFh
1 64 10000h-1FFFFh
0 64 00000h-0FFFFh

Table 4. Bottom Boot Block Addresses,
M29W008AB

#

Size

(Kbytes)

Address Range

18 64 F0000h-FFFFFh
17 64 E0000h-EFFFFh
16 64 D0000h-DFFFFh
15 64 C0000h-CFFFFh
14 64 B0000h-BFFFFh
13 64 A0000h-AFFFFh
12 64 90000h-9FFFFh
11 64 80000h-8FFFFh
10 64 70000h-7FFFFh

9 64 60000h-6FFFFh
8 64 50000h-5FFFFh
7 64 40000h-4FFFFh
6 64 30000h-3FFFFh
5 64 20000h-2FFFFh
4 64 10000h-1FFFFh
3 32 08000h-0FFFFh
2 8 06000h-07FFFh
1 8 04000h-05FFFh
0 16 00000h-03FFFh

5/30

M29W008AT, M29W008AB

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs

for the memory array are latched during a write op­eration on the falling edge of Chip Enable E

or

Write Enable W

. When A9 is raised to VID, either a
Read Electronic Signature Manufacturer or Device
Code, Block Protection Status or a Write Block
Protection or Block Unprotection is enabled de­pending on the combinat ion of levels on A0, A1
A6, A12 and A15.

Data Input/Outputs (DQ0-DQ7). The input is
data to be programm ed in the memory array or a
command to be written to the C.I. Both are latched
on the rising edge of Chip Enable E or Write E n­able W

. The output is data from the Memory Array,
the Electronic Signature Manufa cturer or Device
codes, the Block Prote ction Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E

and

Output Enable G

are active. The output is high i m­pedance when the chip is deselected or the out­puts are disabled and when RP

is at a Low level.

Chip Enable (E

). The Chip Enable input acti-

vates the memory control logic, input buffers, de­coders and sense amplifiers. E

High deselects the
memory and reduces the power consumption to
the stand-by level. E

can also b e used to control
writing to the command register and to the memo­ry array, while W

remains at a low le v el. The Chip

Enable must be forced to V

ID

during the Block Un-

protection operation.

Output Enable (G

). The Output Enable gates the

outputs through the data buffers during a read op­eration. When G

is High the outpu ts are High im-

pedance. G

must be forced to VID level during

Block Protection and Unprotection operations.

Write Enable (W

). This input controls writing to

the Command Register and Address and Data
latches.

Ready/Busy Output (RB

). Ready/Busy is an

open-drain output and gives the internal state of
the P/E.C. of the device. When RB

is Low, the de­vice is Busy with a Program or Erase operation
and it will not accept any additional program or
erase instructions except the Erase Suspend in­struction.

When RB

is High, the device is ready for any

Read, Program or Erase operation. The RB

will
also be High when the memory is put in Erase
Suspend or Stand-by modes.

Reset/Block Temporary Unprotect Input (RP

).

The RP

Input provides hardware reset and pro­tected block(s) temporary unprotection functions.
Reset of the memory is achieved by pulling RP

to

V

IL

for at least t

PLPX

. When the reset pulse is giv­en, if the memory is in Read or Stand-by modes, it
will be available for new operations in t

PHEL

after

the rising edge of RP

.

If the memory is in Erase, Erase Suspend or Pro­gram modes the reset will take t

PLYH

during which

the R B

signal will be held at VIL. The end of the
memory re set will be indicate d by the risi ng edge
of RB

. A hardware reset d uring an Erase or Pro­gram operation will corrupt the data being pro­grammed or the sector(s) being erased. See
Tables 15, 16 and Figure 8.

Temporary block unprotection is made by holding
RP

at VID. In this condi tion previously pro tected
blocks can be programmed or erased. The transi­tion o f RP

from VIH to VID must slower than t

PH-

PHH

. (See Tables 17, 18 and Figure 8). When RP
is returned from VID to VIH all blocks temporarily
unprotected will be again protected.

V

CC

Supply Voltage. The power supply for all

operations (Read, Program and Erase).

V

SS

Ground. VSS is the reference for all voltage

measurements.

M29W008AT, M29W008AB

6/30

DEVICE OPERATIONS

See Tables 5, 6 and 7.
Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig­nature, the Status Register or the Block Protection
Status. Both Chip Enab le E

and Output Enable G
must be low in order to read the output of the mem­ory. A new read operation is initiated either on the
falling edge of Chip, Enable E

, or on any address

transition with E

at VIL.

Write. Write operations are used to give I nstruc­tion Commands to the memory or to latch input
data to be programmed. A write operation is initi­ated when Chip Enable E

is Low and Write Enable

W

is Low with Output E nable G High. Addresses

are latched on the falling edge of W

or E whichever
occurs last. Commands and Input Data are
latched on the rising edge of W

or E whichever oc-

curs first.
Output Disa bl e . The data outputs are high im-

pedance when the Output Enable G

is High with

Write Enable W

High.

Stand-by. The memory is in stand-by wh en Chip
Enable E

is High and the P/E.C. is idle. The power
consumption is reduced to the st and-by level and
the outputs are high impedanc e, independent of
the Output Enable G

or Write Enable W inputs.

Automatic Stand-by. After 150ns of bus inactivi­ty (no address transition, E

= VIL) and when CMOS
levels are driving the addresses, the chip automat­ically enters a pseudo-stand-by mode where con­sumption is reduced to the CMOS stand-by value,
while outpu t s still d riv e th e bu s (if G

= VIL).

Electronic Signature. Tw o codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for STMicro­electronics is 20h, the device code is D2h for the
M29W008AT (Top Boot) and DCh for the
M29W008AB (Bottom Boot). These codes allow
programming equipment or applications to auto­matically match their interface to the characteris­tics of the M29W008A. The Electronic Signature is
output by a Read operation when the voltage ap­plied to A9 is at V

ID

and address inputs A1 is Low.
The manufacturer code is output when the Ad­dress input A0 is Low a nd the device code when
this input is High. Other Address inputs are ig­nored. The Electronic Signature can also be read,
without raising A9 to V

ID

, by giving the memory the

Instructi on AS.

Block Protection. Each block c an be separately
protected against Program or Erase on program ­ming equipment. Block protection provid es addi­tional data security, as it disables all program or
erase operations. This mode is activated when
both A9 and G

are raised to VID and an address in
the block is applied on A13-A1 9. Block protection
is initiated on the edge of W

falling to VIL. Then af-

ter a delay of 100µs, the edge of W

rising to V

IH

ends the protection operations. Block protection
verify is achieved by bringing G

, E, A0 a nd A6 t o

V

IL

and A1 to VIH, while W is at VIH and A9 at VID.
Under these conditions, reading the data output
will yield 01h if the block def ined by the inputs on
A13-A19 is protected. Any at tempt to program or
erase a protected block will be ignored by the de­vice .

Block Temporary Unprotection. Any previously
protected block can be temporaril y unprotec ted in
order to change stored data. The tem porary un­protection mode is activated by bringing RP to VID.
During the temporary unprotection mode the pre­viously protected blocks a re unprotected. A block
can be selected and data can be modified by exe­cuting the Erase or Program instruction with the
RP

signal held at VID. When RP is returned to VIH,
all the previously protected blocks are again pro­tected.

Block Unprotection. All protected blocks can be
unprotected on programming equ ipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G

and E are at

V

ID

and A12, A15 at VIH. Unprote ction is init iated

by the edge of W

falling t o VIL. After a delay of
10ms, the unprotection operation will end. Unpro­tection verify is achieved by bringing G

and E to

V

IL

while A0 is at VIL, A6 and A1 are at VIH and A9

remains at V

ID

. In these conditions, reading the
output data will yield 00h if the block defined by the
inputs A13-A19 has been s uccessfully unprotect­ed. Each block must be separately verified by giv­ing its address in order to ensure that it has been
unprotected.

7/30

M29W008AT, M29W008AB

Table 5. User Bus Operations

(1)

Note: 1. X = VIL or VIH.

2. Block Address m ust be given an A13-A19 bi ts.

3. See Table 7.

4. Oper atio n pe rform ed on pro g ramming equipment.

Table 6. Read Electronic Signature (following AS instruction or with A9 = VID)

Table 7. Read Block Protection with AS Instruction

Operation E G W RP A0 A1 A6 A9 A12 A15 DQ0-DQ7

Read Byte

V

IL

V

IL

V

IH

V

IH

A0 A1 A6 A9 A12 A15 Data Output

Write Byte

V

IL

V

IH

V

IL

V

IH

A0 A1 A6 A9 A12 A15 Data Input

Output Disable

V

IL

V

IH

V

IH

V

IH

XXXXXX Hi-Z

Stand-by

V

IH

XX

V

IH

XXXXXX Hi-Z

Reset X X X

V

IL

XXXXXX Hi-Z

Block
Protection

(2,4)

V

IL

V

ID

VIL Pulse V

IH

XXX

V

ID

XX X

Blocks
Unprotection

(4)

V

ID

V

ID

VIL Pulse V

IH

XXX

V

ID

V

IH

V

IH

X

Block
Protection

Verify

(2,4)

V

IL

V

IL

V

IH

V

IH

V

IL

V

IH

V

IL

V

ID

A12 A15

Block

Protect

Status

(3)

Block
Unprotection

Verify

(2,4)

V

IL

V

IL

V

IH

V

IH

V

IL

V

IH

V

IH

V

ID

A12 A15

Block

Protect

Status

(3)

Block
Temporary
Unprotection

XX X

V

ID

XXXXXX X

Code Device E

G W A0 A1

Other

Addresses

DQ0-DQ7

Manufact. Code

V

IL

V

IL

V

IH

V

IL

V

IL

Don’t Care 20h

Code E

G W A0 A1 A13-A19

Other

Addresses

DQ0-DQ7

Protected Block

V

IL

V

IL

V

IH

V

IL

V

IH

Block Address Don’t Care 01h

Unprotected Block

V

IL

V

IL

V

IH

V

IL

V

IH

Block Address Don’t Care 00h

M29W008AT, M29W008AB

8/30

Table 8. Commands

Hex Code Command

00h Invalid/Reserved
10h Chip Erase Confir m
20h Rese r ved
30h Block Erase Resume/Confirm
80h Set-up Erase

90h

Read Electronic Signature/

Block Protection Status
A0h Program
B0h Erase Suspend
F0h Read Array/Reset

INSTRUCTIONS AND COMMANDS

The Command Interface latches c ommands writ­ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Pro­tection, Program, Block Erase, Chip E rase, Eras e
Suspend and Erase Resume. Commands are
made of address and data sequences. The in­structions require from 1 to 6 cycles, the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirm the first command or
execute the command immediately. Command se­quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increase d number of cycles has
been chosen to assure maximum data security. In­structions are initialised by two initial Coded cycles
which unlock the Command Interface. In addition,
for Erase, instruction confirmation is again preced­ed by the two Coded cycles.

Status Register Bits

P/E.C. status is indicated during execution by Data
Polling on D Q7, detection of T oggle on DQ6 and
DQ2, or Error on DQ5 and E ras e T imer DQ3 bits.
Any read attempt during P rogram or Erase com­mand execution will automatically output these
five Status Register bits. The P/E.C. automatically
sets bits DQ2, DQ 3, DQ5, DQ6 and DQ7. Other
bits (DQ0, DQ1 and D Q4) a re reserved for future
use and should be masked. See Tables 10 and 11.

Data Polling Bit (DQ7). When Program ming op­erations are in progress, this bit out puts the com­plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com­pletion of the operation, DQ7 will output the bit last
program me d or a ’1 ’ after er asi ng. Data Pollin g is
valid and only effective during P/E.C. operation,
that is after the fourth W

pulse for programming or

after the sixth W

pulse for erase. It must be per­formed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will

be set to '0' for about 100µs, and then return to the
previous addressed memory data value. See Fig­ure 10 for the D ata P olling flowcha rt a nd F igure 9
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from '0' to

'1' at the start of the Erase Suspend. In order to
monitor DQ7 in t he Erase Sus pend mode an ad­dress within a block being erased must be provid­ed. For a Read Operation in Erase Suspend
mode, DQ7 will output '1' if the read is attempted
on a block being erased and the data value on oth­er blocks. During Program operation in Erase Sus­pend Mode, DQ7 will have the same behavior as
in the normal program execution outside of the
suspend mode.

Toggle Bit (DQ6). When Programming or Eras­ing operations are in progress, successive at­tempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G

,

or E

when G is low. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last pro­grammed or a '1' after erasing. The toggle bit DQ6
is valid only during P/E.C. op erations, that is after
the fourth W

pulse for programming or after the

sixth W

pulse for Erase. If the blocks selected for
erasure are protected, DQ6 will toggle for about
100µs and then return ba ck to Read. DQ6 will be
set to '1' if a Read operation is at tempted on an
Erase Suspend block. When erase is suspended
DQ6 will toggle during programming operations in
a block different to the block in Erase Suspend. Ei­ther E

or G toggling will cause DQ6 to toggle. See
Figure 11 for Toggle Bit flowchart and Figure 12
for Toggle Bit wav e f o r m s .

9/30

M29W008AT, M29W008AB

Table 9. Instructions

(1)

Note: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of t

PLYH

is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new

operation (see Tables 15, 16 and Figur e 9).

3. X = Don’t Car e.

4. The f i rst cycle s of the RD or AS instruction s are follo wed by read operati ons. Any number of read cycles can occ ur after the com­mand cycl e s.

5. Signature Addr ess bits A0, A 1, a t V

IL

will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will out put De vice

code.

6. Block Protect io n Address: A 0, at V

IL

, A1 at VIH and A13-A19 within the Block will output the Block Protection status.

7. For C oded cycles address inputs A15-A 19 are don’t care.

8. Opti onal, additional Blocks addr esses mus t be entered within the erase t i meout delay a ft er las t write entry, t i meout st atusc a n b e
verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit
until Erase is completed or suspended.

9. Rea d Data Poll i ng, T oggle bits or RB

until Erase complete s.

10. Duri ng Erase Su spend, Read and Data Prog ram functions are allow ed in blocks not bei ng erased.

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

RD

(2,4)

Read/Reset
Memory Array

1+

Addr.

(3,7)

X

Read Memo ry Array unti l a new write cycle is initi ated.

Data F0h

3+

Addr.

(3,7)

555h 2AAh 555h

Read Memory Array until a new write cycle is
initiated.

Data AAh 55h F0h

AS

(4)

Auto Select 3+

Addr.

(3,7)

555h 2AAh 555h

Read Ele ct ronic Signature or Block P rotection
Status until a new write cycle is initiated. See Note 5
and 6.Data AAh 55h 90h

PG Pr ogram 4

Addr.

(3,7)

555h 2AAh 555h

Program
Address

Read Data Polling or Toggle Bit until
Program com pl etes.

Data AAh 55h A0h

Program

Data

BE Block Erase

6

Addr.

(3,7)

555h 2AAh 555h 555h 2AAh

Block

Address

Additional

Block

(8)

Data AAh 55h 80h AAh 55h 30h 30h

CE Chip Erase

6

Addr.

(3,7)

555h 2AAh 555h 555h 2AAh 555h

Note 9

Data AAh 55h 80h AAh 55h 10h

ES

(10)

Eras e Suspen d 1

Addr.

(3,7)

X

Read until Toggle stops, then read all th e data needed from any Block( s) not
being erased then Resum e Erase.

Data B0h

ER Erase Resume 1

Addr.

(3,7)

X

Read Data Polling or Toggle Bits until Erase completes or Erase is suspended
another time.

Data 30h

M29W008AT, M29W008AB

10/30

Table 10. Status Register Bits

Note: Logic level ’1’ is Hig h, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represen t bit value in successive Read opera tions.

DQ Name Logic Level Definition Note

7

Data
Polling

’1’

Erase Complete or erase block
in Erase Suspend

Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits DQ5 for program or Erase
Success.

’0’ Erase On-going

DQ

Program Complete or data of
non erase block during Erase
Suspend

DQ

Program On-going

6 Toggle Bit

’-1-0-1-0-1-0-1-’ Erase or Program On-going

Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.

DQ Program Complete

’-1-1-1-1-1-1-1-’

Erase Complete or Erase
Suspend on currently
addressed block

5 Error Bit

’1’ Program or Erase Error

This bit is set to ‘1’ in the case of
Programming or Erase failure.

’0’ Program or Erase On-going

4 Reserved

3

Erase
Time Bit

’1’ Erase Timeout Period Expired

P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).

’0’ Erase Timeout Period On-going

An additional block to be erased in parallel
can be entered to the P/E.C.

2 Toggle Bit

’-1-0-1-0-1-0-1-’

Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the currently
addressed block
(when DQ5 = ‘1’).

Indicates the erase status and allows to
identify the erased block.

1

Program on-going, Erase on­going on another block or
Erase Complete

DQ

Erase Suspend read on non

Erase Suspend block
1 Reserved
0 Reserved

11/30

M29W008AT, M29W008AB

confirmation command. The Coded cycles consist
of writing the data AAh at address 555h during the
first cycle. During the second cycle the Coded cy­cles consist of writing the data 55h at address
2AAh. A0 to A11 are valid, other address lines are
’don’t care’. The Coded cycles happen on first and
second cycles of the command write or on the
fourth and fifth cycles.

Instructions

See Table 9.
Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera­tions will r ead the memory array a ddressed and

output the data read. A wait state of 10µs is nec­essary after Read/Reset prior to any valid read if
the memory w as in a n Erase mode when the RD
instruction is given. The Read/Reset command is
not accepted during Erase and Erase Suspend.

Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. A subsequent read will output
the manufacturer code and the device code or the
block protection status depending on th e levels of
A0 and A1. The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code, EAh for Top B oot, EBh for Bottom
Boot is output when A0 is High with A1 Low.

The AS instruction also allows access to the block
protection status. After giving the AS instruction,
A0 and A6 are set to V

IL

with A1 at VIH, while A13­A19 define the address of the block to be verified.
A read in these condi tions will out put a 0 1h if the
block is protected and a 00h if the block is not pro­tected.

Program (PG) Instruction. This in struction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W

or E and the Data
to be written on the rising edge and starts the P/
E.C. Read operations o utput the Status Register
bits after the programming has started. Memory
programming is made only by writing '0' in place of
'1'. Status bits DQ6 and DQ7 determine if pro­gramming is on-going and DQ5 allows verification
of any possible error. Programming at an address
not in blocks being erased is also possible during
erase suspend. In this case, DQ2 will toggle at the
address being programmed.

Table 11. Polling and Toggle Bits

Note: 1. Toggle if t he address is within a bloc k being erased.

’1’ if the address is wi t hi n a block no t being eras ed.

Mode DQ7 DQ6 DQ2

Program DQ7

Toggle 1
Erase 0 Toggle Note 1
Erase Suspend Read

(in Erase Suspend
block)

1 1 Toggle

Erase Suspend Read
(outside Erase Suspend
block)

DQ7 DQ6 DQ2

Erase Suspend Program DQ7

Toggle N/A

Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to det ermine the d evice status
during the Erase operations. It can also be used to
identify the block being erased. During Er ase or
Erase Suspend a read from a block bei ng erased
will cause DQ2 to toggle. A r ead from a block not
being erased will set DQ2 to '1' during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ 2 to toggle as all
blocks are b eing erased. DQ2 wi ll be set to '1' d ur ­ing program operation and when erase is com­plete. After erase completion and if the error bit
DQ5 is set to '1', DQ2 will toggle if the faulty block
is addressed.

Error Bit (DQ5). This bit is set to '1' by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block
erase or program, the block in wh ich t he error oc­curred or to which the program me d dat a belongs,
must be discarded. The DQ5 failure condition will
also appear if a u ser tries t o program a '1' to a lo­cation that is previously programmed t o '0'. Other
Blocks may still be used. The error bit resets after
a Read/Reset (RD) instruction. In case of success
of Program or Erase, the error bit will be set to '0'.

Erase Timer Bit (DQ3). This bit is s et to ' 0' by the
P/E.C. when the last block Erase command has
been entered to the Co mmand Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50µs to 90µs, DQ3 returns
to '1'.

Coded Cycles

The two Coded cycles unlock the Command Inter­face. They are followed by an input command or a

M29W008AT, M29W008AB

12/30

Figure 3. AC Testing Input Output Waveform

AI01417

3V

0V

1.5V

Figure 4. AC Testing Load Circuit

AI01968

0.8V

OUT

CL = 30pF or 100pF

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 13. Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

Note: Sampled only, not 100% tested.

Table 14. DC Characteristics

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

C

IN

Input Capacitance

V

IN

= 0V

6pF

C

OUT

Output Capacitance

V

OUT

= 0V

12 pF

Symbol Parameter Test Condition Min

Typ.

Max Unit

I

LI

Input Leakage Current

0V ≤ V

IN

≤ V

CC

±1

µA

I

LO

Output Leakage Curren t

0V ≤ V

OUT

≤ V

CC

±1 µA

I

CC1

Supply Current (Read)

E

= VIL, G = VIH, f = 6MHz

310mA

I

CC2

Supply Current (Read)

E

= VIL, G = VIL, f = 6MHz

4.5 100 mA

I

CC3

Supply Current (Stand-by)

E

= VCC ±0.2V

30 100 µA

I

CC4

(1)

Supply Current
(Program or Erase)

Byte program, Block or
Chip Erase in progress

20 mA

V

IL

Input Low Voltage –0.5 0.8 V

V

IH

Input High Voltage

0.7 V

CC

VCC + 0.3

V

V

OL

Output Low Voltage

I

OL

= 1.8mA

0.45 V

V

OH

Output High Voltage CMOS

I

OH

= –100µA VCC –0.4V

V

V

ID

A9 Voltage (Electronic Signature) 11.5 12.5 V

I

ID

A9 Current (Electronic Signature)

A9 = V

ID

30 100 µA

V

LKO

(1)

Supply Voltage (Erase and
Program lock-out)

2.0 2.3 V

Table 12. AC Measurement Conditions

Input Rise and Fall Times

≤

10ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

13/30

M29W008AT, M29W008AB

Table 15. Read AC Characteristics

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. G

may be delayed by up to t

ELQV

- t

GLQV

after the fal ling edge of E without increasi ng t

ELQV

.

3. To be c onsidered onl y if the Rese t pulse is giv en while the mem ory is in Erase or Program mode.

Symbol Alt Parame ter

Test

Condition

M29W008AT / M29W008AB

Unit

80 90

V

CC

= 3.0V to 3.6V

CL = 30pF

VCC = 3.0V to 3.6V

CL = 30pF

Min Max Min Max

t

AVAV

t

RC

Address Valid to Next Address
Valid

E

= V

IL,

G =V

IL

80 90 ns

t

AVQV

t

ACC

Address Valid to Output Valid

E

= V

IL,

G =V

IL

80 90 ns

t

AXQX

t

OH

Address Transition to Output
Transition

E

= V

IL,

G =V

IL

00

ns

t

EHQX

t

OH

Chip Enable High to Output
Transition

G

= V

IL

00ns

t

EHQZ

(1)

t

HZ

Chip Enable High to Output Hi-Z

G

= V

IL

30 30 ns

t

ELQV

(2)

t

CE

Chip Enable Low to Output Valid

G

= V

IL

80 90 ns

t

ELQX

(1)

t

LZ

Chip Enable Low to Output
Transition

G

= V

IL

00ns

t

GHQX

t

OH

Output Enable High to Output
Transition

E

= V

IL

00ns

t

GHQZ

(1)

t

DF

Output Enable High to Output Hi-Z

E

= V

IL

30 30 ns

t

GLQV

(2)

t

OE

Output Enable Low to Output Valid

E

= V

IL

35 35 ns

t

GLQX

(1)

t

OLZ

Output Enable Low to Output
Transition

E

= V

IL

00ns

t

PHEL

t

RH

RP High to Chip Enable Low 50 50 ns

t

PL YH

(1,3)

t

RRB

t

READY

RP Low to Read Mode 10 10 µs

t

PLPX

t

RP

RP Pulse Width 500 500 ns

M29W008AT, M29W008AB

14/30

Table 16. Read AC Characteristics

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. G

may be delayed by up to t

ELQV

- t

GLQV

after the fal ling edge of E without increasi ng t

ELQV

.

3. To be c onsidered onl y if the Rese t pulse is giv en while the mem ory is in Erase or Program mode.

Symbol Alt Parame ter

Test

Condition

M29W008AT / M29W008AB

Unit

100 120

V

CC

= 2.7V to 3.6V
CL = 30pF

VCC = 2.7V to 3.6V

CL = 30pF

Min Max Min Max

t

AVAV

t

RC

Address Valid to Next Address
Valid

E

= V

IL,

G =V

IL

100 120 ns

t

AVQV

t

ACC

Address Valid to Output Valid

E

= V

IL,

G =V

IL

100 120 ns

t

AXQX

t

OH

Address Transition to Output
Transition

E

= V

IL,

G =V

IL

00

ns

t

EHQX

t

OH

Chip Enable High to Output
Transition

G

= V

IL

00ns

t

EHQZ

(1)

t

HZ

Chip Enable High to Output Hi-Z

G

= V

IL

30 30 ns

t

ELQV

(2)

t

CE

Chip Enable Low to Output Valid

G

= V

IL

100 120 ns

t

ELQX

(1)

t

LZ

Chip Enable Low to Output
Transition

G

= V

IL

00ns

t

GHQX

t

OH

Output Enable High to Output
Transition

E

= V

IL

00ns

t

GHQZ

(1)

t

DF

Output Enable High to Output Hi-Z

E

= V

IL

30 30 ns

t

GLQV

(2)

t

OE

Output Enable Low to Output Valid

E

= V

IL

40 50 ns

t

GLQX

(1)

t

OLZ

Output Enable Low to Output
Transition

E

= V

IL

00ns

t

PHEL

t

RH

RP High to Chip Enable Low 50 50 ns

t

PL YH

(1,3)

t

RRB

t

READY

RP Low to Read Mode 10 10 µs

t

PLPX

t

RP

RP Pulse Width 500 500 ns

15/30

M29W008AT, M29W008AB

Figure 5. Read Mode AC Waveforms

AI02191

tAVAV

tAVQV tAXQX

tELQX

tEHQX

tGLQV

tGLQX

tGHQX

VALID

A0-A19

E

G

DQ0-DQ7

tELQV

VALID

ADDRESS VALID

AND CHIP ENABLE

OUTPUT ENABLE DATA VALID

tEHQZ

tGHQZ

Note: Wri t e Enable (W) = High.

M29W008AT, M29W008AB

16/30

Table 17. Write AC Characteristics, W Controlled

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Symbol Alt Parameter

M29W008AT / M29W008AB

Unit

80 90

V

CC

= 3.0V to 3.6V

CL = 30pF

VCC = 3.0V to 3.6V

CL = 30pF

Min Max Min Max

t

AVAV

t

WC

Address Valid to Next Address Valid 80 90 ns

t

AVWL

t

AS

Address Valid to Write Enable Low 0 0 ns

t

DVWH

t

DS

Input Valid to Write Enable High 35 45 ns

t

ELWL

t

CS

Chip Enable Low to Write Enable Low 0 0 ns

t

GHWL

Output Enable High to Write Enable Low 0 0 ns

t

PHPHH

(1, 2)

t

VIDR

RP Rise Time to V

ID

500 500 ns

t

PHWL

(1)

t

RSP

RP High to Write Enable Low 4 4 µs

t

PLPX

t

RP

RP Pulse Width 500 500 ns

t

VCHEL

t

VCSVCC

High to Chip Enable Low

50 50 µs

t

WHDX

t

DH

Write Enable High to Input Transition 0 0 ns

t

WHEH

t

CH

Write Enable High to Chip Enable High 0 0 ns

t

WHGL

t

OEH

Write Enable High to Output Enable Low 0 0 ns

t

WHRL

(1)

t

BUSY

Program Erase Valid to RB Delay 90 90 ns

t

WHWL

t

WPH

Write Enable High to Write Enable Low 30 30 ns

t

WLAX

t

AH

Write Enable Low to Address Transition 45 45 ns

t

WLWH

t

WP

Write Enable Low to Write Enable High 35 35 ns

Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
cycles. During the input of the second comm and
an address within the b lock to be erased is given
and latched into the memory. Additional block
Erase Confirm commands and block addresses
can be written subsequently to erase other blocks
in parallel, without further Coded cycles. The
erase will start after the erase timeout period ( see
Erase Timer Bit DQ3 description). Thus, additional
Erase Confirm commands for other blocks must

be given within this delay. The input of a new
Erase Confirm command will restart the timeout
period. The status of the internal timer can be
monitored through the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.C. is erasing the Block(s). If
the second command gi ven is not an erase con­firm or if the Coded cycles are wrong, the instruc­tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris­ing edge of W

or E output the status register status

bits.

17/30

M29W008AT, M29W008AB

Table 18. Write AC Characteristics, W Controlled

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Symbol Alt Parameter

M29W008AT / M29W008AB

Unit

100 120

V

CC

= 2.7V to 3.6V

CL = 30pF

VCC = 2.7V to 3.6V

CL = 30pF

Min Max Min Max

t

AVAV

t

WC

Address Valid to Next Address Valid 100 120 ns

t

AVWL

t

AS

Address Valid to Write Enable Low 0 0 ns

t

DVWH

t

DS

Input Valid to Write Enable High 45 50 ns

t

ELWL

t

CS

Chip Enable Low to Write Enable Low 0 0 ns

t

GHWL

Output Enable High to Write Enable Low 0 0 ns

t

PHPHH

(1, 2)

t

VIDR

RP Rise Time to V

ID

500 500 ns

t

PHWL

(1)

t

RSP

RP High to Write Enable Low 4 4 µs

t

PLPX

t

RP

RP Pulse Width 500 500 ns

t

VCHEL

t

VCSVCC

High to Chip Enable Low

50 50 µs

t

WHDX

t

DH

Write Enable High to Input Transition 0 0 ns

t

WHEH

t

CH

Write Enable High to Chip Enable High 0 0 ns

t

WHGL

t

OEH

Write Enable High to Output Enable Low 0 0 ns

t

WHRL

(1)

t

BUSY

Program Erase Valid to RB Delay 90 90 ns

t

WHWL

t

WPH

Write Enable High to Write Enable Low 30 30 ns

t

WLAX

t

AH

Write Enable Low to Address Transition 45 50 ns

t

WLWH

t

WP

Write Enable Low to Write Enable High 35 50 ns

During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
and Read/Reset RD instructions . Data Polling bit
DQ7 returns ’0’ while the erasure is in progress
and ’1’ when i t has completed. The Toggle bit DQ2
and DQ6 toggle during the erase op eration. They
stop when erase is completed. After completion
the Status Register bit DQ5 returns ’1’ if there has
been an erase failure. In such a situation, the Tog­gle bit DQ2 can be used to determine which block
is not correctly erased. In the case of erase failure,
a Read/Reset RD instruction is necessary in order
to reset the P/E.C.

Chip Erase (CE) Instruction. This instruction
uses six write cycles. The Erase Set-up command
80h is written to address 555h on the third cycle af-

ter the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts
and the device is reset to Read Array. It is not nec­essary to program the array with 00h first as the P/
E.C. will automat ically do this be fore era sing it t o
FFh. Read operations after the sixth rising edge of
W

or E output the Status Register bits. During the
execution of the erase by the P/E.C., Data Polling
bit DQ7 returns ’0’, then ’1’ on completion. The
Toggle bits DQ2 and DQ6 toggle during erase op­eration and stop when eras e is completed. After
completion the Status Register bit DQ5 returns ’1’
if there has been an Erase Failure.

M29W008AT, M29W008AB

18/30

Figure 6. Write AC Waveforms, W Controlled

Note: Address are latched on the falling edge of W, Dat a i s latched on t he ri sing edge of W.

AI02192

E

G

W

A0-A19

DQ0-DQ7

VALID

VALID

V

CC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

RB

tWHRL

Erase Suspend (ES) Instruction. The Block
Erase operation may be suspended by this in­struction which consists of writing the command
B0h without any specific address. No Coded cy­cles are required. It permits reading of data from
another block and progra mming in another block
while an erase operation is in progress. Erase sus­pend is accepted only during the Block Erase in­struction execution. Writing this comm and during
Erase timeout will, in addition to suspending the
erase, terminate the timeout. The Toggle b it DQ6
stops toggling when the P/E.C. is suspended. The

Toggle bits will stop toggling betwee n 0.1µs and
15µs after the Erase Suspend (ES) command has
been written. The device will then automatically be
set to Read Mem ory Array mode . When erase is

suspended, a Read from blocks being erased will
output DQ2 toggling and DQ6 at '1'. A Rea d from
a block not being erased returns valid data. During
suspens ion the memory w ill respond only to the
Erase Resume ER and the Program PG instruc­tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
when the data is being programmed. A Read/Re­set command will definitively abort erasure and re­sult in invalid data in the blocks being erased.

Erase Resume (ER) Instruction. If an Erase
Suspend instruction was previously exec uted, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.

19/30

M29W008AT, M29W008AB

Table 19. Write AC Characteristics, E Controlled

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Symbol Alt Parameter

M29W008AT / M29W008AB

Unit

80 90

V

CC

= 3.0V to 3.6V

CL = 30pF

VCC = 3.0V to 3.6V

CL = 30pF

Min Max Min Max

t

AVAV

t

WC

Address Valid to Next Address Valid 80 90 ns

t

AVEL

t

AS

Address Valid to Chip Enable Low 0 0 ns

t

DVEH

t

DS

Input Valid to Chip Enable High 35 45 ns

t

EHDX

t

DH

Chip Enable High to Input Transition 0 0 ns

t

EHEL

t

CPH

Chip Enable High to Chip Enable Low 30 30 ns

t

EHGL

t

OEH

Chip Enable High to Output Enable Low 0 0 ns

t

EHRL

(1)

t

BUSY

Program Erase Valid to RB Delay 90 90 ns

t

EHWH

t

WH

Chip Enable High to Write Enable High 0 0 ns

t

ELAX

t

AH

Chip Enable Low to Address Transition 45 45 ns

t

ELEH

t

CP

Chip Enable Low to Chip Enable High 35 35 ns

t

GHEL

Output Enable High Chip Enable Low 0 0 ns

t

PHPHH

(1, 2)

t

VIDR

RP Rise TIme to V

ID

500 500 ns

t

PHWL

(1)

t

RSP

RP High to Write Enable Low 4 4 µs

t

PLPX

t

RP

RP Pulse Width 500 500 ns

t

VCHWL

t

VCSVCC

High to Write Enable Low

50 50 µs

t

WLEL

t

WS

Write Enable Low to Chip Enable Low 0 0 ns

POWE R SU PPLY
Power Up

The memory Command Interface is reset on pow­er up to Read Array. The device does not accept
commands on the first rising edge of W

, if both W
and E are at VIL with G at VIH during power-up.
Any write cycle initiation is blocked when V

CC

is

below V

LKO

.

Supply Rails

Normal precautions must be taken for supply volt­age decoupling; each device in a system should
have the V

CC

rail decoupled with a 0.1µF capacitor

close to the V

CC

and VSS pins. The PCB trace

widths should be sufficient to carry the V

CC

pro-

gram and erase currents required.

M29W008AT, M29W008AB

20/30

Table 20. Write AC Characteristics, E Controlled

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Symbol Alt Parameter

M29W008AT / M29W008AB

Unit

100 120

V

CC

= 2.7V to 3.6V

CL = 30pF

VCC = 2.7V to 3.6V

CL = 30pF

Min Max Min Max

t

AVAV

t

WC

Address Valid to Next Address Valid 100 120 ns

t

AVEL

t

AS

Address Valid to Chip Enable Low 0 0 ns

t

DVEH

t

DS

Input Valid to Chip Enable High 45 50 ns

t

EHDX

t

DH

Chip Enable High to Input Transition 0 0 ns

t

EHEL

t

CPH

Chip Enable High to Chip Enable Low 30 20 ns

t

EHGL

t

OEH

Chip Enable High to Output Enable Low 0 0 ns

t

EHRL

(1)

t

BUSY

Program Erase Valid to RB Delay 90 90 ns

t

EHWH

t

WH

Chip Enable High to Write Enable High 0 0 ns

t

ELAX

t

AH

Chip Enable Low to Address Transition 45 50 ns

t

ELEH

t

CP

Chip Enable Low to Chip Enable High 35 50 ns

t

GHEL

Output Enable High Chip Enable Low 0 0 ns

t

PHPHH

(1, 2)

t

VIDR

RP Rise TIme to V

ID

500 500 ns

t

PHWL

(1)

t

RSP

RP High to Write Enable Low 4 4 µs

t

PLPX

t

RP

RP Pulse Width 500 500 ns

t

VCHWL

t

VCSVCC

High to Write Enable Low

50 50 µs

t

WLEL

t

WS

Write Enable Low to Chip Enable Low 0 0 ns

21/30

M29W008AT, M29W008AB

Figure 7. Write AC Waveforms, E Controlled

Note: Address are latched on the falling edge of E, Data is la tc hed on the rising edge of E.

Figure 8. Read and Write AC Characteristics, RP Related

AI02193

E

G

W

A0-A19

DQ0-DQ7

VALID

VALID

V

CC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

RB

tEHRL

AI02091

RB

W

RP

tPLPX

tPHWL

tPLYH

tPHPHH

E

tPHEL

M29W008AT, M29W008AB

22/30

Table 21. Data Polling and Toggle Bit AC Characteristics

(1)

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. All other timings are defined in Read AC Characteristics table.

Table 22. Data Polling and Toggle Bit AC Characteristics

(1)

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. All other timings are defined in Read AC Characteristics table.

Symbol Parameter

M29W008AT / M29W008AB

Unit

80 90

V

CC

= 3.0V to 3.6V
CL = 30pF

VCC = 3.0V to 3.6V

CL = 30pF

Min Max Min Max

t

EHQ7V

Chip Enable High to DQ7 Valid
(Program, E

Controlled)

10 2400 10 2400 µs

Chip Enable High to DQ7 Valid
(Chip Erase, E

Controlled)

1.0 60 1.0 60 sec

t

EHQV

Chip Enable High to Output Valid (Program) 10 2400 10 2400 µs
Chip Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec

t

Q7VQV

Q7 Valid to Output Valid (Data Polling) 35 35 ns

t

WHQ7V

Write Enable High to DQ7 Valid
(Program, W

Controlled)

10 2400 10 2400 ms

Write Enable High to DQ7 Valid
(Chip Erase, W

Controlled)

1.0 60 1.0 60 sec

t

WHQV

Write Enable High to Output Valid (Program) 10 2400 10 2400 µs
Write Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec

Symbol Parameter

M29W008AT / M29W008AB

Unit

100 120

V

CC

= 2.7V to 3.6V
CL = 30pF

VCC = 2.7V to 3.6V

CL = 30pF

Min Max Min Max

t

EHQ7V

Chip Enable High to DQ7 Valid
(Program, E

Controlled)

10 2400 10 2400 µs

Chip Enable High to DQ7 Valid
(Chip Erase, E

Controlled)

1.0 60 1.0 60 sec

t

EHQV

Chip Enable High to Output Valid (Program) 10 2400 10 2400 µs
Chip Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec

t

Q7VQV

Q7 Valid to Output Valid (Data Polling) 40 50 ns

t

WHQ7V

Write Enable High to DQ7 Valid
(Program, W

Controlled)

10 2400 10 2400 ms

Write Enable High to DQ7 Valid
(Chip Erase, W

Controlled)

1.0 60 1.0 60 sec

t

WHQV

Write Enable High to Output Valid (Program) 10 2400 10 2400 µs
Write Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec

23/30

M29W008AT, M29W008AB

Figure 9. Data Po ll i ng DQ7 AC Wave form s

AI02194

E

G

W

A0-A19

DQ7

IGNORE

VALID

DQ0-DQ6

ADDRESS (WITHIN BLOCKS)

DATA OUTPUT VALID

tAVQV

tEHQ7V

tGLQV

tWHQ7V

VALID

tQ7VQV

DQ7

DATA POLLING (LAST) CYCLE MEMORY

ARRAY

READ CYCLE

DATA POLLING

READ CYCLES

LAST WRITE

CYCLE OF

PROGRAM

OR ERASE

INSTRUCTION

tELQV

M29W008AT, M29W008AB

24/30

Table 23. Program, Erase Times and Program , Erase End urance Cycl es

(T

A

= 0 to 70°C; VCC = 2.7V to 3.6V)

Note: 1. Excluded the time required to execute bus cycles sequence for program operation.

Parameter

M29W008AT / M29W008AB

Unit

Min Typ

Typical after

100k W/E Cycles

Max

Chip Erase (Preprogrammed, V

CC

= 2.7V)

10 10 sec

Chip Erase (V

CC

= 2.7V)

15 15 sec

Main Block Erase (V

CC

= 2.7V)

1.5 15 sec

Chip Program (Byte)

(1)

55 sec

Byte Program 10 10 µs

Program/Erase Cycles (per Block) 100,000 cycles

Figure 10. Data Polling Flowchart

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

FAIL PASS

AI01369

DQ7

=

DATA

YES

NO

YES

NO

DQ5

= 1

DQ7

=

DATA

YES

NO

Figure 11. Data Toggle Flowchart

READ

DQ2, DQ5 & DQ6

START

READ DQ2, DQ6

FAIL PASS

AI01873

DQ2, DQ6

=

TOGGLE

NO

NO

YES

YES

DQ5

= 1

NO

YES

DQ2, DQ6

=

TOGGLE

25/30

M29W008AT, M29W008AB

Figure 12. Data Toggle DQ6, DQ2 AC Waveforms

AI02195

E

G

W

A0-A19

DQ6,DQ2

tAVQV

STOP TOGGLE

LAST WRITE

CYCLE OF

PROGRAM

OF ERASE

INSTRUCTION

VALID

VALID

VALID

IGNORE

DATA TOGGLE

READ CYCLE

MEMORY ARRAY

READ CYCLE

tWHQV

tEHQV

tELQV

tGLQV

DATA

TOGGLE

READ CYCLE

DQ0-DQ1,DQ3-DQ5,DQ7

Note: All othe r ti m i ngs are as a normal Read cycl e .

M29W008AT, M29W008AB

26/30

Table 24. Security Block Instruction

Note: 1. Address bi ts A10-A19 are don’t ca re for coded address inputs.

2. Data bits DQ8-DQ15 are don’t care for cod ed address inputs.

Mne. Instr. Cyc.

Unlock Cycle

2nd Cyc.

1st Cyc.

RDS

Read
Security
Data

1

Addr.

(1)

AAh

Read OTP Data until a new write cycle is initiated.

Data

(2)

B8h

Figure 13. Security Block Address Table

Security

Memory Block

AI02740

TOP BOOT BLOCK

000FFh

Security

Memory Block

00000h

0E0FFh

0E000h

BOTTOM BOOT BLOCK

SECURITY PROTECTION MEMORY AREA

The M29W008A features a security protection
memory area. It consists of a memory block of 256
bytes which is programmed in the ST factory to
store a unique code that uniquely identifies the
part.

This memory block can be read by using the Read
Security Data instruction (RDS) as shown in Table

24.

Read Security Data (RDS) Instruction. This RDS
uses a single write cycle instruction: the command
B8h is written to the address AAh. This sets the
memory to the Read Security mode. Any succes­sive read attempt will output the addressed Sec u­rity byte until a new write cycle is initiated.

27/30

M29W008AT, M29W008AB

Table 25. Ordering Information Scheme

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the ST Sales Office nearest to you.

Example: M29W008AT 80 N 1 T

Device Type

M29

Operating Voltage

W = 2.7 to 3.6V

Device Function

008A = 8 Mbit (1Mb x8), Boot Block

Array Matrix

T = Top Boot
B = Bottom Boot

Speed

80 = 80 ns
90 = 90 ns
100 = 100 ns
120 = 120 ns

Package

N = TSOP40: 10 x 20 mm

Temperature Range

1 = 0 to 70 °C
5 = –20 to 85°C
6 = –40 to 85 °C

Option

T = Tape & Reel Packing

M29W008AT, M29W008AB

28/30

Table 26. Revision History

Date Description

November 1998 First issue

02/09/00

New document template
Document type: from Preliminary Data to Data Sheet

03/06/00 Program Erase Times change (Table 23)

29/30

M29W008AT, M29W008AB

Table 27. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

Symbol

mm inches

Typ Min Max Typ Min Max

A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 9.90 10.10 0.3898 0 .3976

e 0.50 – – 0.0197 – –

L 0.50 0.7 0 0.0197 0.0276

α

0° 5° 0° 5°

N40 40

CP 0.10 0.0039

Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

Drawing is not to scale.

TSOP-a

D1

E

1 N

CP

B

e

A2

A

N/2

D

DIE

C

LA1 α

M29W008AT, M29W008AB

30/30

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