Datasheet LTC3548 Datasheet (LINEAR TECHNOLOGY)

查询LT3407供应商

FEATURES

LTC3548

Dual Synchronous,

400mA/800mA, 2.25MHz

Step-Down DC/DC Regulator

U

DESCRIPTIO

■

High Efficiency: Up to 95%

■

Very Low Quiescent Current: Only 40µA

■

2.25MHz Constant Frequency Operation

■

High Switch Current: 0.7A and 1.2A

■

No Schottky Diodes Required

■

Low R

■

Current Mode Operation for Excellent Line

Internal Switches: 0.35Ω

DS(ON)

and Load Transient Response

■

Short-Circuit Protected

■

Low Dropout Operation: 100% Duty Cycle

■

Ultralow Shutdown Current: IQ < 1µA

■

Output Voltages from 5V down to 0.6V

■

Power-On Reset Output

■

Externally Synchronizable Oscillator

■

Small Thermally Enhanced MSOP and 3mm × 3mm
DFN Packages

U

APPLICATIO S

■

PDAs/Palmtop PCs

■

Digital Cameras

■

Cellular Phones

■

Portable Media Players

■

PC Cards

■

Wireless and DSL Modems

The LTC®3548 is a dual, constant frequency, synchronous
step down DC/DC converter. Intended for low power
applications, it operates from 2.5V to 5.5V input voltage
range and has a constant 2.25MHz switching frequency,
allowing the use of tiny, low cost capacitors and inductors
with a profile ≤1.2mm. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35Ω, 0.7A/1.2A
power switches provide high efficiency without the need
for external Schottky diodes.

A user selectable mode input is provided to allow the user
to trade-off noise ripple for low power efficiency. Burst
Mode® operation provides high efficiency at light loads,
while Pulse Skip Mode provides low noise ripple at light
loads.

To further maximize battery runtime, the P-channel
MOSFETs are turned on continuously in dropout (100%
duty cycle), and both channels draw a total quiescent
current of only 40µA. In shutdown, the device draws <1µA.

, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Burst Mode is a registered
trademark of Linear Technology Corporation. Protected by U.S. Patents including 5481178,
6580258, 6304066, 6127815, 6498466, 6611131.

TYPICAL APPLICATIO

V

= 2.8V

IN

TO 5.5V

10µF

= 2.5V

V

OUT2

AT 400mA

4.7µF 10µF

887k 604k

Figure 1. 2.5V/1.8V at 400mA/800mA Step-Down Regulators

RUN2 V

MODE/SYNC

SW2

V

FB2

U

IN

LTC3548

GND

RUN1

POR

SW1

V

FB1

LTC3548 Efficiency Curve

100

100k

RESET

2.2µH4.7µH

33pF68pF

301k280k

V

= 1.8V

OUT1

AT 800mA

3548 TA01

95

90

85

80

POWER LOSS

75

EFFICIENCY (%)

70

65

60

1

EFFICIENCY

VIN = 3.3V, V
Burst Mode OPERATION
CHANNEL 1, NO LOAD ON CHANNEL 2

LOAD CURRENT (mA)

= 1.8V

OUT

10 100 1000

3548 TA02

1000

100

POWER LOSS (mW)

10

1

0.1

3548f

1

LTC3548

TOP VIEW

1
2
3
4
5

V

FB1

RUN1

V

IN

SW1
GND

10
9
8
7
6

V

FB2

RUN2
POR
SW2

MODE/
SYNC

11

MSE PACKAGE

10-LEAD PLASTIC MSOP

MSE PIN 11, EXPOSED PAD: PGND

MUST BE CONNECTED TO GND

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

VIN Voltages.................................................–0.3V to 6V

, V

V

FB1

, RUN1, RUN2

FB2

Voltages ..................................... – 0.3V to VIN + 0.3V

MODE/SYNC Voltage ...................... – 0.3V to V

SW1, SW2 Voltage ......................... – 0.3V to V

+ 0.3V

IN

+ 0.3V

IN

POR Voltage ................................................ – 0.3V to 6V

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

V

1

FB1

RUN1

2

11

3

V

IN

4

SW1

5

GND

10-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

DD PACKAGE

DD PIN 11, EXPOSED PAD: PGND

MUST BE CONNECTED TO GND

= 125°C, θJA = 45°C/W, θJC = 3°C/W

(Soldered to a 4-layer board)

10

V

RUN2

9

POR

8

7

SW2

6

MODE/
SYNC

FB2

ORDER PART

NUMBER

LTC3548EDD

DD PART MARKING

LBNJ

Ambient Operating Temperature

Range (Note 2) ................................... –40°C to 85°C

Junction Temperature (Note 5)............................. 125°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

LTC3548EMSE only .......................................... 300°C

ORDER PART

NUMBER

LTC3548EMSE

MSE PART MARKING

LTBNH

T

= 125°C, θJA = 45°C/W, θJC = 10°C/W

JMAX

(Soldered to a 4-layer board)

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

FB

V

FB

∆V

LINE REG

∆V

LOAD REG

I

S

f

OSC

f

SYNC

I

LIM

R

DS(ON)

I

SW(LKG)

2

The ● denotes the specifications which apply over the full operating

Operating Voltage Range ● 2.5 5.5 V
Feedback Pin Input Current ● 30 nA
Feedback Voltage (Note 3) 0°C ≤ TA ≤ 85°C 0.588 0.6 0.612 V

–40°C ≤ T

Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) 0.3 0.5 %/V
Output Voltage Load Regulation (Note 3) 0.5 %
Input DC Supply Current

Active Mode V
Sleep Mode V

FB1
FB1

Shutdown RUN = 0V, V
Oscillator Frequency VFB = 0.6V ● 1.8 2.25 2.7 MHz
Synchronization Frequency 2.25 MHz
Peak Switch Current Limit Channel 1 VIN = 3V, VFB = 0.5V, Duty Cycle <35% 0.95 1.2 1.6 A

Peak Switch Current Limit Channel 2 V

IN

Top Switch On-Resistance (Note 6) 0.35 0.45 Ω
Bottom Switch On-Resistance (Note 6) 0.30 0.45 Ω

Switch Leakage Current VIN = 5V, V

≤ 85°C ● 0.585 0.6 0.612 V

A

= V

= 0.5V 700 950 µA

FB2

= V

= 0.63V, MODE/SYNC = 3.6V 40 60 µA

FB2

= 5.5V, MODE/SYNC = 0V 0.1 1 µA

IN

= 3V, VFB = 0.5V, Duty Cycle <35% 0.6 0.7 0.9 A

= 0V, VFB = 0V 0.01 1 µA

RUN

3548f

LTC3548

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

POR Power-On Reset Threshold VFB Ramping Down, MODE/SYNC = 0V –8.5 %

Power-On Reset On-Resistance 100 200 Ω
Power-On Reset Delay 262,144 Cycles

V

RUN

I

RUN

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired. No pin shall exceed 6V.

Note 2: The LTC3548 is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the – 40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: The LTC3548 is tested in a proprietary test mode that connects

RUN Threshold ● 0.3 1 1.5 V
RUN Leakage Current ● 0.01 1 µA

to the output of the error amplifier.

V

FB

Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.

Note 5: T

is calculated from the ambient TA and power dissipation P

J

D

according to the following formula: TJ = TA + (PD • θJA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to

wafer level measurements.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

TA = 25°C unless otherwise specified.

Load StepBurst Mode Operation Pulse Skipping Mode

SW

5V/DIV

V

OUT

20mV/DIV

I

L

200mA/DIV

VIN = 3.6V

= 1.8V

V

OUT

= 180mA

I

LOAD

CHANNEL 1; CIRCUIT OF FIGURE 3

Efficiency vs Input Voltage

100

95

90

85

80

75

EFFICIENCY (%)

70

V

65

Burst Mode OPERATION
CIRCUIT OF FIGURE 3

60

2

100mA

10mA

1mA

800mA

= 1.8V, CHANNEL 1

OUT

3

INPUT VOLTAGE (V)

SW

5V/DIV

V

OUT

10mV/DIV

I

L

200mA/DIV

2µs/DIV 1µs/DIV

3548 G01 3548 G02

V

= 3.6V

IN

= 1.8V

V

OUT

= 30mA

I

LOAD

CHANNEL 1; CIRCUIT OF FIGURE 3

Oscillator Frequency vs
Temperature

2.5

VIN = 3.6V

2.4

2.3

2.2

FREQUENCY (MHz)

2.1

456

3548 G04

2.0

–50 25 75

–25 0

TEMPERATURE (°C)

50 100 125

3548 G05

V

OUT

200mV/DIV

I

L

500mA/DIV

I

LOAD

500mA/DIV

V

= 3.6V

IN

= 1.8V

V

OUT

= 80mA TO 800mA

I

LOAD

CHANNEL 1; CIRCUIT OF FIGURE 3

Oscillator Frequency vs Supply
Voltage

10

8

6

4

2

0

–2

–4

FREQUENCY DEVIATION (%)

–6

–8

–10

2

20µs/DIV

3

SUPPLY VOLTAGE (V)

456

3548 G03

3548 G06

3548f

3

LTC3548

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Reference Voltage vs
Temperature R

0.615
VIN = 3.6V

0.610

0.605

0.600

0.595

REFERENCE VOLTAGE (V)

0.590

0.585

–50 25 75

–25 0

TEMPERATURE (°C)

50 100 125

3548 G07

500

450

400

(mΩ)

350

DS(ON)

R

300

250

200

1

vs Input Voltage R

DS(ON)

TA = 25°C

MAIN
SWITCH

SYNCHRONOUS

SWITCH

3

2

V

57

46

(V)

IN

3548 G08

550

500

450

400

350

(mΩ)

300

DS(ON)

R

250

200

150

100

vs Junction Temperature

DS(ON)

VIN = 4.2V

MAIN SWITCH
SYNCHRONOUS SWITCH

–50

–25 0

25 75

JUNCTION TEMPERATURE (°C)

VIN = 2.7V

VIN = 3.6V

50 100 150125

3548 G09

Efficiency vs Load Current

100

95

90

Burst Mode OPERATION

85

80

75

EFFICIENCY (%)

70

65

60

1

NO LOAD ON OTHER CHANNEL

CHANNEL 1; CIRCUIT OF FIGURE 3

10 100 1000

LOAD CURRENT (mA)

Efficiency vs Load Current

100

2.7V

90

80

70

EFFICIENCY (%)

60

V

50

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3

40

1

3.6V

4.2V

= 2.5V, CHANNEL 1

OUT

10 100 1000

LOAD CURRENT (mA)

PULSE SKIP MODE

VIN = 3.6V, V

OUT

= 1.8V

3548 G11

3548 G10

Load Regulation

2.0

1.5

Burst Mode OPERATION

1.0

0.5

0

PULSE SKIP MODE

ERROR (%)

–0.5

OUT

V

–1.0

–1.5

–2.0

1

NO LOAD ON OTHER CHANNEL

CHANNEL 1; CIRCUIT OF FIGURE 3

10 100 1000

LOAD CURRENT (mA)

Efficiency vs Load Current

100

95

90

2.7V

85

80

75

EFFICIENCY (%)

70

V

= 1.5V, CHANNEL 1

OUT

Burst Mode OPERATION

65

NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3

60

1

3.6V

4.2V

10 100 1000

LOAD CURRENT (mA)

VIN = 3.6V, V

OUT

= 1.8V

3548 G12

3548 G14

Line Regulation

0.5
V

= 1.8V

OUT

0.4

= 200mA

I

OUT

= 25°C

T

A

0.3

0.2

0.1

0

ERROR (%)

–0.1

OUT

V

–0.2

–0.3

–0.4

–0.5

2

35

Efficiency vs Load Current

100

95

90

2.7V

85

80

75

EFFICIENCY (%)

70

65

60

4.2V

V

= 1.2V, CHANNEL 1

OUT

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3

1

10 100 1000

LOAD CURRENT (mA)

4

VIN (V)

6

3548 G15

3.6V

3548 G13

4

3548f

LTC3548

U

UU

PI FU CTIO S

V

(Pin 1): Output Feedback. Receives the feedback

FB1

voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.

RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to V
enables regulator 1, while forcing it to GND causes regu­lator 1 to shut down. This pin must be driven; do not float.

VIN (Pin 3): Main Power Supply. Must be closely decoupled
to GND.

SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.

GND (Pin 5): Main Ground. Connect to the (–) terminal of
C

, and (–) terminal of CIN.

OUT

MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the operation
of the device. When tied to VIN or GND, Burst Mode
operation or pulse skipping mode is selected, respec­tively. Do not float this pin. The oscillation frequency can

IN

be synchronized to an external oscillator applied to this pin
and pulse skipping mode is automatically selected.

SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.

POR (Pin 8): Power-On Reset . This common-drain logic
output is pulled to GND when the output voltage falls
below –8.5% of regulation and goes high after 117ms
when both channels are within regulation.

RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to V
enables regulator 2, while forcing it to GND causes regu­lator 2 to shut down. This pin must be driven; do not float.

V

(Pin 10): Output Feedback. Receives the feedback

FB2

voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.

Exposed Pad (GND) (Pin 11): Power Ground. Connect to
the (–) terminal of C
connected to electrical ground on PCB.

, and (–) terminal of CIN. Must be

OUT

IN

3548f

5

LTC3548

BLOCK DIAGRA

W

MODE/SYNC

V

RUN1

RUN2

V

REGULATOR 1

6

SLOPE
COMP

EN

0.35V

–

BURST

+

SRQ

RS

LATCH

Q

SLEEP

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

PGOOD1

POR

COUNTER

PGOOD2

+

0.6V

1

FB1

0.55V

–

–

UVDET

I

TH

EA

UV

+

+

OVDET

0.65V

–

SHUTDOWN

2

0.6V REF OSC

9

REGULATOR 2 (IDENTICAL TO REGULATOR 1)

10

FB2

OV

OSC

–

I

COMP

ANTI

SHOOT-

THRU

I

RCMP

+

BURST
CLAMP

+

–

V

IN

5Ω

SW1

4

GND

11

V

IN

3

V

IN

POR

8

5

GND

7

SW2

U

OPERATIO

The LTC3548 uses a constant frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable Mode pin allows
the user to choose between low noise and high efficiency.

The output voltage is set by an external divider returned to
the VFB pins. An error amplfier compares the divided
output voltage with a reference voltage of 0.6V and adjusts
the peak inductor current accordingly. An undervoltage
comparator will pull the POR output low if the output
voltage is not above –8.5% of the reference voltage. The
POR output will go high after 262,144 clock cycles (about
117ms) of achieving regulation.

3548 BD

Main Control Loop

During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the VFB voltage is below the the reference voltage.
The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.

The peak inductor current is controlled by the internally
compensated ITH voltage, which is the output of the error
amplifier.This amplifier compares the VFB pin to the 0.6V
reference. When the load current increases, the VFB volt­age decreases slightly below the reference. This

3548f

6

OPERATIO

LTC3548

U

decrease causes the error amplifier to increase the I
voltage until the average inductor current matches the new
load current.

The main control loop is shut down by pulling the RUN pin
to ground.

Low Current Operation

By selecting MODE/SYNC (pin 6), two modes are available
to control the operation of the LTC3548 at low currents.
Both modes automatically switch from continuous opera­tion to the selected mode when the load current is low.

To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3548
automatically switches into Burst Mode operation, in
which the PMOS switch operates intermittently based on
load demand with a fixed peak inductor current. By run­ning cycles periodically, the switching losses which are
dominated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
voltage comparator trips when I
ting off the switch and reducing the power. The output
capacitor and the inductor supply the power to the load
until ITH exceeds 0.65V, turning on the switch and the main
control loop which starts another cycle.

For lower ripple noise at low currents, the pulse skipping

is below 0.35V, shut-

TH

TH

mode can be used. In this mode, the LTC3548 continues
to switch at a constant frequency down to very low
currents, where it will begin skipping pulses. The effi­ciency in pulse skip mode can be improved slightly by
connecting the SW node to the MODE/SYNC input which
reduces the clock frequency by approximately 30%.

Dropout Operation

When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal p-channel MOSFET and the inductor.

An important design consideration is that the R
the P-channel switch increases with decreasing input
supply voltage (See Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3548 is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applica­tions Information Section).

Low Supply Operation

To prevent unstable operation, the LTC3548 incorporates
an Under-Voltage Lockout circuit which shuts down the
part when the input voltage drops below about 1.65V.

DS(ON)

of

WUUU

APPLICATIO S I FOR ATIO

A general LTC3548 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, CIN and C
be selected.

Inductor Selection

Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ∆IL decreases with
higher inductance and increases with higher VIN or V

∆ =

I

L

V

OUT

•–1

•

fL

O

⎛
⎜

⎝

V

OUT

V

IN

⎞
⎟

⎠

OUT

can

OUT

:

Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is
∆IL = 0.3 • I
channel 1 and 400mA for channel 2. The largest ripple
current ∆IL occurs at the maximum input voltage. To
guarantee that the ripple current stays below a specified
maximum, the inductor value should be chosen according
to the following equation:

L

=

The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation

OUT(MAX)

V

OUT

•–

fIVV

∆

•

OL

⎛

1

⎜
⎝

, where I

⎞

OUT

⎟
⎠

()

IN MAX

OUT(MAX)

is 800mA for

3548f

7

LTC3548

U

WUU

APPLICATIO S I FOR ATIO

begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency to
increase.

Inductor Core Selection

Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate­rials are small and don’t radiate much energy, but gener­ally cost more than powdered iron core inductors with
similar electrical characterisitics. The choice of which
style inductor to use often depends more on the price vs
size requirements and any radiated field/EMI require­ments than on what the LTC3548 requires to operate.
Table 1 shows some typical surface mount inductors that
work well in LTC3548 applications.

Input Capacitor (CIN) Selection

In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately V
VIN. To prevent large voltage transients, a low equivalent
series resistance (ESR) input capacitor sized for the maxi­mum RMS current must be used. The maximum RMS
capacitor current is given by:

(– )

VVV

II

≈

RMS MAX

where the maximum average output current I

OUT IN OUT

V

IN

MAX

the peak current minus half the peak-to-peak ripple cur­rent, I

This formula has a maximum at VIN = 2V
= I

OUT/2

= I

MAX

– ∆IL/2.

LIM

OUT

, where I

. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours life­time. This makes it advisable to further derate the capaci­tor, or choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recom-
mended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.

OUT

equals

RMS

/

Table 1. Representative Surface Mount Inductors

PART VALUE DCR MAX DC SIZE
NUMBER (µH) (Ω MAX) CURRENT (A) W × L × H (mm

Sumida 2.2 0.075 1.20 3.8 × 3.8 × 1.8
CDRH3D16 3.3 0.110 1.10

4.7 0.162 0.90

Sumida 1.5 0.068 0.900 3.2 × 3.2 × 1.2
CDRH2D11 2.2 0.170 0.780

Sumida 2.2 0.116 0.950 4.4 × 5.8 × 1.2
CMD4D11 3.3 0.174 0.770

Murata 1.0 0.060 1.00 2.5 × 3.2 × 2.0
LQH32CN 2.2 0.097 0.79

Toko 2.2 0.060 1.08 2.5 × 3.2 × 2.0
D312F 3.3 0.260 0.92

Panasonic 3.3 0.17 1.00 4.5 × 5.4 × 1.2
ELT5KT 4.7 0.20 0.95

Output Capacitor (C

The selection of C

) Selection

OUT

is driven by the required ESR to

OUT

3

)

minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (∆V

) is deter-

OUT

mined by:

∆≈∆ +

V I ESR

OUT L

⎜
⎝

8

fC

O OUT

where f = operating frequency, C

⎛

⎞

1

⎟
⎠

= output capacitance

OUT

and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3 • I

OUT(MAX)

the output
ripple will be less than 100mV at maximum VIN and
fO= 2.25MHz with:

ESR

Once the ESR requirements for C
RMS current rating generally far exceeds the I

COUT

< 150mΩ

have been met, the

OUT

RIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi­num electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages. The
OS-CON semiconductor dielectric capacitor available from
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer

3548f

8

LTC3548

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APPLICATIO S I FOR ATIO

capacitors, such as Sanyo POSCAP, Panasonic Special
Polymer (SP), and Kemet A700, offer very low ESR, but
have a lower capacitance density than other types. Tanta­lum capacitors have the highest capacitance density, but
they have a larger ESR and it is critical that the capacitors
are surge tested for use in switching power supplies. An
excellent choice is the AVX TPS series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors have a signifi­cantly larger ESR, and are often used in extremely cost­sensitive applications provided that consideration is given
to ripple current ratings and long term reliability. Ceramic
capacitors have the lowest ESR and cost, but also have the
lowest capacitance density, a high voltage and tempera­ture coefficient, and exhibit audible piezoelectric effects.
In addition, the high Q of ceramic capacitors along with
trace inductance can lead to significant ringing.

In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3548 in parallel with the
main capacitors for high frequency decoupling.

V

= 2.5V

IN

TO 5.5V

C

IN

BM*

V

OUT2

R4 R2

C

OUT2

R3

RUN2 V

IN

MODE/SYNC

PS*

L2

LTC3548

SW2

V

FB2

GND

*MODE/SYNC = 0V: PULSE SKIP
MODE/SYNC = V

RUN1

POR

SW1

V

: Burst Mode

IN

Figure 2. LTC3548 General Schematic

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempt­ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generates a loop “zero” at 5kHz to 50kHz that is instrumen­tal in giving acceptable loop phase margin. Ceramic ca­pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which

R5

POWER-ON
RESET

L1

C4C5

FB1

R1

C

V

OUT1

OUT1

3548 F02

requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramic capacitors is available from Taiyo Yuden, AVX,
Kemet, TDK, and Murata.

Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.

Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation and the
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, V

DROOP

, is usually
about 2-3 times the linear drop of the first cycle. Thus, a
good place to start is with the output capacitor size of
approximately:

I

C

OUT

≈∆25.

OUT

fV

•

O DROOP

More capacitance may be required depending on the duty
cycle and load step requirements.

In most applications, the input capacitor is merely re­quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.

Setting the Output Voltage

The LTC3548 develops a 0.6V reference voltage between
the feedback pin, VFB, and the ground as shown in
Figure 2. The output voltage is set by a resistive divider
according to the following formula:

3548f

9

LTC3548

U

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APPLICATIO S I FOR ATIO

VV

=+

06 1

OUT

.

⎜
⎝

Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.

To improve the frequency response, a feed-forward ca-

⎛

pacitor C
route the V

may also be used. Great care should be taken to

F

line away from noise sources, such as the

FB

inductor or the SW line.

Power-On Reset

The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are above –8.5% of regulation, a timer is started
which releases POR after 2
This delay can be significantly longer in Burst Mode
operation with low load currents, since the clock cycles
only occur during a burst and there could be milliseconds
of time between bursts. This can be bypassed by tying the
POR output to the MODE/SYNC input, to force pulse
skipping mode during a reset. In addition, if the output
voltage faults during Burst Mode sleep, POR could have a
slight delay for an undervoltage output condition. This can
be avoided by using pulse skipping mode instead. When
either channel is shut down, the POR output is pulled low,
since one or both of the channels are not in regulation.

Mode Selection and Frequency Synchronization

The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect­ing this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. Connecting this pin to ground
selects pulse skipping mode, which provides the lowest
output ripple, at the cost of low current efficiency.

⎞

R

2

⎟

R

1

⎠

18

clock cycles (about 117ms).

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ∆I
resistance of C
discharge C

• ESR, where ESR is the effective series

LOAD

OUT

, generating a feedback error signal used

OUT

by the regulator to return V
During this recovery time, V

immediately shifts by an amount

OUT

. ∆I

also begins to charge or

LOAD

to its steady-state value.

OUT

can be monitored for

OUT

overshoot or ringing that would indicate a stability
problem.

The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second­order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feed-forward capacitor, C

,

F

can be added to improve the high frequency response, as
shown in Figure 2. Capacitor CF provides phase lead by
creating a high frequency zero with R2, which improves
the phase margin.

The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica­tion Note 76.

In some applications, a more severe transient can be
caused by switching loads with large (>1µF) load input
capacitors. The discharged load input capacitors are ef­fectively put in parallel with C
V

. No regulator can deliver enough current to prevent

OUT

, causing a rapid drop in

OUT

this problem, if the switch connecting the load has low
resistance and is driven quickly. The solution is to limit the
turn-on speed of the load switch driver. A Hot Swap

TM

controller is designed specifically for this purpose and
usually incorporates current limiting, short-circuit protec­tion, and soft-starting.

The LTC3548 can also be synchronized to an external

2.25MHz clock signal by the MODE/SYNC pin. During
synchronization, the mode is set to pulse skipping and the
top switch turn-on is synchronized to the rising edge of the
external clock.

10

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would

Hot Swap is a trademark of Linear Technology Corporation.

3548f

LTC3548

U

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APPLICATIO S I FOR ATIO

produce the most improvement. Percent efficiency can be
expressed as:

% Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3548 circuits: 1)V

2

2) switching losses, 3) I

1) The V

current is the DC supply current given in the

IN

R losses, 4) other losses.

Electrical Characteristics which excludes MOSFET driver
and control currents. VIN current results in a small (< 0.1%)
loss that increases with VIN, even at no load.

2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN that is
typically much larger than the DC bias current. In continu­ous mode, I

GATECHG

= fO(QT + QB), where QT and QB are the
gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
and thus their effects will be more pronounced at higher
supply voltages.

3) I2R losses are calculated from the DC resistances of the
internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current flows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
R

The R

and the duty cycle (D) as follows:

DS(ON)

RSW = (R

DS(ON)

DS(ON)TOP

for both the top and bottom MOSFETs can be

)(D) + (R

obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:

I2R losses = I

OUT2(RSW

+ RL)

4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to

quiescent current,

IN

DS(ON)BOT

)(1 – D)

IN

include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C

has adequate

IN

charge storage and very low ESR at the switching fre­quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac­count for less than 2% total additional loss.

Thermal Considerations

In a majority of applications, the LTC3548 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3548 is running at high ambi­ent temperature with low supply voltage and high duty
cycles, such as in dropout, the heat dissipated may exceed
the maximum junction temperature of the part. If the
junction temperature reaches approximately 150°C, both
power switches will turn off and the SW node will become
high impedance.

To prevent the LTC3548 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera­ture rise is given by:

T

= PD • θ

RISE

where PD is the power dissipated by the regulator and θ

JA

JA

is the thermal resistance from the junction of the die to the
ambient temperature.

The junction temperature, TJ, is given by:

TJ = T

RISE

+ T

AMBIENT

As an example, consider the case when the LTC3548 is in
dropout on both channels at an input voltage of 2.7V with
a load current of 400mA and 800mA and an ambient
temperature of 70°C. From the Typical Performance Char­acteristics graph of Switch Resistance, the R

DS(ON)

resis-

tance of the main switch is 0.425Ω. Therefore, power
dissipated by each channel is:

PD = I2 • R

= 272mW and 68mW

DS(ON)

The MS package junction-to-ambient thermal resistance,

θJA, is 45°C/W. Therefore, the junction temperature of the

3548f

11

LTC3548

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APPLICATIO S I FOR ATIO

regulator operating in a 70°C ambient temperature is
approximately:

TJ = (0.272 + 0.068) • 45 + 70 = 85.3°C

which is below the absolute maximum junction tempera­ture of 125°C.

Design Example

As a design example, consider using the LTC3548 in an
portable application with a Li-Ion battery. The battery
provides a V
mum of 800mA in active mode and 2mA in standby mode.
The output voltage is V
needs power in standby, Burst Mode operation is selected
for good low load efficiency.

First, calculate the inductor value for about 30% ripple
current at maximum VIN:

L

2 25 240

Choosing a vendor’s closest inductor value of 2.2µH,
results in a maximum ripple current of:

∆ =

L

For cost reasons, a ceramic capacitor will be used. C
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:

C

OUT

A good standard value is 10µF. Since the output imped-
ance of a Li-Ion battery is very low, CIN is typically 10µF.

The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing

= 2.8V to 4.2V. The load requires a maxi-

IN

= 2.5V. Since the load still

OUT

V

25

.

MHz mA

.•

V

25

.

MHz

225 22

.•.

≈ =µ25

225 5 25

.•(%•.)

µ

800

MHz V

⎛

•–

⎜
⎝

⎛

•

⎜
⎝

mA

V

25

.

⎞

.

25

.

42

.

=µ

⎟
⎠

V

⎞

V

=I

⎟

V

⎠

71.

19

.

204

.

F

1

42

−

1

H=

mA

OUT

2µA with the 0.6V feedback voltage makes R1~300k. A
close standard 1% resistor is 280k, and R2 is then 887k.

The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.

Figure 3 shows the complete schematic for this design
example.

Board Layout Considerations

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3548. These items are also illustrated graphically in
the layout diagram of Figure 4. Check the following in your
layout:

1. Does the capacitor CIN connect to the power VIN (Pin 3)
and GND (exposed pad) as close as possible? This capaci­tor provides the AC current to the internal power MOSFETs
and their drivers.

2. Are the C
C

returns current to GND and the (–) plate of CIN.

OUT

3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
terminated near GND (exposed pad). The feedback signals
VFB should be routed away from noisy components and
traces, such as the SW line (Pins 4 and 7), and its trace
should be minimized.

4. Keep sensitive components away from the SW pins. The
input capacitor CIN and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.

5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point and
should not share the high current path of CIN or C

6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con­nected to VIN or GND.

and L1 closely connected? The (–) plate of

OUT

and a ground sense line

OUT

OUT

.

12

3548f

LTC3548

U

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APPLICATIO S I FOR ATIO

V

= 2.5V*

IN

TO 5.5V

= 2.5V*

V

OUT2

AT 400mA

C3

4.7µF

C1, C2, C3: TAIYO YUDEN JMK212BJ106MG
C3: TAIYO YUDEN JMK212BJ475MG

*V

C1
10µF

RUN2 V

IN

MODE/SYNC

L2

4.7µH

R4

R3

887k

280k

CONNECTED TO VIN FOR VIN ≤ 2.8V (DROPOUT)

OUT

SW2

V

FB2

LTC3548

GND

R5
100k

RUN1

POR

SW1

V

FB1

L1: MURATA LQH32CN2R2M11
L2: MURATA LQH32CN4R7M23

L1

2.2µH

R1
301k

POWER-ON
RESET

C4, 33pFC5, 68pF

R2

604k

Figure 3. LTC3548 Typical Application

U

TYPICAL APPLICATIO S

Low Ripple Buck Regulators Using Ceramic Capacitors

V

= 2.5V

IN

TO 5.5V

V

= 1.8V

OUT2

AT 400mA

C1
10µF

L2

10µH

V

OUT1

AT 800mA

C2
10µF

RUN2 V

SW2

V

IN

C

= 1.8V

V

OUT2

C

OUT2

3548 F03

BOLD LINES INDICATE HIGH CURRENT PATHS

IN

R4 R2

RUN2 V

MODE/SYNC

L2

SW2

V

FB2

R3

IN

LTC3548

GND

RUN1

SW1

POR

V

L1

C4C5

FB1

R1

Figure 4. LTC3548 Layout Diagram (See Board Layout Checklist)

R5

L1

4.7µH

100k

POWER-ON
RESET

C4, 33pFC5, 68pF

V

= 1.2V

OUT1

AT 800mA

IN

LTC3548

RUN1

POR

SW1

3548 F04

V

OUT1

C

OUT1

V

R4

887k

442k

C1, C2, C3: TDK C2012X5R0J106M L1: SUMIDA CDRH2D18/HP-4R7NC

10µF

C3

FB2

MODE/SYNC

R3

V

FB1

GND

L2: SUMIDA CDRH2D18/HP-100NC

Efficiency vs Load Current

100

95

90

85

80

75

70

EFFICIENCY (%)

65

60

VIN = 3.3V
PULSE SKIP MODE

55

NO LOAD ON OTHER CHANNEL

50

10 100 1000

1.8V

1.2V

LOAD CURRENT (mA)

3548 TA03b

R1
604k

R2

604k

C2
10µF

3548 TA03

3548f

13

LTC3548

TYPICAL APPLICATIO S

V

= 3.6V

IN

TO 5.5V

= 3.3V

V

OUT2

AT 400mA

U

1mm Profile Core and I/O Supplies

C1*
10µF

L2

4.7µH

RUN2 V

MODE/SYNC

LTC3548

SW2

RUN1

IN

POR

L1

2.2µH

SW1

R5
100k

POWER-ON
RESET

C4, 33pFC5, 68pF

V

= 1.8V

OUT1

AT 800mA

V

C3

4.7µF

C1, C2: MURATA GRM219R60J106KE19
C3: MURATA GRM219R60J475KE19
L1: COILTRONICS LPO3310-222MX
L2: COILTRONICS LPO3310-472MX
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.

R4

887k

R3

196k

FB2

Efficiency vs Load Current

100

95

90

85

80

75

EFFICIENCY (%)

70

VIN = 5V

65

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

60

1

LOAD CURRENT (mA)

V

FB1

GND

10 100 1000

R1
301k

3.3V

1.8V

3548 TA08

R2

604k

C2
10µF

3548 TA07

14

3548f

PACKAGE DESCRIPTIO

U

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

0.675 ±0.05

R = 0.115

TYP

LTC3548

0.38 ± 0.10

106

5.23

(.206)

MIN

0.305 ± 0.038

(.0120 ± .0015)

TYP

3.50 ±0.05

1.65 ±0.05
(2 SIDES)2.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

2.38 ±0.05
(2 SIDES)

0.50
BSC

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1663)

2.794 ± 0.102
(.110 ± .004)

2.083 ± 0.102
(.082 ± .004)

0.50

(.0197)

RECOMMENDED SOLDER PAD LAYOUT

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

BSC

0.889 ± 0.127
(.035 ± .005)

3.20 – 3.45

(.126 – .136)

GAUGE PLANE

0.18

(.007)

0.254

(.010)

DETAIL “A”

DETAIL “A”

3.00
(4 SIDES)

0.75 ±0.05

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

3.00 ± 0.102
(.118 ± .004)

(NOTE 3)

4.90 ± 0.152

SEATING

PLANE

(.193 ± .006)

0.17 – 0.27

(.007 – .011)

TYP

(.043)

MAX

° – 6° TYP

0

0.53 ± 0.152

(.021 ± .006)

1.10

0.00 – 0.05

12

0.50

(.0197)

BSC

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

0.497 ± 0.076

7

6

45

(.0196 ± .003)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0.86

(.034)

REF

0.127 ± 0.076
(.005 ± .003)

MSOP (MSE) 0603

8910

3

2.38 ±0.10
(2 SIDES)

REF

15

0.25 ± 0.05

0.50 BSC

BOTTOM VIEW OF

EXPOSED PAD OPTION

1

10

1.65 ± 0.10

±0.10

(DD10) DFN 1103

2.06 ± 0.102
(.081 ± .004)

± 0.102

1.83
(.072 ± .004)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3548f

15

LTC3548

TYPICAL APPLICATIO

2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator

= 3.3V

V

OUT2

AT 100mA

+

C6
22µF

U

C3

4.7µF

V

= 2.8V

IN

TO 4.2V

D1

L2

15µH

M1

C5, 22pF

R4

887k

C1
10µF

196k

R3

RUN2 V

MODE/SYNC

LTC3548

SW2

V

FB2

GND

RUN1

IN

POR

SW1

V

R5
100k

POWER-ON
RESET

L1

2.2µH

C4, 33pF

FB1

R1
301k

R2

604k

V

OUT1

AT 800mA

C2
10µF

= 1.8V

L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-150M (D52LC SERIES)
M1: SILICONIX Si2302DS

Efficiency vs Load Current

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

1

4.2V

V

= 1.8V

OUT

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

LOAD CURRENT (mA)

2.8V

10 100 1000

Efficiency vs Load Current

90

80

70

60

EFFICIENCY (%)

50

40

V

= 3.3V

OUT

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

30

1

10 100 1000

LOAD CURRENT (mA)

C1, C2: TAIYO YUDEN JMK316BJ106ML
C3: MURATA GRM21BR60J475KA11B
C6: KEMET C1206C226K9PAC
D1: PHILIPS PMEG2010

4.2V

3.6V

2.8V

3548 TA05

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1878 600mA (I

Synchronous Step-Down DC/DC Converter I

LT1940 Dual Output 1.4A(I

High Efficiency Step-Down DC/DC Converter TSSOP-16E Package

LTC3252 Dual 250mA (I

Inductorless Step-Down DC/DC Converter I

LTC3405/LTC3405A 300mA (I

Synchronous Step-Down DC/DC Converters I

LTC3406/LTC3406B 600mA (I

Synchronous Step-Down DC/DC Converters I

LT3407/LT3407-2 600mA/1.5MHz, 800mA/2.25MHz 96% Efficiency, VIN: 2.5V to 5.5V, V

Dual Synchronous Step-Down DC/DC Converter I

LTC3411 1.25A (I

Synchronous Step Down DC/DC Converter I

LTC3412 2.5A (I

Synchronous Step Down DC/DC Converter I

LTC3414 4A (I

Synchronous Step Down DC/DC Converter ISD <1µA, TSSOP-28E Package

LTC3440 600mA (I

Synchronous Buck-Boost DC/DC Converter ISD <1µA, MSOP-10 Package

Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone] ● www.linear.com

), 550kHz, 95% Efficiency, VIN: 2.7V to 6V, V

OUT

, Constant 1.1MHz, VIN: 3V to 25V, V

OUT)

), 1MHz, Spread Spectrum 88% Efficiency, VIN: 2.7V to 5.5V, V

OUT

), 1.5MHz, 96% Efficiency, VIN: 2.5V to 5.5V, V

OUT

), 1.5MHz, 96% Efficiency, VIN: 2.5V to 5.5V, V

OUT

), 4MHz, 95% Efficiency, VIN: 2.5V to 5.5V, V

OUT

), 4MHz, 95% Efficiency, VIN: 2.5V to 5.5V, V

OUT

), 4MHz, 95% Efficiency, VIN: 2.25V to 5.5V, V

OUT

), 2MHz, 95% Efficiency, VIN: 2.5V to 5.5V, V

OUT

<1µA, MSOP-8 Package

SD

= 1.2V, IQ = 2.5mA, ISD = <1µA,

OUT(MIN)

= 60µA, ISD < 1µA, DFN-12 Package

Q

<1µA, ThinSOT Package

SD

<1µA, ThinSOT Package

SD

<1µA, MSE, DFN Package

SD

<1µA, MSOP-10 Package

SD

<1µA, TSSOP-16E Package

SD

OUT(MIN)

© LINEAR TECHNOLOGY CORPORATION 2005

3548 TA04

3.6V

3548 TA06

= 0.8V, IQ = 10µA,

= 0.9V to 1.6V,

OUT(MIN)

= 0.8V, IQ = 20µA,

OUT(MIN)

= 0.6V, IQ = 20µA,

OUT(MIN)

= 0.6V, IQ = 40µA,

OUT(MIN)

= 0.8V, IQ = 60µA,

OUT(MIN)

= 0.8V, IQ = 60µA,

OUT(MIN)

= 0.8V, IQ = 64µA,

OUT(MIN)

= 2.5V, IQ = 25µA,

OUT(MIN)

LT/TP 0305 500 • PRINTED IN USA

3548f