Page 1
FEATURES
LTC3412
2.5A, 4MHz, Monolithic
Synchronous Step-Down Regulator
U
DESCRIPTIO
■
High Efficiency: Up to 95%
■
2.5A Output Current
■
Low Quiescent Current: 62µA
■
Low R
■
Programmable Frequency: 300kHz to 4MHz
■
No Schottky Diode Required
■
±2% Output Voltage Accuracy
■
0.8V Reference Allows Low Output Voltage
■
Selectable Forced Continuous/Burst Mode Operation
Internal Switches: 85mΩ
DS(ON)
with Adjustable Burst Clamp
■
Synchronizable Switching Frequency
■
Low Dropout Operation: 100% Duty Cycle
■
Power Good Output Voltage Monitor
■
Overtemperature Protection
■
Available in 16-Lead Thermally Enhanced TSSOP
Package
U
APPLICATIO S
■
Portable Instruments
■
Battery-Powered Equipment
■
Notebook Computers
■
Distributed Power Systems
■
Cellular Telephones
■
Digital Cameras
The LTC®3412 is a high efficiency monolithic synchronous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.625V to 5.5V and provides an
adjustable regulated output voltage from 0.8V to 5V while
delivering up to 2.5A of output current. The internal
synchronous power switch with 85mΩ on-resistance
increases efficiency and eliminates the need for an external Schottky diode. Switching frequency is set by an
external resistor or can be sychronized to an external
clock. 100% duty cycle provides low dropout operation
extending battery life in portable systems. OPTI-LOOP
®
compensation allows the transient response to be optimized over a wide range of loads and output capacitors.
The LTC3412 can be configured for either Burst Mode
®
operation or forced continuous operation. Forced continuous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reducing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
the output voltage ripple to be adjusted according to the
requirements of the application. To further maximize
battery life, the P-channel MOSFET is turned on continuously in dropout (100% duty cycle).
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
V
IN
2.7V TO 5.5V
SVINPV
R
T
4.7M
470pF
15k
1000pF
Figure 1. 2.5V, 2.5A Step-Down Regulator
309k
100pF
RUN/SS
I
TH
SYNC/MODE
LTC3412
110k
75k
U
PGOOD
V
FB
IN
PGND
SGND
SW
392k
1µH
3412 F01
22µF
100µF
V
2.5V
2.5A
OUT
Efficiency vs Load Current
100
80
60
40
EFFICIENCY (%)
20
0
0.001
Burst Mode OPERATION
FORCED CONTINUOUS
0.1 10.01
LOAD CURRENT (A)
VIN = 3.3V
= 2.5V
V
OUT
10
3412 G01
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1
Page 2
LTC3412
WW
W
ABSOLUTE AXI U RATI GS
U
UUW
PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage ...................................– 0.3V to 6V
ITH, RUN, VFB Voltages ...............................–0.3V to V
SYNC/MODE Voltages ................................ –0.3V to V
IN
IN
SW Voltage ...................................–0.3V to (VIN + 0.3V)
Peak SW Sink and Source Current ......................... 6.5A
Operating Ambient Temperature
Range (Note 2) ....................................... – 40°C to 85°C
Junction Temperature (Note 5)............................. 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
TOP VIEW
1
SV
IN
2
PGOOD
3
I
TH
4
V
FB
5
R
T
SYNC/MODE
RUN/SS
EXPOSED PAD IS SGND (MUST BE SOLDERED TO PCB)
T
6
7
8
SGND
FE PACKAGE
16-LEAD PLASTIC TSSOP
= 125°C, θJA = 37.6°C/W, θJC = 10°C/W
JMAX
PV
16
IN
SW
15
SW
14
PGND
13
PGND
12
SW
11
SW
10
PV
9
IN
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ORDER PART
NUMBER
LTC3412EFE
FE PART
MARKING
3412EFE
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SV
IN
V
FB
I
FB
∆V
FB
V
LOADREG
∆V
PGOOD
R
PGOOD
I
Q
f
OSC
f
SYNC
R
PFET
R
NFET
I
LIMIT
V
UVLO
I
LSW
V
RUN
I
RUN
Signal Input Voltage Range 2.625 5.5 V
Regulated Feedback Voltage (Note 3) ● 0.784 0.800 0.816 V
Voltage Feedback Leakage Current 0.1 0.4 µA
Reference Voltage Line Regulation VIN = 2.7V to 5.5V (Note 3) ● 0.04 0.2 %/V
Output Voltage Load Regulation Measured in Servo Loop, V
Measured in Servo Loop, V
= 0.36V ● 0.02 0.2 %
ITH
= 0.84V ● –0.02 –0.2 %
ITH
Power Good Range ±7.5 ±9%
Power Good Pull-Down Resistance 120 200 Ω
Input DC Bias Current (Note 4)
Active Current V
= 0.78V, V
FB
Sleep VFB = 1V, V
Shutdown V
Switching Frequency R
RUN
OSC
= 0V, V
= 309kΩ 0.88 0.95 1.1 MHz
= 1V 250 330 µA
ITH
= 0V 62 80 µA
ITH
= 0V 0.02 1 µA
MODE
Switching Frequency Range (Note 6) 0.3 4 MHz
SYNC Capture Range (Note 6) 0.3 4 MHz
R
of P-Channel FET ISW = 1A 85 110 mΩ
DS(ON)
R
of N-Channel FET ISW = –1A 65 90 mΩ
DS(ON)
Peak Current Limit 4 5.4 A
Undervoltage Lockout Threshold 2.375 2.500 2.625 V
SW Leakage Current V
= 0V, VIN = 5.5V 0.1 1 µA
RUN
RUN Threshold 0.5 0.65 0.8 V
RUN/SS Leakage Current 1 µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3412E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3412 is tested in a feedback loop that adjusts V
to
FB
2
achieve a specified error amplifier output voltage (ITH).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
dissipation as follows: LTC3412: T
is calculated from the ambient temperature TA and power
J
= TA + PD (37.6°C/W).
J
Note 6: 4MHz operation is guaranteed by design and not production tested.
sn3412 3412fs
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UW
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load CurrentEfficiency vs Load Current Efficiency vs Load Current
100
80
60
40
EFFICIENCY (%)
20
0
0.001
Burst Mode OPERATION
FORCED CONTINUOUS
0.1 10.01
LOAD CURRENT (A)
VIN = 3.3V
= 2.5V
V
OUT
10
3412 G01
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
V
OUT
1MHz
10
Burst Mode OPERATION
0
0.001
VIN = 3.3V VIN = 5V
= 2.5V
0.1 10.01
LOAD CURRENT (A)
3412 G02
LTC3412
100
90
80
VIN = 3.3V VIN = 5V
70
60
50
40
EFFICIENCY (%)
30
20
10
10
0
0.001
V
= 2.5V
OUT
1MHz
FORCED CONTINUOUS
0.1 10.01
LOAD CURRENT (A)
10
3412 G03
98
LOAD = 100mA
96
94
92
EFFICIENCY (%)
90
88
86
OUT
V
LOAD = 2.5A
V
= 2.5V
OUT
1MHz
Burst Mode OPERATION
2.55 3.05 3.55 4.05 4.55 5.05
20mV/DIV
LOAD = 1A
INPUT VOLTAGE (V)
3412 G04
Efficiency vs FrequencyEfficiency vs Input Voltage
97
96
95
94
EFFICIENCY (%)
93
VIN = 3.3V
= 2.5V
V
92
OUT
LOAD = 1A
Burst Mode OPERATION
91
300
800 1300 1800 2300 2800 3300 3800
0.47µH
1µH
2.2µH
FREQUENCY (kHz)
Load Step Transient Forced
ContinuousBurst Mode Operation
OUT
V
100mV/DIV
3412 G05
Load Regulation
0.02
0.00
–0.02
–0.04
–0.06
OUT
/V
–0.08
OUT
–0.10
%∆V
–0.12
–0.14
–0.16
–0.18
0.5 1 1.5 2 2.5
0
LOAD CURRENT (A)
Load Step Transient Burst Mode
Operation
OUT
V
100mV/DIV
VIN = 3.3V
V
= 2.5V
OUT
3412 G06
L
I
200mA/DIV
VIN = 3.3V, V
LOAD = 50mA
OUT
4µs/DIV
= 2.5V
3412 G07
L
I
1A/DIV
20µs/DIV
VIN = 3.3V, V
LOAD STEP = NO LOAD TO 2.5A
OUT
= 2.5V
3412 G08
L
I
1A/DIV
VIN = 3.3V, V
LOAD STEP = 50mA TO 2.5A
OUT
= 2.5V
20µs/DIV
3412 G09
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LTC3412
R
OSC
(kΩ)
50
150 250 350 450 550 650 750 850 950
FREQUENCY (kHz)
3412 G15
4500
4000
3500
3000
2500
2000
1500
1000
500
0
VIN = 3.3V
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Start-Up, Burst Mode Operation
OUT
V
1V/DIV
RUN
V
1V/DIV
L
I
1A/DIV
1ms/DIV
VIN = 3.3V, V
LOAD = 1Ω
OUT
= 2.5V
3412 G10
Reference Voltage
vs Temperature
0.7960
VIN = 3.3V
0.7955
0.7950
0.7945
0.7940
0.7935
0.7930
REFERENCE VOLTAGE (V)
0.7925
0.7920
–45 –25 –5 15 35 55 75 95 115 120
TEMPERATURE (°C)
3412 G11
Switch On-Resistance
vs Input Voltage
120
100
80
60
40
ON-RESISTANCE (mΩ)
20
0
2.5 3
Switch On-Resistance
vs Temperature Switch Leakage vs Input Voltage Frequency vs R
120
VIN = 3.3V
110
100
PFET ON-RESISTANCE
90
80
70
60
NFET ON-RESISTANCE
50
ON-RESISTANCE (mΩ)
40
30
20
–20 0 20 40 60 80 100 120
–40
TEMPERATURE (°C)
3412 G13
2.5
2.0
1.5
1.0
LEAKAGE CURRENT (nA)
SYNCHRONOUS SWITCH
0.5
0
2.5 3
3.5 4 4.5 5 5.5
INPUT VOLTAGE (V)
MAIN SWITCH
3412 G14
PFET ON-RESISTANCE
NFET ON-RESISTANCE
3.5 4 4.5 5
INPUT VOLTAGE (V)
3412 G12
OSC
4
Frequency vs Input Voltage
1050
R = 309k
1040
1030
1020
1010
FREQUENCY (kHz)
1000
990
3 3.5 4 4.5 5 5.5
2.5
INPUT VOLTAGE (V)
3412 G16
Switching Frequency
vs Temperature
1010
VIN = 3.3V
1008
1006
1004
1002
1000
998
FREQUENCY (kHz)
996
994
992
990
–20 0 20 40 60 80 100 120
–40
TEMPERATURE (°C)
3412 G17
DC Supply Current
vs Input Voltage
350
300
250
200
150
DC SUPPLY CURRENT (µA)
100
50
3 3.5 4 4.5 5 5.5
2.5
ACTIVE
SLEEP
INPUT VOLTAGE (V)
3412 G18
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UW
INPUT VOLTAGE (V)
2.75
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
4.25 5.25
3412 G21
3.25 3.75
4.75
CURRENT LIMIT (A)
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Peak Inductor Current
DC Supply Current vs Temperature
350
VIN = 3.3V
300
250
200
150
100
SUPPLY CURRENT (µA)
50
0
–20 0 20 40 60 80 100 120
–40
ACTIVE
SLEEP
TEMPERATURE (°C)
3412 G19
vs Burst Clamp Voltage
4000
VIN = 3.3V
3500
3000
2500
2000
1500
1000
500
MINIMUM PEAK INDUCTOR CURRENT (mA)
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0 0.1
BURST CLAMP VOLTAGE (V)
LTC3412
Current Limit vs Input Voltage
3412 G20
PI FU CTIO S
SVIN (Pin 1): Signal Input Supply. Decouple this pin to
SGND with a capacitor. Normally SVIN is equal to PVIN.
SVIN can be greater than PVIN but keep the voltage
difference between SVIN and PVIN less than 0.5V.
PGOOD (Pin 2): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage is
not within ±7.5% of regulation point.
ITH (Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V to
1.4V with 0.2V corresponding to the zero-sense voltage
(zero current).
VFB (Pin 4): Feedback Pin. Receives the feedback voltage
from a resistive divider connected across the output.
RT (Pin 5): Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
SYNC/MODE (Pin 6): Mode Select and External Clock
Synchronization Input. To select forced continuous, tie to
SVIN. Connecting this pin to a voltage between 0V and 1V
selects Burst Mode operation with the burst clamp set to
the pin voltage.
UUU
RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3412. In shutdown
all functions are disabled drawing < 1µA of supply current.
A capacitor to ground from this pin sets the ramp time to
full output current.
SGND (Pin 8): Signal Ground. All small-signal components, compensation components and the exposed pad
on the bottom side of the IC should connect to this ground,
which in turn connects to PGND at one point.
PVIN (Pins 9, 16): Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 10, 11, 14, 15): Switch Node Connection to the
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
PGND (Pins 12, 13): Power Ground. Connect this pin
close to the (–) terminal of CIN and C
OUT
.
sn3412 3412fs
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LTC3412
UU
W
FU CTIO AL BLOCK DIAGRA
SGND
VOLTAGE
REFERENCE
0.8V
SV
IN
1
+
4
V
FB
0.74V
–
+
ERROR
AMPLIFIER
SYNC/MODE
–
+
RUNRUN/SS
7
0.86V
–
I
TH
3
+
–
–
+
OSCILLATOR
BCLAMP
BURST
COMPARATOR
SLOPE
COMPENSATION
RECOVERY
LOGIC
PMOS CURRENT
COMPARATOR
+
–
SLOPE
COMPENSATION
+
98
P-CH
N-CH
PV
IN
16
10
11
SW
14
15
PGOOD
2
NMOS
CURRENT
COMPARATOR
–
–
REVERSE
CURRENT
COMPARATOR
5
R
T
6
SYNC/MODE
+
3412 FBD
12
PGND
13
6
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OPERATIO
LTC3412
U
Main Control Loop
The LTC3412 is a monolithic, constant-frequency, current
mode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by
comparing the feedback signal from a resistor divider on
the VFB pin with an internal 0.8V reference. When the load
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the ITH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –2A for forced continuous mode and 0A for
Burst Mode operation.
The operating frequency is set by an external resistor
connected between the RT pin and ground. The practical
switching frequency can range from 300kHz to 4MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SVIN will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation but may be desirable
in some applications where it is necessary to keep switching harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage between 0V
to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the I
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the ITH pin drops. As the ITH voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top MOSFET is held
off and the ITH pin is disconnected from the output of the
error amplifier. The majority of the internal circuitry is also
turned off to reduce the quiescent current to 62µA while
the load current is solely supplied by the output capacitor.
When the output voltage drops, the ITH pin is reconnected
to the output of the error amplifier and the top power
MOSFET along with all the internal circuitry is switched
back on. This process repeats at a rate that is dependent
on the load demand.
Pulse skipping operation can be implemented by connecting the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
peak inductor current will be determined by the voltage on
the ITH pin until the ITH voltage drops below 200mV. At this
point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Frequency Synchronization
The internal oscillator of the LTC3412 can be synchronized
to an external clock connected to the SYNC/MODE pin. The
frequency of the external clock can be in the range of
300kHz to 4MHz. For this application, the oscillator timing
TH
sn3412 3412fs
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LTC3412
OPERATIO
U
resistor should be chosen to correspond to a frequency
that is 25% lower than the synchronization frequency.
During synchronization, the burst clamp is set to 0V and
each switching cycle begins at the falling edge of the
external clock signal.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3412 is designed to operate down to an input
supply voltage of 2.625V. One important consideration at
low input supply voltages is that the R
channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3412 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
DS(ON)
of the P-
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.8A, the top
power MOSFET will be held off and switching cycles will be
skipped until the inductor current falls to a safe level.
8
sn3412 3412fs
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LTC3412
U
WUU
APPLICATIO S I FOR ATIO
The basic LTC3412 application circuit is shown in Figure␣ 1. External component selection is determined by the
maximum load current and begins with the selection of the
inductor value and operating frequency followed by C
and C
OUT
.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance values and/or capacitance to
maintain low output ripple voltage.
The operating frequency of the LTC3412 is determined by
an external resistor that is connected between the RT pin
and ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
fHz
()
11
()
10
k
323 10
R
OSC
.•
=Ω−Ω
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412 imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns. Therefore, the minimum duty cycle is
equal to 100 • 110ns • f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ∆IL increases with higher VIN and decreases
with higher inductance.
∆=
I
L
V
OUT OUT
fL
1
−
V
V
IN
IN
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with
small ripple current. This, however, requires a large
inductor.
A reasonable starting point for selecting the ripple current
is ∆IL = 0.4(I
). The largest ripple current occurs at the
MAX
highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
V
L
=
OUT
fI
∆
LMAX
() ()
V
1
−
V
IN MAX
OUT
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation begins
when the peak inductor current falls below a level set by the
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, mollypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value but it is very dependent on
the inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
Kool Mµ is a registered trademark of Magnetics, Inc.
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LTC3412
U
WUU
APPLICATIO S I FOR ATIO
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate energy but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
CIN and C
The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent
large ripple voltage, a low ESR input capacitor sized for the
maximum RMS current should be used. RMS current is
given by:
II
RMS OUT MAX
This formula has a maximum at VIN = 2V
= I
/2. This simple worst-case condition is commonly
OUT
used for design because even significant deviations do not
offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design.
The selection of C
resistance (ESR) that is required to minimize voltage
ripple and load step transients, as well as the amount of
bulk capacitance that is necessary to ensure that the
Selection
OUT
V
=−
()
OUT
V
is determined by the effective series
OUT
IN
V
V
IN
OUT
1
, where I
OUT
RMS
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple, ∆V
∆≤∆ +
V I ESR
OUT L
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
8
fC
, is determined by:
OUT
1
OUT
10
sn3412 3412fs
Page 11
LTC3412
U
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APPLICATIO S I FOR ATIO
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
R
2
VV
=+
OUT
08 1
.
The resistive divider allows the VFB pin to sense a fraction
of the output voltage as shown in Figure 2.
Figure 2. Setting the Output Voltage
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than VIN by 1V,
Burst Mode operation is enabled. During Burst Mode
operation, the voltage on the SYNC/MODE pin determines
the burst clamp level which sets the minimum peak
inductor current, I
ing to the following equation:
IV V
BURST BURST
V
BURST
=−
()
is the voltage on the SYNC/MODE pin. I
be programmed in the range of 0A to 3.75A. For values of
V
of V
greater than 1V, I
BURST
less than 0.2V, I
BURST
load current drops, the peak inductor current decreases to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than I
, the burst clamp will force the peak inductor
BURST
current to remain equal to I
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
R
1
V
OUT
R2
V
FB
LTC3412
SGND
3412 F02
, for each switching cycle accord-
BURST
02
.
BURST
BURST
BURST
R1
375
.
A
08
.
V
is set at 3.75A. For values
is set at 0A. As the output
regardless of further
BURST
can
on the ITH pin will decrease. When the ITH voltage drops to
150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
I
is determined by the desired amount of output
BURST
voltage ripple. As the value of I
increases, the sleep
BURST
period between pulses and the output voltage ripple increase. The burst clamp voltage, V
, can be set by a
BURST
resistor divider from the VFB pin to the SGND pin as shown
in Figure 1.
Pulse skipping, which is a compromise between low output voltage ripple and efficiency, can be implemented by
connecting the SYNC/MODE pin to ground. This sets I
BURST
to 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator, and
the lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads,
pulse skipping allows only a few switching cycles to be
skipped while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3412’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external frequency should be set 25% higher than the frequency set
by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412 in a low
quiescent current shutdown state (IQ < 1µA).
sn3412 3412fs
11
Page 12
LTC3412
U
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APPLICATIO S I FOR ATIO
The LTC3412 contains an internal soft-start clamp that
gradually raises the clamp on ITH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on ITH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on ITH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
tRC
=
SS SS SS
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses.
The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current out
ln
V
VV
IN
IN
−
Seconds
()
.18
of VIN that is typically larger than the DC bias current. In
continuous mode, I
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In continuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
RSW = (R
The R
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to R
and multiply the result by the square of the average output
current.
Other losses including CIN and C
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3412 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3412 is running at high ambient temperature with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC3412 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
DS(ON)
DS(ON)TOP
for both the top and bottom MOSFETs can be
DS(ON)
GATECHG
and the duty cycle (DC) as follows:
=f(QT + QB) where QT and Q
)(DC) + (R
DS(ON)BOT
)(1 – DC)
ESR dissipative
OUT
B
L
12
sn3412 3412fs
Page 13
LTC3412
U
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APPLICATIO S I FOR ATIO
maximum junction temperature of the part. The temperature rise is given by:
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and θ
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + T
R
where TA is the ambient temperature.
As an example, consider the LTC3412 in dropout at an
input voltage of 3.3V, a load current of 2.5A and an
ambient temperature of 70°C. From the typical performance graph of switch resistance, the R
DS(ON)
of the P-
channel switch at 70°C is approximately 97mΩ. Therefore, power dissipated by the part is:
PD = (I
LOAD
2
)(R
) = (2.5A)2(97mΩ) = 0.61W
DS(ON)
For the TSSOP package, the θJA is 37.6°C/W. Thus the
junction temperature of the regulator is:
TJ = 70°C + (0.61W)(37.6°C/W) = 93°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (R
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ∆I
resistance of C
discharge C
(ESR), where ESR is the effective series
LOAD
OUT
generating a feedback error signal used by
OUT
the regulator to return V
During this recovery time, V
immediately shifts by an amount
OUT
. ∆I
also begins to charge or
LOAD
to its steady-state value.
OUT
can be monitored for
OUT
overshoot or ringing that would indicate a stability problem. The ITH pin external components and output capacitor shown in Figure 1 will provide adequate compensation
for most applications.
DS(ON)
JA
).
Design Example
As a design example, consider using the LTC3412 in an
application with the following specifications: VIN = 2.7V to
4.2V, V
= 2.5V, I
OUT
OUT(MAX)
= 2.5A, I
OUT(MIN)
= 10mA, f
= 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
323 10
Rkk
OSC
.•
=−=
110
11
10 313
6
•
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current at maximum VIN:
L
25
MHz A
11
()()..
V
.
1
V
25
42
=µ
V
−
101
.
H=
Using a 1µH inductor, results in a maximum ripple current
of:
25
∆=
L
C
will be selected based on the ESR that is required to
OUT
.
MHz H
11
()()..
V
1
µ
−
25
42
V
=I
A
101
.
V
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. In this application,
two tantalum capacitors will be used to provide the bulk
capacitance and a ceramic capacitor in parallel to lower the
total effective ESR. For this design, two 100µF tantalum
capacitors in parallel with a 10µF ceramic capacitor will be
used. CIN should be sized for a maximum current rating of:
V
25
.
IA
=
()
RMS RMS
42
.
V
42
.
25
.
V
−=25
1123.
A
.
V
Decoupling the PVIN and SVIN pins with a 22µF ceramic
capacitor and a 220µF tantalum capacitor is adequate for
most applications.
The burst clamp and output voltage can now be programmed by choosing the values of R1, R2 and R3. The
voltage on the MODE pin will be set to 0.32V by the resistor
divider consisting of R2 and R3. A burst clamp voltage of
sn3412 3412fs
13
Page 14
LTC3412
U
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APPLICATIO S I FOR ATIO
0.32V will set the minimum inductor current, I
follows:
375
.
V
IVV
If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
RR k
1
The last two equations shown result in the following
values for R2 and R3: R2 = 110k , R3 = 75k. The value of
R1 can now be determined by solving the equation shown
below:
1
Rk
A value of 392k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
=−
BURST
2 3 185
+=
+=
1 393
()
+=
R
2308
R
R
1
1852508
=
k
.
032
.
V
V
.
.
V
V
08
.
=032 02
563..
V
mA
BURST
, as
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3412. Check the following in your layout.
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3412. The exposed pad should
be connected to SGND.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PVIN, SVIN, V
in your system).
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between V
SGND.
, PGND, SGND, or any other DC rail
OUT
OUT
and
14
Top Side Bottom Side
Figure 3. LTC3412 Layout Diagram
sn3412 3412fs
Page 15
LTC3412
U
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APPLICATIO S I FOR ATIO
R
PG
100k
R3
75k
R
4.7M
R
ITH
7.15k
C
C
100pF
R2
110k
R
OSC
SS
309k
C
SS
470pF X7R
680pF X7R
C
ITH
*
TOKO D62CB A920CY-1ROM
**
SANYO POSCAP 4TPB100M
†
TAIYO YUDEN LMK325BJ106MN
††
SANYO POSCAP 2R5TPC220M
1
SV
IN
2
PGOODPGOOD
3
I
TH
4
V
FB
5
R
T
SYNC/MODE
6
7
RUN
8
SGND
C
FB
22pF X5R
R1 392k
LTC3412
PV
SW
SW
PGND
PGND
SW
SW
PV
V
IN
2.7V TO 4.2V
††
C
C
IN2
22µF
X5R 6.3V
220µF
3412 F04
IN1
L1*
1µH
C
OUT2
10µF
V
OUT
2.5V
2.5A
†
+
C
**
OUT1
100µF
×2
GND
16
IN
15
14
13
12
11
10
9
IN
Figure 4. Single Lithium-Ion to 2.5V, 2.5A Regulator at 1MHz, Burst Mode Operation Using POSCAPs
sn3412 3412fs
15
Page 16
LTC3412
TYPICAL APPLICATIO S
1000pF X7R
C
ITH
R3
75k
R
SS
4.7M
***TOKO D62CB A920CY-1ROM
TDK C4532X5R0J107M
U
2.5V, 2.5A Regulator Using All Ceramic Capacitors
C1 22pF X5R
R1 392k
C
IN1
C
IN2
22µF
X5R 6.3V
3412 F05
22µF
X5R 6.3V
L1*
1µH
R
ITH
15k
100pF
R
PG
100k
C
C
R2
110k
R
OSC
309k
C
SS
470pF X7R
1
SV
IN
2
PGOODPGOOD
3
I
TH
4
V
FB
5
R
T
6
SYNC/MODE
7
RUN
8
SGND
LTC3412
PV
SW
SW
PGND
PGND
SW
SW
PV
16
IN
15
14
13
12
11
10
9
IN
C
IN3
100µF
GND
**
C
100µF
V
IN
2.7V TO 5.5V
V
OUT
2.5V
2.5A
**
OUT
1.8V, 2.5A Step-Down Regulator at 1MHz, Burst Mode Operation
C1 22pF X5R
R1 232k
C
C
IN2
22µF**
IN1
22µF
C
560pF X7R
ITH
R3
75k
R
SS
4.7M
***SUMIDA CR431R0
AVX 12066D226MAT
R
10k
ITH
R
PG
100k
C2
47pF
R2
110k
R
OSC
309k
C
SS
470pF X7R
1
SV
IN
2
PGOODPGOOD
3
I
TH
4
V
FB
5
R
T
6
SYNC/MODE
7
RUN
8
SGND
LTC3412
PV
SW
SW
PGND
PGND
SW
SW
PV
16
IN
15
14
13
12
11
10
9
IN
**
L1
1µH*
3412 TA05
GND
V
3.3V
V
1.8V
2A
C
OUT
22µF
×2
IN
OUT
**
sn3412 3412fs
16
Page 17
TYPICAL APPLICATIO S
C
IN3
0.1µF
X5R
1000pF X7R
C
ITH
R
SS
4.7M
***VISHAY DALE IHLP-2525CZ-01 0.47
TDK C4532X5R0J107M
U
2.5V, 2.5A Low Output Noise Regulator at 2MHz
CFF 22pF X7R
R
IN
R
ITH
22.1k
5Ω
R
PG
100k
C1
56pF
R2
182k
R
OSC
137k
C
SS
470pF X7R
1
2
3
4
5
6
7
8
R1 392k
SV
IN
PGOODPGOOD
I
TH
LTC3412
V
FB
R
T
SYNC/MODE
RUN
SGND
PV
SW
SW
PGND
PGND
SW
SW
PV
C
IN2
100µF**
C
100µF
16
IN
15
14
13
12
11
10
9
IN
**
IN1
0.47µH*
L1
3412 TA06
GND
V
IN
3.3V
V
OUT
2.5V
2.5A
C
OUT
100µF
×2
LTC3412
**
Efficiency vs Load Current
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.01
2MHz, Low Noise
0.1 1 10
LOAD CURRENT (A)
3412 TA07
sn3412 3412fs
17
Page 18
LTC3412
TYPICAL APPLICATIO S
3.3V, 2.5A Step-Down Regulator at 1MHz, Forced Continuous Mode Operation
C
1000pF X7R
ITH
***PULSE P1166.162T
TDK C4532X5R0J107M
U
R
4.7M
V
IN
5V
C
**
L1*
1µH
3412 TA01
IN3
100µF
GND
V
OUT
3.3V
2.5A
C
OUT
100µF
**
C1 22pF X5R
R1 634k
C
IN1
C
IN2
22µF
X5R 6.3V
22µF
X5R 6.3V
1
SV
R
PG
100k
R
ITH
15k
C
C
100pF
R2
200k
R
OSC
309k
C
SS
SS
470pF X7R
IN
2
PGOODPGOOD
3
I
TH
4
V
FB
5
R
T
6
SYNC/MODE
7
RUN
8
SGND
LTC3412
PV
SW
SW
PGND
PGND
SW
SW
PV
16
IN
15
14
13
12
11
10
9
IN
Lithium-Ion to 3.3V, Single Inductor Buck-Boost Converter
C1
22pF
R1 576k
C
IN1
C
IN2
22µF
X5R 6.3V
22µF
X5R 6.3V
3412 F04
C
1000pF X7R
ITH
R3
75k
R
SS
4.7M
***TOKO D63CB
TDK C4532X5R0J107M
R
15k
ITH
100pF
R
PG
100k
C2
R2
110k
R
OSC
309k
C
SS
470pF X7R
1
SV
IN
2
PGOODPGOOD
3
I
TH
4
V
FB
5
R
T
6
SYNC/MODE
7
RUN
8
SGND
LTC3412
PV
SW
SW
PGND
PGND
SW
SW
PV
16
IN
15
14
13
12
11
10
9
IN
L1*
2µH
C
**
IN3
100µF
×2
GND
D1
DIODES, INC.
B320A
M1
SILICONIX
Si2302DS
GND
VINMAXIMUM I
2.7V 800mA
3V 900mA
3.5V 1.05A
4.2V 1.2A
C
OUT
100µF
V
2.7V TO 4.2V
V
3.3V
**
OUT
IN
OUT
18
sn3412 3412fs
Page 19
PACKAGE DESCRIPTIO
2.74
(.108)
U
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
16 1514 13 12 11
LTC3412
10 9
6.60 ±0.10
4.50 ±0.10
RECOMMENDED SOLDER PAD LAYOUT
0.09 – 0.20
(.0036 – .0079)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
0.45 ±0.05
0.65 BSC
4.30 – 4.50*
(.169 – .177)
0.45 – 0.75
(.018 – .030)
MILLIMETERS
(INCHES)
2.74
(.108)
1.05 ±0.10
1345678
2
° – 8°
0
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
2.74
(.108)
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
FE16 (BA) TSSOP 0203
6.40
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
sn3412 3412fs
19
Page 20
LTC3412
TYPICAL APPLICATIO
C
1000pF X7R
ITH
4.7M
***TOKO D62CB A920CY-1ROM
TDK C4532X5R0J107M
U
2.5V, 2.5A Step-Down Regulator Synchronized to 1.25MHz
C1 22pF X5R
R1 392k
C
IN1
C
IN2
22µF
X5R 6.3V
3412 TA02
22µF
X5R 6.3V
L1*
1µH
R
SS
CC 100pF
R2 182k
R
OSC
R
PG
100k
R
ITH
15k
309k
1.25MHz
EXT CLOCK
C
SS
470pF X7R
1
SV
IN
2
PGOODPGOOD
3
I
TH
4
V
FB
5
R
T
6
SYNC/MODE
7
RUN
8
SGND
LTC3412
PV
SW
SW
PGND
PGND
SW
SW
PV
16
IN
15
14
13
12
11
10
9
IN
C
IN3
100µF
GND
**
V
IN
2.7V TO 5.5V
V
OUT
2.5V
2.5A
C
**
OUT1
100µF
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ThinSOT is a trademark of Linear Technology Corporation.
LT/TP 0203 2K • PRINTED IN USA
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
TM
sn3412 3412fs
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