Datasheet LT1792 Datasheet (Linear Technology)

FEATURES

LT1792

Low Noise, Precision,

JFET Input Op Amp

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DESCRIPTIO

■

100% Tested Low Voltage Noise: 6nV/√Hz Max

■

A Grade 100% Temperature Tested

■

Voltage Gain: 1.2 Million Min

■

Offset Voltage Over Temp: 800µV Max

■

Gain-Bandwidth Product: 5.6MHz Typ

■

Guaranteed Specifications with ±5V Supplies

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APPLICATIO S

■

Photocurrent Amplifiers

■

Hydrophone Amplifiers

■

High Sensitivity Piezoelectric Accelerometers

■

Low Voltage and Current Noise Instrumentation Amplifier Front Ends

■

Two and Three Op Amp Instrumentation Amplifiers

■

Active Filters

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TYPICAL APPLICATIO

The LT®1792 achieves a new standard of excellence in noise performance for a JFET op amp. The 4.2nV/√Hz voltage noise combined with low current noise and picoampere bias currents make the LT1792 an ideal choice for amplifying low level signals from high impedance capacitive transducers.

The LT1792 is unconditionally stable for gains of 1 or more, even with load capacitances up to 1000pF. Other key features are 600µV VOS and a voltage gain of over 4 million. Each individual amplifier is 100% tested for voltage noise, slew rate and gain bandwidth.

The design of the LT1792 has been optimized to achieve true precision performance with an industry standard pinout in the SO-8 package. Specifications are also provided for ±5V supplies.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Low Noise Hydrophone Amplifier with DC Servo

2

3

–5V TO –15V

R8 100M

R7 1M

< 70°C

A

5V TO 15V

–

LT1792

+

R6

100k

7

6

4

C2

0.47µF

6

LT1097

R1* 100M

R2 200Ω

HYDRO-

PHONE

DC OUTPUT ≤ 2.5mV FOR T OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20) C1 ≈ C

T

R3

3.9k

C1*

C

T

≈ 100pF TO 5000pF; R4C2 > R8CT; *OPTIONAL

1kHz Input Noise Voltage Distribution

VS = ±15V

40

= 25°C

T

A

OUTPUT

R4 1M

–

2

R5 1M

3

+

1792 TA01

30

20

PERCENT OF UNITS (%)

10

0

3.8 4.2

3.6

4.0

INPUT VOLTAGE NOISE (nV/√Hz)

270 OP AMPS TESTED

5.0

4.6 5.6

4.8

4.4

5.2

5.4

1792 TA02

1

LT1792

A

W

O

LUTEXI TIS

S

A

WUW

U

ARB

G

(Note 1)

Supply Voltage ..................................................... ±20V

Differential Input Voltage ...................................... ±40V

Input Voltage (Equal to Supply Voltage)............... ±20V

Output Short-Circuit Duration ........................ Indefinite

Operating Temperature Range............... –40°C to 85°C

WU

/

PACKAGE

VOS ADJ

–IN A +IN A

–

V

JMAX

O

RDER I FOR ATIO

TOP VIEW

1 2

A

3 4

N8 PACKAGE 8-LEAD PDIP

= 140°C, θJA = 130°C/W

ORDER PART

NUMBER

NC

8

+

V

7

OUT

6

ADJ

V

5

OS

LT1792ACN8 LT1792CN8 LT1792AIN8 LT1792IN8

Specified Temperature Range

Commercial (Note 8) ......................... –40°C to 85°C

Industrial ........................................... –40°C to 85°C

Storage Temperature Range................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................ 300°C

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ORDER PART

NUMBER

LT1792ACS8 LT1792CS8 LT1792AIS8 LT1792IS8

S8 PART MARKING

1792A 1792

VOS ADJ

–IN A +IN A

TOP VIEW

1

2

3

–

V

4

S8 PACKAGE

8-LEAD PLASTIC SO

T

= 160°C, θJA = 190°C/WT

JMAX

NC

8

V+

A

7

OUT

6

ADJ

V

5

OS

1792AI 1792I

Consult factory for Military grade parts.

LECTRICAL C CHARA TERIST

E

SYMBOL PARAMETER CONDITIONS (Note 2) MIN TYP MAX MIN TYP MAX UNITS

V

OS

I

OS

I

B

e

n

i

n

R

IN

C

IN

V

CM

CMRR Common Mode Rejection Ratio V PSRR Power Supply Rejection Ratio VS = ±4.5V to ±20V 88 105 83 98 dB

Input Offset Voltage 0.2 0.6 0.2 0.8 mV

V

S

Input Offset Current Warmed Up (Note 3) 100 400 100 400 pA Input Bias Current Warmed Up (Note 3) 300 800 300 800 pA Input Noise Voltage 0.1Hz to 10Hz 2.4 2.4 µV Input Noise Voltage Density fO = 10Hz 8.3 8.3 nV/√Hz

f

O

Input Noise Current Density fO = 10Hz, fO = 1000Hz (Note 4) 10 10 fA/√Hz Input Resistance

Differential Mode 10 Common Mode V

Input Capacitance 14 14 pF

Input Voltage Range (Note 5) 13.0 13.5 13.0 13.5 V

CM

V

CM

V

S

CM

ICS

T

= 25°C, VS = ±15V, V

A

= ±5V 0.4 1.0 0.4 1.3 mV

= 1000Hz 4.2 6.0 4.2 6.0 nV/√Hz

= –10V to 8V 10 = 8V to 11V 10

= ±5V 27 27 pF

–10.5 –11.0 –10.5 –11.0 V

= –10V to 13V 85 105 82 100 dB

= 0V, unless otherwise noted. (Note 9)

CM

LT1792AC/LT1792AI

11 11 10

LT1792C/LT1792I

10 10 10

P-P

11 11 10

Ω Ω Ω

2

LECTRICAL C CHARA TERIST

E

ICS

T

= 25°C, VS = ±15V, V

A

= 0V, unless otherwise noted.

CM

LT1792

LT1792AC/LT1792AI

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

A

VOL

V

OUT

SR Slew Rate RL ≥ 2k (Note 7) 2.3 3.4 2.3 3.4 V/µs GBW Gain-Bandwidth Product fO = 100kHz 4.0 5.6 4.0 5.6 MHz I

S

Large-Signal Voltage Gain VO = ±12V, RL = 10k 1200 4800 1000 4500 V/mV

V

= ±10V, RL = 1k 600 4000 500 3000 V/mV

O

Output Voltage Swing RL = 10k ±13.0 ±13.2 ±13.0 ±13.2 V

= 1k ±12.0 ±12.3 ±12.0 ±12.3 V

R

L

Supply Current 4.2 5.20 4.2 5.20 mA

= ±5V 4.2 5.15 4.2 5.15 mA

V

S

Offset Voltage R Adjustment Range

(to VEE) = 10k 10 10 mV

POT

The ● denotes specifications which apply over the temperature range 0°C ≤ TA ≤ 70°C. VS = ±15V, V

LT1792C/LT1792I

= 0V,

CM

unless otherwise noted. (Note 9)

LT1792AC LT1792C

SYMBOL PARAMETER CONDITIONS (Note 2) MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V

OS

∆Temp I

OS

I

B

V

CM

CMRR Common Mode Rejection Ratio V PSRR Power Supply Rejection Ratio VS = ±4.5V to ±20V ● 85 99 81 97 dB A

VOL

V

OUT

SR Slew Rate RL ≥ 2k (Note 7) ● 2.1 3.1 2.1 3.1 V/µs GBW Gain-Bandwidth Product fO = 100kHz ● 3.2 4.5 3.2 4.5 MHz I

S

Input Offset Voltage ● 0.4 0.8 0.8 2.7 mV

= ±5V ● 0.6 1.2 1.2 3.2 mV

V

S

Average Input Offset (Note 6) ● 410 740 µV/°C Voltage Drift

Input Offset Current ● 180 500 180 500 pA Input Bias Current ● 500 1800 500 1800 pA

Input Voltage Range ● 12.9 13.4 12.9 13.4 V

= –10V to 12.9V ● 81 104 79 99 dB

CM

Large-Signal Voltage Gain VO = ±12V, RL = 10k ● 900 3600 800 3400 V/mV

V

= ±10V, RL = 1k ● 500 2600 400 2400 V/mV

O

Output Voltage Swing RL = 10k ● ±12.9 ±13.2 ±12.9 ±13.2 V

= 1k ● ±11.9 ±12.15 ±11.9 ±12.15 V

R

L

Supply Current ● 4.2 5.30 4.2 5.30 mA

= ±5V ● 4.2 5.25 4.2 5.25 mA

V

S

● –10.0 –10.8 –10.0 –10.8 V

3

LT1792

LECTRICAL C CHARA TERIST

E

–40°C ≤ TA ≤ 85°C. V

SYMBOL PARAMETER CONDITIONS (Note 2) MIN TYP MAX MIN TYP MAX UNITS

V

OS

∆V

OS

∆Temp I

OS

I

B

V

CM

CMRR Common Mode Rejection Ratio V PSRR Power Supply Rejection Ratio VS = ±4.5V to ±20V ● 83 98 79 96 dB A

VOL

V

OUT

SR Slew Rate RL ≥ 2k ● 2.0 3.0 2.0 3.0 V/µs GBW Gain-Bandwidth Product fO = 100kHz ● 2.9 4.3 2.9 4.3 MHz I

S

Input Offset Voltage ● 0.5 1.0 1.2 3.7 mV

Average Input Offset (Note 6) ● 410 740 µV/°C Voltage Drift

Input Offset Current ● 300 800 300 800 pA Input Bias Current ● 1200 4000 1200 4000 pA

Input Voltage Range ● 12.6 13.0 12.6 13.0 V

Large-Signal Voltage Gain VO = ±12V, RL = 10k ● 850 3300 750 3000 V/mV

Output Voltage Swing RL = 10k ● ±12.8 ±13.1 ±12.8 ±13.1 V

Supply Current ● 4.2 5.40 4.2 5.40 mA

= ±15V, VCM = 0V, unless otherwise noted. (Notes 8, 9)

S

V

R

V

ICS

= ±5V ● 0.8 1.4 1.5 4.2 mV

S

= –10V to 12.6V ● 80 103 78 98 dB

CM

= ±10V, RL = 1k ● 400 2200 300 2000 V/mV

O

= 1k ● ±11.8 ±12.1 ±11.8 ±12.1 V

L

= ±5V ● 4.2 5.35 4.2 5.35 mA

S

The ● denotes specifications which apply over the temperature range

LT1792AC/LT1792AI LT1792C/LT1792I

● –10.0 –10.5 –10.0 –10.5 V

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: Typical parameters are defined as the 60% yield of parameter distributions of individual amplifiers.

Note 3: Warmed-up I temperature of 32°C from 25°C measurements and 32°C characterization data.

Note 4: Current noise is calculated from the formula:

i

= (2qIB)

n

where q = 1.6 • 10 swamps the contribution of current noise.

Note 5: Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of 2.3mV (A grade), to 2.8mV (C grade).

and IOS readings are extrapolated to a chip

B

1/2

–19

coulomb. The noise of source resistors up to 200M

Note 6: This parameter is not 100% tested. Note 7: Slew rate is measured in AV = –1; input signal is ±7.5V, output

measured at ±2.5V. Note 8: The LT1792AC and LT1792C are guaranteed to meet specified

performance from 0°C to 70°C and are designed, characterized and expected to meet these extended temperature limits, but are not tested at –40°C and 85°C. The LT1792I is guaranteed to meet the extended temperature limits. The LT1792AC and LT1792AI grade are 100% temperature tested for the specified temperature range.

Note 9: The LT1792 is measured in an automated tester in less than one second after application of power. Depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed-up chip temperature can be 10°C to 50°C higher than the ambient temperature.

4

LPER

F

0.1Hz to 10Hz Voltage Noise

VOLTAGE NOISE (1µV/DIV)

2

0

4

TIME (SEC)

O

6

R

LT1792

UW

ATYPICA

8

1792 G01

CCHARA TERIST

E

C

Voltage Noise vs Frequency

100

VS = ±15V

= 25°C

T

A

10

1/f CORNER

RMS VOLTAGE NOISE DENSITY (nV/√Hz)

1

10

110

30Hz

FREQUENCY (Hz)

ICS

100 10k1k

1792 G02

Voltage Noise vs Chip Temperature

10

VS = ±15V

9 8 7

6

5 4 3 2

VOLTAGE NOISE (AT 1kHz) (nV/√Hz)

1

0

–75

–50 0

–25

TEMPERATURE (°C)

100

25

75

50

125

1792 G03

Input Bias and Offset Current Over the Common Mode Range

400

TA = 25°C

= ±15V

V

S

NOT WARMED UP

300

200

BIAS CURRENT

100

INPUT BIAS AND OFFSET CURRENTS (pA)

0

–15

OFFSET CURRENT

–10 –5 0 5

COMMON-MODE RANGE (V)

Common Mode Rejection Ratio vs Frequency

120

100

80

60

40

20

COMMON MODE REJECTION RATIO (dB)

0

1k 100k 1M 10M

10k

FREQUENCY (Hz)

10 15

1792 G22

TA = 25°C V

= ±15V

S

1792 G06

Input Bias and Offset Current vs Chip Temperature

100

VS = ±15V

30

10

3

1

0.3

0.1

0.03

INPUT BIAS AND OFFSET CURRENT (nA)

0.01 –75

–25 25 75–50 0 50 100

TEMPERATURE (°C)

I

B

Power Supply Rejection Ratio vs Frequency

120

100

80

60

40

20

POWER SUPPLY REJECTION RATIO (dB)

0

10

–PSRR

1k 10k 100k

100

FREQUENCY (Hz)

+PSRR

I

OS

1792 G04

TA = 25°C

1M 10M

1792 G07

V

COMMON MODE LIMIT

V

125

Common Mode Limit vs Temperature

+

0 –0.5 –1.0 –1.5 –2.0

4.0

3.5

3.0

REFERRED TO POWER SUPPLY (V)

2.5

–

+2.0

–60

–20

V+ = 5V TO 20V

V– = –5V TO –20V

20

TEMPERATURE (°C)

Voltage Gain vs Frequency

180 160 140 120 100

80

60

VOLTAGE GAIN (dB)

40

20

0

–20

0.01

1

FREQUENCY (Hz)

100

60

10k

100

1M

140

1792 G05

100M

1792 G08

5

LT1792

LPER

Gain and Phase Shift vs Frequency

50

40

30

20

10

VOLTAGE GAIN (dB)

PHASE

GAIN

UW

R

F

O

ATYPICA

TA = 25°C

= ±15V

V

S

= 10pF

C

L

CCHARA TERIST

E

C

Small-Signal Transient Response

80

100

PHASE SHIFT (DEG)

120

140

160

20mV/DIV

ICS

Large-Signal Transient Response

5V/DIV

0

–10

0.1

1 10 100

FREQUENCY (MHz)

Output Voltage Swing vs Load Current

V+ –0.8

–1.0 –1.2 –1.4 –1.6

2.0

1.8

1.6

1.4

OUTPUT VOLTAGE SWING (V)

1.2

–

V

+1.0

–8

–10

I

SINK

VS = ±5V TO ±20V

125°C

–55°C

–6 –4

OUTPUT CURRENT (mA)

Warm-Up Drift

90

VS = ±15V

= 25°C

T

A

75

60

25°C

–55°C

25°C

048

–2

SO-8 PACKAGE

125°C

2

6

1792 G09

I

SOURCE

1792 G12

180

200

10

AV = 1

= 10pF

C

L

= ±15V, ±5V

V

S

1µs/DIV

Capacitive Load Handling

50

VS = ±15V

= 25°C

T

A

≥ 10k

R

L

40

= 100mV

V

O

AV = 10 R

F

30

C

F

20

OVERSHOOT (%)

10

0

0.1

P-P

= 10k = 20pF

A

= 1

V

= 10

A

V

1

CAPACITIVE LOAD (pF)

10

THD and Noise vs Frequency for Noninverting Gain

1

ZL = 2k  15pF

= 20V

V

O

P-P

= 1, 10, 100

A

V

MEASUREMENT BANDWIDTH

0.1 = 10Hz TO 80kHz

100

1000

10000

1792 G13

1792 G10

AV = 1 C

= 10pF

L

= 2k

R

L

= ±15V

V

S

5µs/DIV

Slew Rate and Gain-Bandwidth Product vs Temperature

6

VS = ±15V

5

4

3

SLEW RATE (V/µs)

2

1

0

–75

–25 25

–50 0

TEMPERATURE (°C)

GBWP

50

THD and Noise vs Frequency for Inverting Gain

1

ZL = 2k  15pF

= 20V

V

O

P-P

= –1, –10, – 100

A

V

MEASUREMENT BANDWIDTH

0.1 = 10Hz TO 80kHz

1792 G11

GAIN-BANDWIDTH PRODUCT (f

12

10

100

1792 G14

125

8

6

4

2

0

O

= 100kHz) (MHz)

SR

75

CHANGE IN OFFSET VOLTAGE (µV)

6

45

30

15

0

234

1

TIME AFTER POWER ON (MINUTES)

N8 PACKAGE

56

1792 G15

0.01

0.001

TOTAL HARMONIC DISTROTION + NOISE (%)

0.0001 20 100

AV = 100

A

= 10 AV = 1

V

NOISE FLOOR

FREQUENCY (Hz)

1k 20k10k

1792 G16

0.01

0.001

TOTAL HARMONIC DISTROTION + NOISE (%)

0.0001 20 100

AV = –100

AV = –10

NOISE FLOOR

1k 20k10k

FREQUENCY (Hz)

AV = –1

1792 G17

LPER

TEMPERATURE (°C)

–75

3

SUPPLY CURRENT (mA)

4

–25 5025

100

1792 G21

5

–50 0

75

125

VS = ±15V

VS = ±5V

LT1792

UW

R

F

O

ATYPICA

CCHARA TERIST

E

C

ICS

THD and Noise vs Output Amplitude for Noninverting Gain

1

ZL = 2k  15pF, fO = 1kHz A

= 1, 10, 100

V

MEASUREMENT BANDWIDTH = 10Hz TO 22kHz

0.1

AV = 100

0.01

AV = 10

0.001

TOTAL HARMONIC DISTORTION + NOISE (%)

0.0001

0.3

AV = 1

11030

OUTPUT SWING (V

P-P

Short-Circuit Output Current vs Temperature

40

V

= ±15V

S

35

30

SINK SOURCE

25

THD and Noise vs Output Amplitude for Inverting Gain

1

ZL = 2k  15pF, fO = 1kHz

= –1, –10, – 100

A

V

MEASUREMENT BANDWIDTH = 10Hz TO 22kHz

0.1

AV = –100

0.01 AV = –10

0.001

TOTAL HARMONIC DISTORTION + NOISE (%)

0.0001

)

1792 G18

0.3

AV = –1

11030 OUTPUT SWING (V

P-P

)

1792 G19

Supply Current vs Temperature

PPLICATI

A

The LT1792 may be inserted directly into OPA124, AD743, AD745, AD645, AD544 and AD820 sockets with improved noise performance. Offset nulling will be compatible with these devices with the wiper of the potentiometer tied to the negative supply (Figure 1a). No appreciable change in offset voltage drift with temperature will occur when the device is nulled with a potentiometer ranging from 10k to 200k. Finer adjustments can be made with resistors in series with the potentiometer (Figure 1b).

Being a low voltage noise JFET op amp, the LT1792 can replace many bipolar op amps that are used in amplifying low level signals from high impedance transducers. The

20

OUTPUT CURRENT (mA)

15

10

–75

–50 0

–25 5025

TEMPERATURE (°C)

U

O

I FOR ATIO

S

75

100

125

1792 G20

WU

U

15V

–

2

3

7

6

+

1

5

50k

–15V

4

= ±10mV

∆V

OS

1792 F01a

15V

–

2

3

7

6

+

1 10k

5

10k

50k

–15V

4

∆V

= ±1mV

OS

1792 F01b

(b)(a)

Figure 1

7

LT1792

SOURCE RESISTANCE (Ω)

100

1

10

1k

1k 100M

1792 F02

100k

100

10M10k 1M

RESISTOR NOISE ONLY

INPUT NOISE VOLTAGE (nV/

√

H



z)

Vn = AV √V

n2(OP AMP)

+ 4kTR + 2qIB • R

2

+

–

C

S

R

S

V

O

C

S

R

S

LT1007

LT1792

LT1007*

LT1792*

SOURCE RESISTANCE = 2RS = R * PLUS RESISTOR

†

PLUS RESISTOR  1000pF CAPACITOR

LT1792

†

LT1007

†

PPLICATI

A

U

O

I FOR ATIO

S

WU

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best bipolar op amps, with higher current noise, will eventually lose out to the LT1792 when transducer impedance increases. The low voltage noise of the LT1792 allows it to surpass most single JFET op amps available. For the best performance versus area available anywhere, the LT1792 is offered in the SO-8 surface mount package with no degradation in performance.

The low voltage and current noise offered by the LT1792 makes it useful in a wide range of applications, especially where high impedance, capacitive transducers are used such as hydrophones, precision accelerometers and photo diodes. The total output noise in such a system is the gain times the RMS sum of the op amp input referred voltage noise, the thermal noise of the transducer, and the op amp bias current noise times the transducer impedance. Figure 2 shows total input voltage noise versus source resistance. In a low source resistance (<5k) application the op amp voltage noise will dominate the total noise. This means the LT1792 will beat out any JFET op amp, only the lowest noise bipolar op amps have the edge at low source resistances. As the source resistance increases from 5k to 50k, the LT1792 will match the best bipolar op amps for noise performance, since the thermal noise of the transducer (4kTR) begins to dominate the total noise. A further increase in source resistance, above 50k, is where the op amp’s current noise component (2qI R

) will eventually dominate the total noise. At these

TRANS

B

high source resistances, the LT1792 will out perform the lowest noise bipolar op amp due to the inherently low

Figure 2. Comparison of LT1792 and LT1007 Total Output 1kHz Voltage Noise Versus Source Resistance

current noise of FET input op amps. Clearly, the LT1792 will extend the range of high impedance transducers that can be used for high signal-to-noise ratios. This makes the LT1792 the best choice for high impedance, capacitive transducers.

The high input impedance JFET front end makes the LT1792 suitable in applications where very high charge sensitivity is required. Figure 3 illustrates the LT1792 in its inverting and noninverting modes of operation. A charge amplifier is shown in the inverting mode example; here the gain depends on the principal of charge conservation at

8

R1

TRANSDUCER

CSR

R

B

1792 F03

R

F

C

F

–

+

OUTPUT

CB = CFC RB = RFR

Q = CV; = I = C

S

dQ

dV

dt

R2

C

B

R

B

S

–

+

CB ≅ C

S

RB = R

S

RS > R1 OR R2

OUTPUT

CSR

TRANSDUCER

S

C

B

Figure 3. Noninverting and Inverting Gain Configurations

LT1792

U

O

PPLICATI

A

the input of the LT1792. The charge across the transducer capacitance, CS, is transferred to the feedback capacitor CF, resulting in a change in voltage, dV, equal to dQ/CF. The gain therefore is CF/CS. For unity gain, the CF should equal the transducer capacitance plus the input capacitance of the LT1792 and RF should equal RS. In the noninverting mode example, the transducer current is converted to a change in voltage by the transducer capacitance; this voltage is then buffered by the LT1792 with a gain of 1 + R1/R2. A DC path is provided by RS, which is either the transducer impedance or an external resistor. Since RS is usually several orders of magnitude greater than the parallel combination of R1 and R2, RB is added to balance the DC offset caused by the noninverting input bias current and RS. The input bias currents, although small at room temperature, can create significant errors at higher temperature, especially with transducer resistances of up to 100M or more. The optimum value for RS is determined by equating the thermal noise (4kTRS) to the current noise times RS, [(2qIB) • RS], resulting in RB = 2VT/IB (VT = 26mV at 25°C). A parallel capacitor, CB, is used to cancel the phase shift caused by the op amp input capacitance and RB.

Reduced Power Supply Operation

The LT1792 can be operated from ±5V supplies for lower power dissipation resulting in lower IB and noise at the

I FOR ATIO

S

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U

expense of reduced dynamic range. To illustrate this benefit, let’s take the following example:

An LT1792CS8 operates at an ambient temperature of 25°C with ±15V supplies, dissipating 159mW of power (typical supply current = 5.3mA). The SO-8 package has a

θJA of 190°C/W, which results in a die temperature in-

crease of 30.2°C or a room temperature die operating temperature of 55.2°C. At ±5V supplies, the die temperature increases by only one third of the previous amount or

10.1°C resulting in a typical die operating temperature of only 35.1°C. A 20 degree reduction of die temperature is achieved at the expense of a 20V reduction in dynamic range.

To take full advantage of a wide input common mode range, the LT1792 was designed to eliminate phase reversal. Referring to the photographs shown in Figure 4, the LT1792 is shown operating in the follower mode (AV = 1) at ±5V supplies with the input swinging ±5.2V. The output of the LT1792 clips cleanly and recovers with no phase reversal. This has the benefit of preventing lock-up in servo systems and minimizing distortion components.

High Speed Operation

The low noise performance of the LT1792 was achieved by making the input JFET differential pair large to maximize the first stage gain. Increasing the JFET geometry

INPUT: ±5.2V Sine Wave LT1792 Output

1792 F04a 1792 F03b

Figure 4. Voltage Follower with Input Exceeding the Common Mode Range ( V

= ±5V)

S

9

LT1792

PPLICATI

A

U

O

I FOR ATIO

S

WU

U

also increases the parasitic gate capacitance, which if left unchecked, can result in increased overshoot and ringing. When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance and capacitance (RS, CS), and the amplifier input capacitance (CIN = 27pF). In low gain configurations and with RS and RF in the kilohm range (Figure 5), this pole can create excess phase shift and even oscillation. A small capacitor (CF) in parallel with RF eliminates this problem. With RS(CS + CIN) = RFCF, the effect of the feedback pole is completely removed.

U

O

PPLICATITYPICAL

SA

Accelerometer Amplifier with DC Servo

C1

1250pF

C

F

R

F

–

C

IN

R

C

S

+

OUTPUT

1792 F05

Figure 5

ACCELEROMETER

B & K MODEL 4381

OR EQUIVALENT

V

IN

TYPICAL OFFSET ≈ 0.8mV 1% TOLERANCES FOR V = – 6dB AT f = 16.3Hz LOWER RESISTOR VALUES WILL RESULT IN LOWER THERMAL NOISE AND LARGER CAPACITORS

R1

100M

5V TO 15V

–

2

LT1792

+

3

–5V TO –15V

7

4

C2

R3

2µF

2k

–

2

6

LT1792

+

3

6

C3 2µF

R2

18k

R4

20M

R5

20M

1792 TA03

10Hz Fourth Order Chebyshev Lowpass Filter (0.01dB Ripple)

R1

237k

IN

= 10V

R2

237k

R3

249k

C2 100nF

, V

= –121dB AT f > 330Hz

P-P

OUT

2

3

–

LT1792

+

15V

–15V

C1

33nF

7

6

4

R4

154k

R5

154k

R6

249k

C4 330nF

2

3

R4C2 = R5C3 > R1 (1 + R2/R3) C1 OUTPUT = 0.8mV/pC* = 8.0mV/g** DC OUTPUT ≤ 2.7mV OUTPUT NOISE = 6nV/√Hz AT 1kHz

*PICOCOULOMBS **g = EARTH’S GRAVITATIONAL CONSTANT

OUTPUT

C3

10nF

–

6

LT1792

+

V

OUT

1792 TA06

10

LT1792

U

O

C

D

2N3904

SA

Low Noise Light Sensor with DC Servo

C1

2pF

–

2

LT1792

+

D2 1N914

R5

R4

1k

–

V

3

D1

1N914

R3

1k

R2C2 > C1R1

= PARASITIC PHOTODIODE CAPACITANCE

C

D

= 100mV/µWATT FOR 200nm WAVE LENGTH

V

O

330mV/µWATT FOR 633nm WAVE LENGTH

6

R1 1M

6

+

V

7

LT1792

4

–

V

C2

0.022µF

–

+

2

3

OUTPUT

R2

100k

1792 TA05

PPLICATITYPICAL

HAMAMATSU

S1336-5BK

Paralleling Amplifiers to Reduce Voltage Noise

3

51Ω

2

3

2

3

2

+

LT1792

–

+

LT1792

–

+

LT1792

–

An

A2

15V

A1

–15V

1k

7

4

1k

6

10k

15V

1k

6

1k

6

1. ASSUME VOLTAGE NOISE OF LT1792 AND 51Ω SOURCE RESISTOR = 4.3nV/√Hz

2. GAIN WITH n LT1792s IN PARALLEL = n × 200

3. OUTPUT NOISE = √n × 200 × 4.3nV/√Hz

4. INPUT REFERRED NOISE =

5. NOISE CURRENT AT INPUT INCREASES √n TIMES

2

3

–

LT1792

+

–15V

7

6

OUTPUT

4

OUTPUT NOISE = 4.3

n × 200 √n

nV/√H z

1792 TA04

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

11

LT1792

PPLICATITYPICAL

Light Balance Detection Circuit Unity-Gain Buffer with Extended

I

1

PD1

I

2

PD2

V

= 1M × (I1 – I2)

OUT

PD1

PD2 = HAMAMATSU S1336-5BK

,

WHEN EQUAL LIGHT ENTERS PHOTODIODES, V

2pF TO 8pF

–

LT1792

+

PACKAGEDESCRIPTI

1M

R1

C1

O

U SA

Load Capacitance Drive Capability

–

LT1792

+

V

IN

C1 = CL ≤ 0.1µF OUTPUT SHORT-CIRCUIT CURRENT (∼ 30mA) WILL LIMIT THE RATE AT WHICH THE VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS

dV

I = C

()

dt

OUT

1792 TA07

< 3mV.

V

OUT

U

Dimensions in inches (millimeters) unless otherwise noted.

R2 1k

C1

R1

33Ω

C

L

1792 TA08

V

OUT

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.400* (10.160)

MAX

876

0.255 ± 0.015* (6.477 ± 0.381)

1234

0.300 – 0.325

(7.620 – 8.255)

0.065

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

(1.651)

TYP

0.100 ± 0.010

(2.540 ± 0.254)

0.045 – 0.065

(1.143 – 1.651)

5

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.020

(0.508)

MIN

N8 1197

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

DIMENSION DOES NOT INCLUDE MOLD FLASH.

*

MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH.

**

INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

0.016 – 0.050

0.406 – 1.270

0°– 8° TYP

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

0.189 – 0.197* (4.801 – 5.004)

8

1

7

2

6

3

5

0.150 – 0.157** (3.810 – 3.988)

4

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

TYP

SO8 0996

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1113 Low Noise Dual JFET Op Amp Dual Version of LT1792, V LT1169 Low Noise Dual JFET Op Amp Dual Version of LT1793, IB = 10pA, V LT1793 Low Noise Single Op Amp Lower IB Version of LT1792, IB = 10pA, V

Linear Technology Corporation

12

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear-tech.com

= 4.5nV/√Hz

NOISE

1792f LTTP 0599 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1999

= 6nV/√Hz

NOISE