Datasheet LT1767EMS8-1.8, LT1767EMS8, LT1767EMS8E-5, LT1767EMS8E-3.3, LT1767EMS8E-2.5 Datasheet (Linear Technology)
...
FEATURES
■
1.5A Switch in a Small MSOP Package
■
Constant 1.25MHz Switching Frequency
■
High Power Exposed Pad (MS8E) Package
■
Wide Operating Voltage Range: 3V to 25V
■
High Efficiency 0.22Ω Switch
■
1.2V Feedback Reference Voltage
■
Fixed Output Voltages of 1.8V, 2.5V, 3.3V, 5V
■
2% Overall Output Tolerance
■
Uses Low Profile Surface Mount Components
■
Low Shutdown Current: 6µA
■
Synchronizable to 2MHz
■
Current Mode Loop Control
■
Constant Maximum Switch Current Rating at All Duty
Cycles*
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APPLICATIO S
■
DSL Modems
■
Portable Computers
■
Wall Adapters
■
Battery-Powered Systems
■
Distributed Power
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
Monolithic 1.5A, 1.25MHz
Step-Down Switching Regulators
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DESCRIPTIO
The LT®1767 is a 1.25MHz monolithic buck switching
regulator. A high efficiency 1.5A, 0.22Ω switch is included
on the die together with all the control circuitry required to
complete a high frequency, current mode switching regulator. Current mode control provides fast transient response and excellent loop stability.
New design techniques achieve high efficiency at high
switching frequencies over a wide operating range. A low
dropout internal regulator maintains consistent performance over a wide range of inputs from 24V systems to LiIon batteries. An operating supply current of 1mA improves efficiency, especially at lower output currents.
Shutdown reduces quiescent current to 6µA. Maximum
switch current remains constant at all duty cycles. Synchronization allows an external logic level signal to increase the internal oscillator from 1.4MHz to 2MHz.
The LT1767 is available in an 8-pin MSOP fused leadframe
package and a low thermal resistance exposed pad package. Full cycle-by-cycle short-circuit protection and thermal shutdown are provided. High frequency operation
allows the reduction of input and output filtering components and permits the use of chip inductors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
*Patent Pending
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TYPICAL APPLICATIO
12V to 3.3V Step-Down Converter
C2
0.1µF
V
IN
12V
C3
2.2µF
CERAMIC
*MAXIMUM OUTPUT CURRENT IS SUBJECT TO THERMAL DERATING.
OPEN
OR
HIGH
= ON
V
IN
SYNC
BOOST
LT1767-3.3
GND
V
SW
FBSHDN
V
C
C
C
1.5nF
R
C
4.7k
CMDSH-3
5µH
D1
UPS120
Efficiency vs Load Current
95
D2
90
L1
OUTPUT
3.3V
1.2A*
C1
10µF
CERAMIC
1767 TA01
85
80
EFFICIENCY (%)
75
70
0.2 0.4 0.6 0.8 1 1.2 1.4
0
LOAD CURRENT (A)
VIN = 10V
= 5V
V
OUT
VIN = 5V
= 3.3V
V
OUT
sn1767 1767fas
1767 TA01a
1
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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ABSOLUTE MAXIMUM RATINGS
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(Note 1)
Input Voltage .......................................................... 25V
BOOST Pin Above SW ............................................ 20V
Max BOOST Pin Voltage .......................................... 35V
SHDN Pin ............................................................... 25V
FB Pin Voltage .......................................................... 6V
FB Pin Current ....................................................... 1mA
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PACKAGE/ORDER INFORMATION
ORDER PART NUMBER
TOP VIEW
BOOST
1
V
2
IN
3
SW
4
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
= 125°C, θJA = 110°C/W
JMAX
GROUND PIN CONNECTED
TO LARGE COPPER AREA
Consult LTC Marketing for parts specified with wider operating temperature ranges.
8
7
6
5
SYNC
V
C
FB
SHDN
LT1767EMS8
LT1767EMS8-1.8
LT1767EMS8-2.5
LT1767EMS8-3.3
LT1767EMS8-5
MS8 PART MARKING
LTLS
LTWG
LTWD
LTWE
LTWF
SYNC Pin Current .................................................. 1mA
Operating Junction Temperature Range (Note 2)
LT1767E .......................................... –40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART NUMBER
BOOST
1
V
2
IN
3
SW
4
GND
MS8E PACKAGE
8-LEAD PLASTIC MSOP
T
= 125°C, θJA = 40°C/W
JMAX
EXPOSED GND PAD
CONNECTED TO LARGE
COPPER AREA ON PCB
TOP VIEW
8
7
6
5
SYNC
V
C
FB
SHDN
LT1767EMS8E
LT1767EMS8E-1.8
LT1767EMS8E-2.5
LT1767EMS8E-3.3
LT1767EMS8E-5
MS8E PART MARKING
LTZG
LTZH
LTZJ
LTZK
LTZL
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER CONDITION MIN TYP MAX UNITS
Maximum Switch Current Limit TA = 0°C to 125°C 1.5 2 3 A
TA = < 0°C 1.3 3 A
Oscillator Frequency 3.3V < VIN < 25V 1.1 1.25 1.4 MHz
● 1.1 1.5 MHz
Switch On Voltage Drop ISW = –1.5A, 0°C ≤ TA ≤ 125°C and –1.3A, TA < 0°C 330 400 mV
● 500 mV
VIN Undervoltage Lockout (Note 3) ● 2.47 2.6 2.73 V
VIN Supply Current VFB = V
Shutdown Supply Current V
Feedback Voltage 3V < VIN < 25V, 0.4V < VC < 0.9V LT1767 (Adj) 1.182 1.2 1.218 V
FB Input Current LT1767 (Adj) ● – 0.25 –0.5 µA
SHDN
(Note 3) ● 1.176 1.224 V
+ 17% ● 1 1.3 mA
NOM
= 0V, VIN = 25V, VSW = 0V 6 20 µA
● 45 µA
LT1767-1.8 ● 1.764 1.8 1.836 V
LT1767-2.5 ● 2.45 2.5 2.55 V
LT1767-3.3 ● 3.234 3.3 3.366 V
LT1767-5 ● 4.9 5 5.1 V
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LT1767/LT1767-1.8/
TEMPERATURE (°C)
–50
–25 0 25 50 75 100 125
FREQUENCY (MHz)
1767 G03
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
LT1767-2.5/LT1767-3.3/LT1767-5
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER CONDITION MIN TYP MAX UNITS
FB Input Resistance LT1767-1.8 ● 10.5 15 21 kΩ
LT1767-2.5
LT1767-3.3 ● 19 27.5 39 kΩ
LT1767-5
Error Amp Voltage Gain 0.4V < VC < 0.9V 150 350
Error Amp Transconductance ∆IVC = ±10µA ● 500 850 1300 µMho
VC Pin Source Current VFB = V
VC Pin Sink Current VFB = V
– 17% ● 80 120 160 µA
NOM
+ 17% ● 70 110 180 µA
NOM
VC Pin to Switch Current Transconductance 2.5 A/V
VC Pin Minimum Switching Threshold Duty Cycle = 0% 0.35 V
VC Pin 1.5A ISW Threshold 0.9 V
Maximum Switch Duty Cycle VC = 1.2V, ISW = 400mA 85 90 %
Minimum Boost Voltage Above Switch ISW = –1.5A, 0°C ≤ TA ≤ 125°C and –1.3A, TA < 0°C ● 1.8 2.7 V
Boost Current ISW = –0.5A (Note 4) ● 10 15 mA
ISW = –1.5A, 0°C ≤ TA ≤ 125°C and –1.3A, TA < 0°C (Note 4) ● 30 45 mA
SHDN Threshold Voltage ● 1.27 1.33 1.40 V
SHDN Input Current (Shutting Down) SHDN = 60mV Above Threshold ● –7 –10 –13 µA
SHDN Threshold Current Hysteresis SHDN = 100mV Below Threshold ● 4710 µA
SYNC Threshold Voltage 1.5 2.2 V
SYNC Input Frequency 1.5 2 MHz
SYNC Pin Resistance I
= 1mA 20 kΩ
SYNC
● 14.7 21 30 kΩ
● 29 42 60 kΩ
● 80 %
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1767E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls.
TYPICAL PERFORMANCE CHARACTERISTICS
FB VOLTAGE (V)
Note 3: Minimum input voltage is defined as the voltage where the internal
regulator enters lockout. Actual minimum input voltage to maintain a
regulated output will depend on output voltage and load current. See
Applications Information.
Note 4: Current flows into the BOOST pin only during the on period of the
switch cycle.
UW
FB vs Temperature (Adj) Switch On Voltage Drop Oscillator Frequency
1.22
1.21
1.20
1.19
1.18
–50
–25 0 25 50 75 100 125
TEMPERATURE (°C)
1767 G01
400
350
300
250
200
150
SWITCH VOLTAGE (mV)
100
50
0
0 0.5
SWITCH CURRENT (A)
125°C
25°C
–40°C
1 1.5
1767 G02
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LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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TYPICAL PERFOR A CE CHARACTERISTICS
SHDN Threshold vs Temperature SHDN Supply Current vs V
1.40
1.38
1.36
1.34
SHDN THRESHOLD (V)
1.32
1.30
–50
–25 0 25 50 75 100 125
TEMPERATURE (°C)
1767 G04
7
SHDN = 0V
6
5
4
3
CURRENT (µA)
IN
V
2
1
0
0 5 10 15 20 25 30
VIN (V)
IN
1767 G05
SHDN IP Current vs Temperature
–12
–10
–8
–6
–4
SHDN INPUT (µA)
–2
0
–25 0 25 50 75 100 125
–50
TEMPERATURE (°C)
Minimum Input Voltage for 2.5V Out SHDN Supply Current Input Supply Current
3.5
3.3
3.1
2.9
INPUT VOLTAGE (V)
2.7
300
VIN = 15V
250
200
150
CURRENT (µA)
IN
100
V
50
1200
1000
800
600
CURRENT (µA)
IN
400
V
200
MINIMUM
VOLTAGE
SHUTTING DOWN
STARTING UP
1767 G06
INPUT
2.5
0.001 0.01
LOAD CURRENT (A)
Current Limit Foldback
2.0
1.5
SWITCH CURRENT
1.0
0.5
SWITCH PEAK CURRENT (A)
0
0 0.2
FB CURRENT
0.4 0.6 0.8 1 1.2
FEEDBACK VOLTAGE (V)
0.1 1
1767 G07
1767 G10
0
0.2 0.4 0.6 0.8 1 1.2 1.4
0
SHUTDOWN VOLTAGE (V)
1767 G08
Maximum Load Current,
V
= 5V
OUT
40
FB INPUT CURRENT (µA)
30
20
10
0
1.5
1.3
1.1
0.9
OUTPUT CURRENT (A)
0.7
0.5
0 5 10 15 20 25
INPUT VOLTAGE (V)
L = 4.7µH
L = 2.2µH
L = 1.5µH
1767 G11
0
0 5 10 15 20 25 30
INPUT VOLTAGE (V)
Maximum Load Current,
V
= 2.5V
OUT
1.5
1.3
1.1
OUTPUT CURRENT (A)
0.9
0.7
05
10 15 20 25
INPUT VOLTAGE (V)
L = 4.7µH
L = 2.2µH
L = 1.5µH
sn1767 1767fas
1767 G09
1767 G12
4
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PIN FUNCTIONS
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
FB: The feedback pin is used to set output voltage using an
external voltage divider that generates 1.2V at the pin with
the desired output voltage. The fixed voltage 1.8V, 2.5V,
3.3V and 5V versions have the divider network included
internally and the FB pin is connected directly to the
output. If required, the current limit can be reduced during
start up or short-circuit when the FB pin is below 0.5V (see
the Current Limit Foldback graph in the Typical Performance Characteristics section). An impedance of less
than 5kΩ (adjustable part only) at the FB pin is needed for
this feature to operate.
BOOST: The BOOST pin is used to provide a drive voltage,
higher than the input voltage, to the internal bipolar NPN
power switch. Without this added voltage, the typical
switch voltage loss would be about 1.5V. The additional
boost voltage allows the switch to saturate and voltage
loss approximates that of a 0.22Ω FET structure.
VIN: This is the collector of the on-chip power NPN switch.
This pin powers the internal circuitry and internal regulator. At NPN switch on and off, high dI/dt edges occur on
this pin. Keep the external bypass capacitor and catch
diode close to this pin. All trace inductance in this path will
create a voltage spike at switch off, adding to the V
voltage across the internal NPN.
GND: The GND pin acts as the reference for the regulated
output, so load regulation will suffer if the “ground” end of
the load is not at the same voltage as the GND pin of the
IC. This condition will occur when load current or other
currents flow through metal paths between the GND pin
and the load ground point. Keep the ground path short
between the GND pin and the load and use a ground plane
CE
when possible. Keep the path between the input bypass
and the GND pin short. The GND pin of the MS8 package
is directly attached to the internal tab. This pin should be
attached to a large copper area to improve thermal
resistance. The exposed pad of the MS8E package is also
connected to GND. This should be soldered to a large
copper area to improve its thermal resistance.
VSW: The switch pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the switch
pin negative during switch off time. Negative voltage must
be clamped with an external catch diode with a VBR <0.8V.
SYNC: The sync pin is used to synchronize the internal
oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 20% and
80% duty cycle. The synchronizing range is equal to
operating frequency, up to 2MHz. See Synchronization
section in Applications Information for details. When not
in use, this pin should be grounded.
SHDN: The shutdown pin is used to turn off the regulator
and to reduce input drain current to a few microamperes.
The 1.33V threshold can function as an accurate undervoltage lockout (UVLO), preventing the regulator from
operating until the input voltage has reached a predetermined level. Float or pull high to put the regulator in the
operating mode.
VC: The VC pin is the output of the error amplifier and the
input of the peak switch current comparator. It is normally
used for frequency compensation, but can do double duty
as a current clamp or control loop override. This pin sits
at about 0.35V for very light loads and 0.9V at maximum
load. It can be driven to ground to shut off the output.
initial
sn1767 1767fas
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LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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BLOCK DIAGRAM
The LT1767 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
+
0.01Ω
–
CURRENT
SENSE
AMPLIFIER
VOLTAGE GAIN = 40
V
2
IN
2.5V BIAS
REGULATOR
INTERNAL
V
CC
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capacitor and diode. A comparator connected to the shutdown
pin disables the internal regulator, reducing supply
current.
8
SYNC
SHUTDOWN
COMPARATOR
5
SHDN
SLOPE COMP
1.25MHz
OSCILLATOR
Σ
0.35V
+
CURRENT
COMPARATOR
S
FLIP-FLOP
R
R
S
DRIVER
CIRCUITRY
–
7µA
–
+
PARASITIC DIODES
1.33V
FORWARD BIAS
–
3µA
+
1.2V
V
7
C
AMPLIFIER
= 850µMho
g
m
ERROR
DO NOT
1
BOOST
Q1
POWER
SWITCH
3
6
4
1767 F01
V
SW
FB
GND
Figure 1. Block Diagram
sn1767 1767fas
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LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
FB RESISTOR NETWORK
If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required, the
respective fixed option part, -1.8, -2.5, -3.3 or -5, should be
used. The FB pin is tied directly to the output; the necessary
resistive divider is already included on the part. For other
voltage outputs, the adjustable part should be used and an
external resistor divider added. The suggested resistor (R2)
from FB to ground is 10k. This reduces the contribution of
FB input bias current to output voltage to less than 0.25%.
The formula for the resistor (R1) from V
RV
212
=
R
1
12 2025
−µ
.(.)
LT1767
AMPLIFIER
VCGND
INPUT CAPACITOR
Step-down regulators draw current from the input supply in
pulses. The rise and fall times of these pulses are very fast.
The input capacitor is required to reduce the voltage ripple
this causes at the input of LT1767 and force the switching
current into a tight local loop, thereby minimizing EMI. The
RMS ripple current can be calculated from:
IIVVVV
RIPPLE RMS
()
Higher value, lower cost ceramic capacitors are now available in smaller case sizes. These are ideal for input bypassing since their high frequency capacitive nature removes
most ripple current rating and turn-on surge problems. At
higher switching frequency, the energy storage requirement of the input capacitor is reduced so values in the range
of 1µF to 4.7µF are suitable for most applications. Y5V or
similar type ceramics can be used since the absolute value
−
OUT
()
RA
ERROR
.
V
SW
1.2V
+
FB
–
Figure 2. Feedback Network
=−
OUT OUT IN OUT IN
()
OUT
R1
R2
10k
/
+
to FB is:
OUTPUT
1767 F02
2
of capacitance is less important and has no significant
effect on loop stability. If operation is required close to the
minimum input required by the output of the LT1767, a
larger value may be required. This is to prevent excessive
ripple causing dips below the minimum operating voltage,
resulting in erratic operation.
If tantalum capacitors are used, values in the 22µF to 470µF
range are generally needed to minimize ESR and meet ripple
current and surge ratings. Care should be taken to ensure
the ripple and surge ratings are not exceeded. The AVX TPS
and Kemet T495 series are surge rated. AVX recommends
derating capacitor operating voltage by 2:1 for high surge
applications.
OUTPUT CAPACITOR
Unlike the input capacitor, RMS ripple current in the output
capacitor is normally low enough that ripple current rating
is not an issue. The current waveform is triangular, with an
RMS value given by:
VVV
029.
OUT IN OUT
I
RIPPLE RMS
()
The LT1767 will operate with both ceramic and tantalum
output capacitors. Ceramic capacitors are generally chosen
for their small size, very low ESR (effective series resistance), and good high frequency operation, reducing output ripple voltage. Their low ESR removes a useful zero in
the loop frequency response, common to tantalum capacitors. To compensate for this, the VC loop compensation
pole frequency must typically be reduced by a factor of 10.
Typical ceramic output capacitors are in the 1µF to 10µF
range. Since the absolute value of capacitance defines the
pole frequency of the output stage, an X7R or X5R type
ceramic, which have good temperature stability, is recommended.
Tantalum capacitors are usually chosen for their bulk
capacitance properties, useful in high transient load applications. ESR rather than capacitive value defines output
ripple at 1.25MHz. Typical LT1767 applications require a
tantalum capacitor with less than 0.3Ω ESR at 22µF to
500µF, see Table 2.
()
=
LfV
()()( )
−
()
IN
sn1767 1767fas
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LT1767/LT1767-1.8/
IP−
()
−
()
()()( )
VVV
LfV
OUT IN OUT
IN
2
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
Table 2. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E Case Size ESR (Max, Ω) Ripple Current (A)
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
AVX TAJ 0.7 to 0.9 0.4
D Case Size
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
C Case Size
AVX TPS 0.2 (typ) 0.5 (typ)
Figure 3 shows a comparison of output ripple for a ceramic
and tantalum capacitor at 200mA ripple current.
V
USING 47µF, 0.1Ω
OUT
TANTALUM CAPACITOR
(10mV/DIV)
V
USING 2.2µF
OUT
CERAMIC CAPACITOR
(10mV/DIV)
and reduces the current at which discontinuous operation
occurs. The following formula gives maximum output
current for continuous mode operation, implying that the
peak to peak ripple (2x the term on the right) is less than
the maximum switch current.
Continuous Mode
I
OUT MAX
Discontinuous operation occurs when
I
OUT DIS
For VIN = 8V, V
I
OUT MAX
=
()
()
V
OUT
=
()
()
()()
2
Lf
= 5V and L = 3.3µH,
OUT
15
=−
.
2 3 3 10 1 25 10 8
()()
58 5
−
()
()
−
.• . •
66
()
V
SW
(5V/DIV)
0.2µs/DIV
Figure 3. Output Ripple Voltage Waveform
INDUCTOR CHOICE AND MAXIMUM OUTPUT
CURRENT
Maximum output current for a buck converter is equal to
the maximum switch rating (IP) minus one half peak to
peak inductor current. In past designs, the maximum
switch current has been reduced by the introduction of
slope compensation. Slope compensation is required at
duty cycles above 50% to prevent an affect called
subharmonic oscillation (see Application Note 19 for
details). The LT1767 has a new circuit technique that
maintains a constant switch current rating at all duty
cycles. (Patent Pending)
For most applications, the output inductor will be in the
1µH to 10µH range. Lower values are chosen to reduce the
physical size of the inductor, higher values allow higher
output currents due to reduced peak to peak ripple current,
1767 F03
=− =
15 023 127
.. .
Note that the worst case (minimum output current available) condition is at the maximum input voltage. For the
same circuit at 15V, maximum output current would be
only 1.1A.
When choosing an inductor, consider maximum load
current, core and copper losses, allowable component
height, output voltage ripple, EMI, fault current in the
inductor, saturation, and of course, cost. The following
procedure is suggested as a way of handling these somewhat complicated and conflicting requirements.
1. Choose a value in microhenries from the graphs of
maximum load current. Choosing a small inductor with
lighter loads may result in discontinuous mode of
operation, but the LT1767 is designed to work well in
either mode.
Assume that the average inductor current is equal to
load current and decide whether or not the inductor
must withstand continuous fault conditions. If maximum load current is 0.5A, for instance, a 0.5A inductor
may not survive a continuous 2A overload condition.
Also, the instantaneous application of input or release
from shutdown, at high input voltages, may cause
A
sn1767 1767fas
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LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
saturation of the inductor. In these applications, the
soft-start circuit shown in Figure 10 should be used.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current,
especially with smaller inductors and lighter loads, so
don’t omit this step. Powdered iron cores are forgiving
because they saturate softly, whereas ferrite cores
saturate abruptly. Other core materials fall somewhere
in between.
VVV
II
=+
PEAK OUT
VIN = Maximum input voltage
f = Switching frequency, 1.25MHz
3. Decide if the design can tolerate an “open” core geometry like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid
to prevent EMI problems. This is a tough decision
because the rods or barrels are temptingly cheap and
small and there are no helpful guidelines to calculate
when the magnetic field radiation will be a problem.
Table 3
PART NUMBER VALUE (uH) I
Coiltronics
TP1-2R2 2.2 1.3 0.188 1.8
TP2-2R2 2.2 1.5 0.111 2.2
TP3-4R7 4.7 1.5 0.181 2.2
TP4- 100 10 1.5 0.146 3.0
Murata
LQH1C1R0M04 1.0 0.51 0.28 1.8
LQH3C1R0M24 1.0 1.0 0.06 2.0
LQH3C2R2M24 2.2 0.79 0.1 2.0
LQH4C1R5M04 1.5 1.0 0.09 2.6
Sumida
CD73- 100 10 1.44 0.080 3.5
CDRH4D18-2R2 2.2 1.32 0.058 1.8
CDRH5D18-6R2 6.2 1.4 0.071 1.8
CDRH5D28-100 10 1.3 0.048 2.8
OUT IN OUT
2
−
()
LfV
()()( )
SAT
IN
(Amps) DCR (Ω) HEIGHT (mm)
4. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology’s applications department if you feel uncertain about the final
choice. They have experience with a wide range of
inductor types and can tell you about the latest developments in low profile, surface mounting, etc.
CATCH DIODE
The suggested catch diode (D1) is a UPS120 Schottky, or
its Motorola equivalent, MBRM120LTI/MBRM130LTI. It
is rated at 2A average forward current and 20V/30V
reverse voltage. Typical forward voltage is 0.5V at 1A. The
diode conducts current only during switch off time. Peak
reverse voltage is equal to regulator input voltage. Average
forward current in normal operation can be calculated
from:
IVV
I
D AVG
()
BOOST␣ PIN
For most applications, the boost components are a 0.1µF
capacitor and a CMDSH-3 diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately V
stage. The output driver requires at least 2.7V of headroom throughout the on period to keep the switch fully
saturated. However, the output stage discharges the boost
capacitor during the on time. If the output voltage is less
than 3.3V, it is recommended that an alternate boost
supply is used. The boost diode can be connected to the
input, although, care must be taken to prevent the 2x V
boost voltage from exceeding the BOOST pin absolute
maximum rating. The additional voltage across the switch
driver also increases power loss, reducing efficiency. If
available, an independent supply can be used with a local
bypass capacitor.
A 0.1µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
OUT IN OUT
=
−
()
V
IN
above VIN to drive the output
OUT
IN
sn1767 1767fas
9
LT1767/LT1767-1.8/
R
VV
A
R
V
VV
R
A
HL
H
1
7
2
133
133
1
3
=
−
µ
=
−
()
+µ
.
.
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
suitable, but the ESR should be <1Ω to ensure it can be
fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
700ns on-time, 50mA boost current, and 0.7V discharge
ripple. This value is then guard banded by 2x for secondary
factors such as capacitor tolerance, ESR and temperature
effects. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve
circuit operation or efficiency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start up operation.
SHUTDOWN AND UNDERVOLTAGE LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1767. Typically, UVLO is used in situations where
the input supply is
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
V
IN
R1
R2
C1
current limited
LT1767
IN
3µA
SHDN
7µA
1.33V
, or has a relatively high
V
SW
V
CC
GND
OUTPUT
+
VH – Turn-on threshold
VL – Turn-off threshold
Example: switching should not start until the input is
above 4.75V and is to stop if the input falls below 3.75V.
VH = 4.75V
VL = 3.75V
475 375
=
1
R
=
2
R
−
VV
..
µ
7
A
−
475 133
VV
..
()
143
133
.
k
V
=
143
+µ
k
49 4
k
=
.
3
A
Keep the connections from the resistors to the SHDN pin
short and make sure that the interplane or surface capacitance to the switching nodes are minimized. If high resistor values are used, the SHDN pin should be bypassed with
a 1nF capacitor to prevent coupling problems from the
switch node.
Figure 4. Undervoltage Lockout
An internal comparator will force the part into shutdown
below the minimum VIN of 2.6V. This feature can be used
to prevent excessive discharge of battery-operated systems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3µA internal current
source defaults the open pin condition to be operating (see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
10
1767 F04
SYNCHRONIZATION
The SYNC pin, is used to synchronize the internal oscillator to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to
up to 2MHz. This means that
frequency is equal to the worst-case
initial
operating frequency
minimum
practical sync
high
self-oscillating
frequency (1.5MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.6MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
sn1767 1767fas
LT1767/LT1767-1.8/
P
W
PW
PW
SW
BOOST
Q
=
( )()()
+
()
()( )
()
=+=
=
()( )
=
=
()
=
−
027 1 5
10
17 10 1 10 1 25 10
0135 0 21 0 34
5150
10
005
10 0 001 0 01
2
96
2
.
•.•
...
/
.
..
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implemented in the suggested layout of Figure 6. Shortening this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1767
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate voltages across the LT1767 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
LT1767
V
IN
SW
L1
5V
Board layout also has a significant effect on thermal
resistance. Soldering the exposed pad to as large a copper
area as possible and placing feedthroughs under the pad
to a ground plane, will reduce die temperature and increase the power capacity of the LT1767. For the
nonexposed package, Pin 4 is connected directly to the
pad inside the package. Similar treatment of this pin will
result in lower die temperatures.
THERMAL CALCULATIONS
Power dissipation in the LT1767 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following
formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating efficiency at light
load currents.
Switch loss:
RI V
P
SW
Boost current loss for V
P
BOOST
Quiescent current loss:
PV
QIN
SW OUT OUT
=
VI
=
=
0 001.
()
2
()( )
ns I V f
+
17
V
IN
= V
BOOST
2
OUT OUT
()
50/
V
IN
OUT IN
()()()
:
OUT
HIGH
V
IN
Figure 5. High Speed Switching Path
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1767
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
FREQUENCY
CIRCULATING
PATH
D1 C1C3
LOAD
1767 F05
RSW = Switch resistance (≈0.27Ω when hot)
17ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with VIN = 10V, V
= 5V and I
OUT
OUT
= 1A:
sn1767 1767fas
11
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
D2
CMDSH-3
V
IN
12V
C3
OPEN
OR
HIGH
= ON
V
D2
C2
MINIMIZE LT1767,
C3, D1 LOOP
2.2µF
CERAMIC
IN
V
IN
SYNC
BOOST
LT1767-2.5
GND
C2
0.1µF
V
SW
FBSHDN
V
C
C
C
1.5nF
R
C
4.7k
C3
D1
UPS120
L1
5µH
GND
OUTPUT
2.5V
1.2A
C1
10µF
CERAMIC
1767 F06a
PLACE FEEDTHROUGHS
AROUND GROUND PIN
AND UNDER GROUND PAD
FOR GOOD THERMAL
CONDUCTIVITY
SYNC
SHDN
KEEP FB AND V
COMPONENTS
AWAY FROM
HIGH INPUT
COMPONENTS
C
L1
C1
V
OUT
Figure 6. Typical Application and Suggested Layout (Topside Only Shown)
Total power dissipation is 0.34 + 0.05 + 0.01 = 0.4W.
Thermal resistance for LT1767 package is influenced by
the presence of internal or backside planes. With a full
plane under the package, thermal resistance for the
exposed pad package will be about 40°C/W. No plane will
increase resistance to about 150°C/W. To calculate die
temperature, use the appropriate thermal resistance
number and add in worst-case ambient temperature:
TJ = TA + θJA (P
TOT
)
C
D1
GND
KELVIN SENSE
V
OUT
CONNECT TO
GROUND PLANE
C
R
C
1767 F06
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power.
P
DIODE
VV V I
()
=
−
F IN OUT LOAD
()()
V
IN
VF = Forward voltage of diode (assume 0.5V at 1A)
05 12 5 1
PW
DIODE
()
=
−
()()
029..
=
12
12
sn1767 1767fas
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower VF diode can improve efficiency by several percent.
P
INDUCTOR
L
DCR
P
INDUCTOR
Typical thermal resistance of the board is 35°C/W. At an
ambient temperature of 65°C,
Tj = 65 + 40 (0.4) + 35 (0.39) = 95°C
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must first be calibrated,
with no device power, in an oven. The same measurement
can then be used in operation to indicate the die temperature.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered – the
worse the board layout, the more difficult the circuit will be
to stabilize. This is true of almost all high frequency analog
circuits, read the ‘LAYOUT CONSIDERATIONS’ section
first. Common layout errors that appear as stability problems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the VC compensation
to a ground track carrying significant switch current. In
addition, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with production layout and components.
The LT1767 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 7,
with both tantalum and ceramic capacitor equivalent circuits. The LT1767 can be considered as two gm blocks, the
error amplifier and the power stage.
Figure 8 shows the overall loop response with a 330pF V
capacitor and a typical 100µF tantalum output capacitor.
The response is set by the following terms:
= (I
LOAD
) (L
DCR
)
= Inductor DC resistance (assume 0.1Ω)
= (1) (0.1) = 0.1W
C
LT1767
CURRENT MODE
POWER STAGE
= 2.5mho
g
m
GND
V
C
R
C
C
500k
C
AMPLIFIER
g
850µmho
C
ERROR
=
m
F
V
SW
R1
FB
–
+
1.2V
R2
OUTPUT
CERAMICTANTALUM
ESR
ESL
+
C1
C1
1767 F07
Figure 7. Model for Loop Response
80
60
40
20
GAIN (dB)
0
–20
–40
10 1k 10k 1M100 100k
V
OUT
C
OUT
= 330pF
C
C
R
C/CF
I
LOAD
FREQUENCY (Hz)
= 5V
= 100µF, 0.1Ω
= N/C
= 500mA
PHASE
GAIN
1767 F10
180
150
120
PHASE (DEG)
90
60
30
0
Figure 8. Overall Loop Response
Error amplifier:
DC gain set by gm and RL = 850µ • 500k␣ =␣ 425.
Pole set by CF and RL = (2π • 500k • 330p)–1 = 965Hz.
Unity-gain set by CF and gm = (2π • 330p • 850µ–1)–1 =
410kHz.
Power stage:
DC gain set by gm and RL (assume 10Ω) = 2.5 • 10 = 25.
Pole set by C
Unity-gain set by C
and RL = (2π • 100µ • 10)–1 = 159Hz.
OUT
and gm = (2π • 100µ • 2.5–1)–1 =
OUT
3.98kHz.
Tantalum output capacitor:
Zero set by C
OUT
and C
= (2π • 100µ • 0.1)–1 = 15.9kHz.
ESR
sn1767 1767fas
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LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
The zero produced by the ESR of the tantalum output
capacitor is very useful in maintaining stability. Ceramic
output capacitors do not have a zero due to very low ESR,
but are dominated by their ESL. They form a notch in the
1MHz to 10MHz range. Without this zero, the VC pole must
be made dominant. A typical value of 2.2nF will achieve
this.
If better transient response is required, a zero can be
added to the loop using a resistor (RC) in series with the
compensation capacitor. As the value of RC is increased,
transient response will generally improve, but two effects
limit its value. First, the combination of output capacitor
ESR and a large RC may stop loop gain rolling off altogether. Second, if the loop gain is not rolled sufficiently at
the switching frequency, output ripple will perturb the V
pin enough to cause unstable duty cycle switching similar
to subharmonic oscillation. This may not be apparent at
the output. Small signal analysis will not show this since
a continuous time system is assumed. If needed, an
additional capacitor (CF) can be added to form a pole at
typically one fifth the switching frequency (If RC = ~ 5k,
CF = ~ 100pF).
When checking loop stability, the circuit should be operated over the application’s full voltage, current and temperature range. Any transient loads should be applied and
the output voltage monitored for a well-damped behavior.
See Application Note 76 for more details.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for example, a battery powered device with a wall adapter input,
the output of the LT1767 can be held up by the backup
supply with its input disconnected. In this condition, the
SW pin will source current into the VIN pin. If the SHDN pin
is held at ground, only the shut down current of 6µA will
be pulled via the SW pin from the second supply. With the
SHDN pin floating, the LT1767 will consume its quiescent
operating current of 1mA. The VIN pin will also source
current to any other components connected to the input
line. If this load is greater than 10mA or the input could be
shorted to ground, a series Schottky diode must be added,
as shown in Figure 9. With these safeguards, the output
can be held at voltages up to the VIN absolute maximum
rating.
C
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 10 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, CSS and Q1. As
the output starts to rise, Q1 turns on, regulating switch
current via the VC pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current
through CSS defined by R4 and Q1’s VBE. Once the output
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.
RC V
()( )( )
4
RiseTime
Using the values shown in Figure 10,
RiseTime ms==
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can be
used for sequencing multiple regulator outputs.
Dual Output SEPIC Converter
The circuit in Figure 11 generates both positive and
negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
standard B H Electronics inductor. The topology for the 5V
output is a standard buck converter. The –5V topology
would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates a SEPIC
(single-ended primary inductance converter) topology
which improves regulation and reduces ripple current in
L1. Without C4, the voltage swing on L1B compared to
L1A would vary due to relative loading and coupling
losses. C4 provides a low impedance path to maintain an
equal voltage swing in L1B, improving regulation. In a
flyback converter, during switch on time, all the converter’s
energy is stored in L1A only, since no current flows in L1B.
At switch off, energy is transferred by magnetic coupling
into L1B, powering the –5V rail. C4 pulls L1B positive
=
SS OUT
V
()
BE
47 10 15 10 5
(• )(• )()
39
07
–
.
5
sn1767 1767fas
14
LT1767/LT1767-1.8/
OUTPUT
5V
OUTPUT
–5V
†
* L1 IS A SINGLE CORE WITH TWO WINDINGS
BH ELECTRONICS #511-1013
†
IF LOAD CAN GO TO ZERO,
AN OPTIONAL PRELOAD OF 1k TO 5k
MAY BE USED TO IMPROVE LOAD REGULATION
D1, D3: UPS120
V
IN
6V TO 15V
GND
1767 F11
C2
0.1µF
C
C
330pF
D1
C1
100µF
10V TANT
C5
100µF
10V TANT
C3
2.2µF
16V
CERAMIC
C4
2.2µF
16V
CERAMIC
D2
CMDSH-3
D3
L1A*
9µH
L1B*
+
+
BOOST
LT1767-5
V
IN
V
SW
FBSHDN
GND
V
C
SYNC
LT1767-2.5/LT1767-3.3/LT1767-5
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APPLICATIONS INFORMATION
during switch on time, causing current to flow, and energy
to build in L1B and C4. At switch off, the energy stored in
both L1B and C4 supply the –5V rail. This reduces the
12V
V
IN
+
C3
2.2µF
D1: UPS120
Q1: 2N3904
V
IN
SHDN
SYNC
BOOST
LT1767-5
GND
REMOVABLE
INPUT
* ONLY REQUIRED IF INPUT CAN SINK >10mA
UPS120*
83k
28.5k
Figure 9. Dual Source Supply with 6µA Reverse Leakage
D2
CMDSH-3
C2
0.1µF
V
SW
D1
FB
V
C
C
C
330pF
L1
5µH
+
C1
100µF
C
SS
R3
15nF
2k
Q1
R4
47k
1767 F10
V
2.2µF
IN
SYNC
BOOST
LT1767-3.3
OUTPUT
5V
1A
GND
V
SW
FBSHDN
V
C
1.5nF
4.7k
current in L1A and changes L1B current waveform from
square to triangular. For details on this circuit, including
maximum output currents, see Design Note 100.
CMDSH-3
0.1µF
5µH
UPS120
3.3V, 1A
2.2µF
ALTERNATE
SUPPLY
1767 F09
Figure 10. Buck Converter with Adjustable Soft-Start
PACKAGE DESCRIPTION
0.007
(0.18)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.021
± 0.006
(0.53 ± 0.015)
Figure 11. Dual Output SEPIC Converter
U
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
° – 6° TYP
0
0.043
(1.10)
MAX
0.034
(0.86)
REF
SEATING
0.009 – 0.015
(0.22 – 0.38)
0.0256
0.005
± 0.002
(0.13 ± 0.05)
PLANE
(0.65)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
BSC
8
7
12
6
5
0.118 ± 0.004**
4
3
(3.00 ± 0.102)
MSOP (MS8) 1100
sn1767 1767fas
15
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
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PACKAGE DESCRIPTION
MS8E Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1662)
± 0.102
0.889 ± 0.127
(.035 ± .005)
3.2 – 3.45
(.126 – .136)
GAUGE PLANE
0.18
(.077)
0.254
(.010)
DETAIL “A”
DETAIL “A”
° – 6° TYP
0
2.794 ± 0.102
(.110 ± .004)
5.23
(.206)
MIN
0.42 ± 0.04
(.0165 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
2.083
(.082 ± .004)
0.65
(.0256)
BSC
0.53 ± 0.015
(.021 ± .006)
SEATING
PLANE
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
4.88
± 0.1
(.192 ± .004)
0.22 – 0.38
(.009 – .015)
1.10
(.043)
MAX
12
0.65
(.0256)
BCS
BOTTOM VIEW OF
EXPOSED PAD OPTION
0.52
8
7
(.206)
6
5
REF
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4
3
0.86
(.034)
REF
0.13 ± 0.05
(.005 ± .002)
MSOP (MS8E) 0102
1
8
2.06 ± 0.102
(.080 ± .004)
1.83 ± 0.102
(.072 ± .004)
RELATED PARTS
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Regulator V
= 2.65V to 6V
IN
Burst Mode is a trademark of Linear Technology Corporation.
to 600mA at VIN = 5V
OUT
to 600mA at VIN = 3.3V
OUT
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
sn1767 1767fas
LT/TP 0302 REV A 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
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