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LPC661
Low Power CMOS Operational Amplifier
General Description
The LPC661 CMOS operational amplifier is ideal for operation from a single supply. It features a wide range of operating supply voltage from +5V to +15V,rail-to-rail output swing
and an input common-mode range that includes ground.
Performance limitations that have plagued CMOS amplifiers
in the past are not a problem with this design. Input V
OS
,
drift, and broadband noise as well as voltage gain (into 100
kΩ and 5 kΩ) are all equal to or better than widely accepted
bipolar equivalents, while the supply current requirement is
typically 55 µA.
This chip is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
See the LPC660 datasheet for a Quad CMOS operational
amplifier or the LPC662 data sheet for a Dual CMOS operational amplifier with these same features.
Features
(Typical unless otherwise noted)
n Rail-to-rail output swing
n Low supply current 55 µA
n Specified for 100 kΩ and5kΩloads
n High voltage gain 120 dB
n Low input offset voltage 3 mV
n Low offset voltage drift 1.3 µV/˚C
n Ultra low input bias current 2 fA
n Input common-mode range includes GND
n Operating range from +5V to +15V
n Low distortion 0.01%at 1 kHz
n Slew rate 0.11 V/µs
Applications
n High-impedance buffer
n Precision current-to-voltage converter
n Long-term integrator
n High-impedance preamplifier
n Active filter
n Sample-and-Hold circuit
n Peak detector
Connection Diagram
Ordering Information
Package Temperature Range NSC
Drawing
Transport
Media
Military Industrial
−55˚C to +125˚C −40˚C to +85˚C
8-Pin LPC661AIM M08A Tape and Reel
Small Outline LPC661IM Rail
8-Pin LPC661AMN LPC661AIN N08E Rail
Molded DIP LPC661IN
8-Pin DIP/SO
DS011227-1
May 1998
LPC661 Low Power CMOS Operational Amplifier
© 1999 National Semiconductor Corporation DS011227 www.national.com
Page 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+−V−
) 16V
Differential Input Voltage
±
Supply Voltage
Output Short Circuit to V
+
(Notes 2, 9)
Output Short Circuit to V
−
(Note 2)
Storage Temperature Range −65˚C to +150˚C
Lead Temperature
(Soldering, 10 sec.) 260˚C
Junction Temperature (Note 3) 150˚C
Power Dissipation (Note 3)
ESD Rating
(C=100 pF, R=1.5 kΩ) 1000V
Current at Input Pin
±
5mA
Current at Output Pin
±
18 mA
Voltage Input/Output Pin (V
+
) +0.3V, (V−) −0.3V
Current at Power Supply Pin 35 mA
Operating Ratings (Note 1)
Supply Voltage 4.75V ≤ V
+
≤ 15.5V
Junction Temperature Range
LPC661AM −55˚C ≤ T
J
≤ +125˚C
LPC661AI −40˚C ≤ T
J
≤ +85˚C
LPC661I −40˚C ≤ T
J
≤ +85˚C
Power Dissipation (Note 7)
Thermal Resistance (θ
JA
) (Note 8)
8-Pin DIP 101˚C/W
8-Pin SO 165˚C/W
DC Electrical Characteristics
The following specifications apply for V
+
=
5V, V
−
=
0V, V
CM
=
1.5V, V
O
=
2.5V, and R
L
=
1M unless otherwise noted. Bold-
face limits apply at the temperature extremes; all other limits T
J
=
25˚C.
LPC661AM LPC661AI LPC661I Units
(Limit)
Symbol Parameter Conditions Typ Limit Limit Limit
(Note 4) (Note 4) (Note 4)
V
OS
Input Offset Voltage 1 3 3 6 mV
3.5 3.3 6.3
TCV
OS
Input Offset Voltage 1.3 µV/˚C
Average Drift
I
B
Input Bias Current 0.002 20 pA
100 4 4 max
I
OS
Input Offset Current 0.001 20 pA
100 2 2 max
R
IN
Input Resistance
>
1 Tera Ω
CMRR Common Mode 0V ≤ V
CM
≤ 12.0V 83 70 70 63 dB
Rejection Ratio V
+
=
15V 68 68 61 min
+PSRR Positive Power Supply 5V ≤ V
+
≤ 15V 83 70 70 63 dB
Rejection Ratio 68 68 61 min
−PSRR Negative Power Supply 0V ≤ V
−
≤ −10V 94 84 84 74 dB
Rejection Ratio 82 83 73 min
V
CM
Input Common Mode V
+
=
5V and 15V −0.4 −0.1 −0.1 −0.1 V
Voltage Range for CMRR ≥ 50 dB 000max
V
+
− 1.9 V+− 2.3 V+− 2.3 V+− 2.3 V
V
+
− 2.6 V+− 2.5 V+− 2.5 min
A
V
Large Signal Sourcing 1000 400 400 300 V/mV
Voltage Gain R
L
=
100 kΩ (Note 5) 250 300 200 min
Sinking 500 180 180 90 V/mV
R
L
=
100 kΩ (Note 5) 70 120 70 min
Sourcing 1000 200 200 100 V/mV
R
L
=
5kΩ(Note 5) 150 160 80 min
Sinking 250 100 100 50 V/mV
R
L
=
5kΩ(Note 5) 35 60 40 min
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Page 3
DC Electrical Characteristics (Continued)
The following specifications apply for V
+
=
5V, V
−
=
0V, V
CM
=
1.5V, V
O
=
2.5V, and R
L
=
1M unless otherwise noted. Bold-
face limits apply at the temperature extremes; all other limits T
J
=
25˚C.
LPC661AM LPC661AI LPC661I Units
(Limit)
Symbol Parameter Conditions Typ Limit Limit Limit
(Note 4) (Note 4) (Note 4)
V
O
Output Swing V
+
=
5V 4.987 4.970 4.970 4.940 V
R
L
=
100 kΩ to 2.5V 4.950 4.950 4.910 min
0.004 0.030 0.030 0.060 V
0.050 0.050 0.090 max
V
+
=
5V 4.940 4.850 4.850 4.750 V
R
L
=
5kΩto 2.5V 4.750 4.750 4.650 min
0.040 0.150 0.150 0.250 V
0.250 0.250 0.350 max
V
+
=
15V 14.970 14.920 14.920 14.880 V
R
L
=
100 kΩ to 7.5V 14.880 14.880 14.820 min
0.007 0.030 0.030 0.060 V
0.050 0.050 0.090 max
V
+
=
15V 14.840 14.680 14.680 14.580 V
R
L
=
5kΩto 7.5V 14.600 14.600 14.480 min
0.110 0.220 0.220 0.320 V
0.300 0.300 0.400 max
I
O
Output Current Sourcing, V
O
=
0V 22 16 16 13 mA
V
+
=
5V 12 14 11 min
Sinking, V
O
=
5V 21 16 16 13 mA
12 14 11 min
I
O
Output Current Sourcing, V
O
=
0V 40 19 28 23 mA
V
+
=
15V 19 25 20 min
Sinking, V
O
=
13V 39 19 28 23 mA
(Note 9) 19 24 19 min
I
S
Supply Current V
+
=
5V, V
O
=
1.5V 55 60 60 70 µA
70 70 85 max
V
+
=
15V, V
O
=
1.5V 58 75 75 90 µA
85 85 105 max
AC Electrical Characteristics
The following specifications apply for V
+
=
5V, V
−
=
0V, V
CM
=
1.5V, V
O
=
2.5V, and R
L
=
1M unless otherwise noted. Bold-
face limits apply at the temperature extremes; all other limits T
J
=
25˚C.
LPC661AM LPC661AI LPC661I Units
(Limit)
Symbol Parameter Conditions Typ Limit Limit Limit
(Note 4) (Note 4) (Note 4)
SR Slew Rate (Note 6) 0.11 0.07 0.07 0.05 V/µs
0.04 0.05 0.03 min
GBW Gain-Bandwidth Product 350 kHz
φm Phase Margin 50 Deg
G
M
Gain Margin 17 dB
e
n
Input Referred Voltage Noise F=1 kHz 42 nV/√Hz
i
n
Input Referred Current Noise F=1 kHz 0.0002 pA/√Hz
T.H.D. Total Harmonic Distortion F=1 kHz, A
V
=
−10 0.01
R
L
=
100 kΩ,V
O
=
8V
PP
%
V
+
=
15V
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Page 4
AC Electrical Characteristics (Continued)
Note 1: AbsoluteMaximumRatings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 2: Appliesto both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of
±
30 mA over long term may adversely affect reliability.
Note 3: The maximum power dissipation is a function of T
J(max)
, θJAand TA. The maximum allowable power dissipation at any ambient temperature is P
D
=
(T
J(max)–TA
)/θJA.
Note 4: Limits are guaranteed by testing or correlation.
Note 5: V+=15V, V
CM
=
7.5V and R
L
connected to 7.5V. For sourcing tests, 7.5V ≤ VO≤ 11.5V. For sinking tests, 2.5V ≤ VO≤ 7.5V.
Note 6: V+=15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Note 7: For operating at elevated temperatures the device must be derated based on the thermal resistance θ
JA
with P
D
=
(T
J–TA
)/θJA.
Note 8: All numbers apply for packages soldered directly into a PC board.
Note 9: Do not connect output to V
+
when V+is greater than 13V or reliability may be adversely affected.
Typical Performance Characteristics V
S
=
±
7.5V, T
A
=
25˚C unless otherwise specified
Supply Current
vs Supply Voltage
DS011227-26
Input Bias Current
vs Temperature
DS011227-27
Common-Mode Voltage Range
vs Temperature
DS011227-28
Output Characteristics
Current Sinking
DS011227-29
Output Characteristics
Current Sourcing
DS011227-30
Input Voltage Noise
vs Frequency
DS011227-31
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Page 5
Typical Performance Characteristics V
S
=
±
7.5V, T
A
=
25˚C unless otherwise specified (Continued)
CMRR vs Frequency
DS011227-32
CMRR vs Temperature
DS011227-33
Power Supply Rejection
Ratio vs Frequency
DS011227-34
Open-Loop Voltage Gain
vs Temperature
DS011227-35
Open-Loop
Frequency Response
DS011227-36
Gain and Phase Responses
vs Load Capacitance
DS011227-37
Gain and Phase Responses
vs Temperature
DS011227-38
Gain Error
(V
OS
vs V
OUT
)
DS011227-39
Non-Inverting Slew Rate
vs Temperature
DS011227-40
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Page 6
Typical Performance Characteristics V
S
=
±
7.5V, T
A
=
25˚C unless otherwise specified (Continued)
Inverting Slew Rate
vs Temperature
DS011227-41
Large-Signal Pulse
Non-Inverting Response
(A
V
=
+1)
DS011227-42
Non-Inverting Small
Signal Pulse Response
(A
V
=
+1)
DS011227-43
Inverting Large-Signal
Pulse Response
DS011227-44
Inverting Small-Signal
Pulse Response
DS011227-45
Stability vs Capacitive Load
DS011227-4
Note: Avoid resistive loads of less than 500Ω, as they may cause
instability.
Stability vs Capacitive Load
DS011227-5
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Page 7
Application Hints
AMPLIFIER TOPOLOGY
The topology chosen for the LPC661 is unconventional
(compared to general-purpose op amps) in that the traditional unity-gain buffer output stage is not used; instead, the
output is taken directly from the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while maintaining high op amp
gain and stability, and must withstand shorts to either rail,
these tasks now fall to the integrator.
As a result of these demands, the integrator is a compound
affair with an embedded gain stage that is doubly fed forward
(via C
f
and Cff) by a dedicated unity-gain compensation
driver. In addition, the output portion of the integrator is a
push-pull configuration for delivering heavy loads. While
sinking current the whole amplifier path consists of three
gain stages with one stage fed forward, whereas while
sourcing the path contains four gain stages with two fed
forward.
The large signal voltage gain while sourcing is comparable
to traditional bipolar op amps, for load resistance of at least
5kΩ. The gain while sinking is higher than most CMOS op
amps, due to the additional gain stage; however, when driving load resistance of 5 kΩ or less, the gain will be reduced
as indicated in the Electrical Characteristics. The op amp
can drive load resistance as low as 500Ω without instability.
COMPENSATING INPUT CAPACITANCE
Refer to the LMC660 or LMC662 datasheets to determine
whether or not a feedback capacitor will be necessary for
compensation and what the value of that capacitor would be.
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LPC661 may oscillate when
its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration
most sensitive to oscillation is a unity-gain follower. See the
Typical Performance Characteristics.
The load capacitance interacts with the op amp’s output resistance to create an additional pole. If this pole frequency is
sufficiently low, it will degrade the op amp’s phase margin so
that the amplifier is no longer stable at low gains. The addition of a small resistor (50Ω to 100Ω) in series with the op
amp’s output, and a capacitor (5 pF to 10 pF) from inverting
input to output pins, returns the phase margin to a safe value
without interfering with lower-frequency circuit operation.
Thus, larger values of capacitance can be tolerated without
oscillation. Note that in all cases, the output will ring heavily
when the load capacitance is near the threshold for
oscillation.
Capacitive load driving capability is enhanced by using a pull
up resistor to V
+
(
Figure 3
). Typically a pull up resistor conducting 50 µA or more will significantly improve capacitive
load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain
of the amplifier can also be affected by the pull up resistor
(see Electrical Characteristics).
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LPC661, typically less
than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LPC661’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs. See
Figure
4
. To have a significant effect, guard rings should be placed
on both the top and bottom of the PC board. This PC foil
must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
12
Ω, which is normally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of an input. This
would cause a 100 times degradation from the LPC660’s actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 10
11
Ω would
cause only 0.05 pA of leakage current, or perhaps a minor
DS011227-6
FIGURE 1. LPC661 Circuit Topology
DS011227-7
FIGURE 2. Rx, Cx Improve Capacitive Load Tolerance
DS011227-24
FIGURE 3. Compensating for Large
Capacitive Loads with A Pull Up Resistor
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Page 8
Application Hints (Continued)
(2:1) degradation of the amplifier’s performance. See
Fig-
ures 5, 6, 7
for typical connections of guard rings for stan-
dard op-amp configurations. If both inputs are active and at
high impedance, the guard can be tied to ground and still
provide some protection; see
Figure 8
.
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board con-
DS011227-8
FIGURE 4. Example of Guard Ring in P.C. Board Layout, Using the LPC660
DS011227-9
FIGURE 5. Inverting Amplifier
Guard Ring Connections
DS011227-10
FIGURE 6. Non-Inverting Amplifier
Guard Ring Connections
DS011227-11
FIGURE 7. Follower
Guard Ring Connections
DS011227-12
FIGURE 8. Howland Current Pump
Guard Ring Connections
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Page 9
Application Hints (Continued)
struction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring. See
Figure
9
.
BIAS CURRENT TESTING
The test method of
Figure 10
is appropriate for bench-testing
bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is
opened, then
A suitable capacitor for C2 would be a 5 pF or 10 pF silver
mica, NPO ceramic, or air-dielectric. When determining the
magnitude of I
−
, the leakage of the capacitor and socket
must be taken into account. Switch S2 should be left shorted
most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2
shorted)
where Cxis the stray capacitance at the + input.
Typical Single-Supply Applications (V+
=
5.0 VDC)
DS011227-13
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
FIGURE 9. Air Wiring
DS011227-14
FIGURE 10. Simple Input Bias Current Test Circuit
Photodiode Current-toVoltage Converter
DS011227-15
Note: A 5V bias on the photodiode can cut its capacitance by a factor of 2
or 3, leading to improved response and lower noise. However, this bias on
the photodiode will cause photodiode leakage (also known as its dark
current).
Micropower Current Source
DS011227-16
(Upper limit of output range dictated by input common-mode range; lower
limit dictated by minimum current requirement of LM385.)
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Page 10
Typical Single-Supply Applications (V+
=
5.0 VDC) (Continued)
This circuit, as shown, oscillates at 2.0 kHz with a
peak-to-peak output swing of 4.5V
Low-Leakage Sample-and-Hold
DS011227-17
Sine-Wave Oscillator
DS011227-18
Oscillator frequency is determined by R1, R2, C1, and C2:
f
OSC
=
1/2πRC
where R=R1=R2 and C=C1=C2.
1 Hz Square-Wave Oscillator
DS011227-19
Power Amplifier
DS011227-20
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Typical Single-Supply Applications (V+
=
5.0 VDC) (Continued)
10 Hz Bandpass Filter
DS011227-21
f
O
=
10 Hz
Q=2.1
Gain=18.9 dB
10 Hz High-Pass Filter (2 dB Dip)
DS011227-22
f
c
=
10 Hz
d=0.895
Gain=1
1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
DS011227-23
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Page 12
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin Small Outline Molded Package (M)
Order Number LPC661AIM or LPC661IM
NS Package Number M08A
8-Pin Molded Dual-In-Line Package (N)
Order Number LPC661AIN, LPC661IN or LPC661AMN
NS Package Number N08E
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Page 13
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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Tel: 65-2544466
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
LPC661 Low Power CMOS Operational Amplifier
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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