Datasheet LM2698 Datasheet (National Semiconductor)

LM2698
SIMPLE SWITCHER

®

1.35A Boost Regulator

LM2698 SIMPLE SWITCHER

March 2005

General Description

The LM2698 is a general purpose PWM boost converter.
The 1.9A, 18V, 0.2ohm internal switch enables the LM2698
to provide efficient power conversion to outputs ranging from

2.2V to 17V. It can operate with input voltages as low as 2.2V
and as high as 12V. Current-mode architecture provides
superior line and load regulation and simple frequency com­pensation over the device’s 2.2V to 12V input voltage range.
The LM2698 sets the standard in power density and is
capable of supplying 12V at 400mA from a 5V input. The
LM2698 can also be used in flyback or SEPIC topologies.

®

The LM2698 SIMPLE SWITCHER
switching frequency of either 600kHz or 1.25MHz. This pro­motes flexibility in component selection and filtering tech­niques. A shutdown pin is available to suspend the device
and decrease the quiescent current to 5µA. An external
compensation pin gives the user flexibility in setting fre­quency compensation, which makes possible the use of
small, low ESR ceramic capacitors at the output. Switchers
Made Simple
and guaranteed design. The LM2698 is available in a low
profile 8-lead MSOP package.

®

software is available to insure a quick, easy

features a pin selectable

Typical Application Circuit

Features

n 1.9A, 0.2Ω, internal switch (typical)
n Operating voltage as low as 2.2V
n 600kHz/1.25MHz adjustable frequency operation
n Switchers Made Simple
n 8-Lead MSOP package

®

software

Applications

n 3.3V to 5V, 5V to 12V conversion
n Distributed Power
n Set-Top Boxes
n DSL Modems
n Diagnostic Medical Instrumentation
n Boost Converters
n Flyback Converters
n SEPIC Converters

®

1.35A Boost Regulator

20012658

SIMPLE SWITCHER®is a registered trademark of National Semiconductor Corporation.

© 2005 National Semiconductor Corporation DS200126 www.national.com

Connection Diagram

LM2698

Top View

8-Lead Plastic MSOP

20012604

NS Package Number MUA08A

Ordering Information

Order Number Package Type NSC Package

Drawing

LM2698MM-ADJ MSOP-8 MUA08A 1000 Units, Tape and Reel S22B

LM2698MMX-ADJ MSOP-8 MUA08A 3500 Units, Tape and Reel S22B

Supplied As Package ID

Pin Description

Pin Name Function

1V

C

2 FB Output voltage feedback input.

3 SHDN

4 GND Analog and power ground.

5V

6V

SW

IN

7 FSLCT Switching frequency select input. V

8 NC Connect to ground.

Compensation network connection. Connected to the output of the voltage error amplifier.

Shutdown control input, active low.

Power switch input. Switch connected between SW pin and GND pin.

Analog power input.

= 1.25MHz. Ground = 600kHz.

IN

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Block Diagram

LM2698

20012603

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

LM2698

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

V

IN

SW Voltage −0.3V ≤ V

FB Voltage −0.3V ≤ V

V

Voltage 0.965<V

C

SHDN Voltage
(Note 2) −0.3V ≤ V

FSLCT
(Note 2) −0.3V ≤ V

Maximum Junction
Temperature

Power Dissipation (Note 3) Internally Limited

Lead Temperature 300˚C

−0.3V ≤ VIN≤ 12V

C

SHDN

FSLCT

SW

FB

<

≤ 18V

≤ 7V

1.565

≤ 7V

≤ 12V

150˚C

Vapor Phase (60 sec.) 215˚C

Infrared (15 sec.) 220˚C

ESD Susceptibility
(Note 4)

Human Body Model

(Note 5) 2kV

Machine Model 200V

Operating Conditions

Operating Junction
Temperature Range
(Note 6) −40˚C to +125˚C

Storage Temperature −65˚C to +150˚C

Supply Voltage 2.2V to 12V

SW Voltage 0 ≤ V

Electrical Characteristics

Specifications in standard type face are for TJ= 25˚C and those with boldface type apply over the full Operating Tempera­ture Range (T

Symbol Parameter Conditions

I

Q

V

FB

I

CL

%V

/∆VINFeedback Voltage Line

FB

I

B

V

IN

g

m

A

V

D

MAX

D

MIN

f

S

I

SHDN

I

L

R

DS(ON)

TH

SHDN

UVP On Threshold 1.95 2.05 2.2 V

= −40˚C to +125˚C)Unless otherwise specified. VIN=2.2V and IL= 0A, unless otherwise specified.

J

Min

(Note 6)

Typ

(Note 7)

Max

(Note 6)

Quiescent Current FB = 0V (Not Switching) 1.3 2.0 mA

V

=0V 5 10 µA

SHDN

Feedback Voltage 1.2285 1.26 1.2915 V

Switch Current Limit VIN= 2.7V (Note 8) 1.35 1.9 2.4 A

2.2V ≤ VIN≤ 12.0V 0.013 0.1 %/V

Regulation

FB Pin Bias Current

0.5 20 nA

(Note 9)

Input Voltage Range 2.2 12 V

Error Amp Transconductance ∆I = 5µA 40 135 290 µmho

Error Amp Voltage Gain 120 V/V

Maximum Duty Cycle FSLCT = Ground 78 85 %

Minimum Duty Cycle FSLCT = Ground 15 %

FSLCT = V

IN

30

Switching Frequency FSLCT = Ground 480 600 720 kHz

Shutdown Pin Current V

FSLCT = V

SHDN

V

SHDN

IN

=V

IN

=0V −0.5 -1

1 1.25 1.5 MHz

0.01 0.1 µA

Switch Leakage Current VSW= 18V 0.01 3 µA

Switch R

DS(ON)

VIN= 2.7V, ISW= 1A 0.2 0.4 Ω

SHDN Threshold Voltage Output High 0.6 0.9 V

Output Low 0.3 0.6 V

Off Threshold 1.85 1.95 2.1 V

SW

≤ 17.5V

Units

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Electrical Characteristics (Continued)

Specifications in standard type face are for TJ= 25˚C and those with boldface type apply over the full Operating Tempera­ture Range (T

Symbol Parameter Conditions

θ

JA

Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to
be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: Shutdown and voltage frequency select should not exceed V

Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T

and the ambient temperature, T
at any ambient temperature is calculated using: P
temperature, and the regulator will go into thermal shutdown.

Note 4: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin.

Note 5: ESD susceptibility using the human body model is 500V for V

Note 6: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% tested

or guaranteed through statistical analysis.All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
All limits are used to calculate Average Outgoing Quality Level (AOQL).

Note 7: Typical numbers are at 25˚C and represent the most likely norm.

Note 8: This is the switch current limit at 0% duty cycle. The switch current limit will change as a function of duty cycle. See Typical performance Characteristics

section for I

Note 9: Bias current flows into FB pin.

Note 10: Junction to ambient thermal resistance (no external heat sink) for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit.

See "Scenario ’A’" in the Power Dissipation section.

Note 11: Junction to ambient thermal resistance for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit and approximately

0.0191 sq. in. of copper heat sinking. See "Scenario ’B’" in the Power Dissipation section.

Note 12: Junction to ambient thermal resistance for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit and approximately

0.0465 sq. in. of copper heat sinking. See "Scenario ’C’" in the Power Dissipation section.

Note 13: Junction to ambient thermal resistance for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit and approximately

0.2523 sq. in. of copper heat sinking. See "Scenario ’D’" in the Power Dissipation section.

Note 14: Junction to ambient thermal resistance for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit and approximately

0.0098 sq. in. of copper heat sinking on the top layer and 0.0760 sq. in. of copper heat sinking on the bottom layer, with three 0.020 in. vias connecting the planes.
See "Scenario ’E’" in the Power Dissipation section.

= −40˚C to +125˚C)Unless otherwise specified. VIN=2.2V and IL= 0A, unless otherwise specified.

J

Min

(Note 6)

Thermal Resistance Junction to Ambient

Typ

(Note 7)

235 ˚C/W

(Note 10)

Junction to Ambient

225

(Note 11)

Junction to Ambient

220

(Note 12)

Junction to Ambient

200

(Note 13)

Junction to Ambient

195

(Note 14)

.

IN

. See the Electrical Characteristics table for the thermal resistance of various layouts. The maximum allowable power dissipation

A

vs. V

CL

IN

(MAX) = (T

D

J(MAX)−TA

.

C

)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die

(MAX), the junction-to-ambient thermal resistance, θJA,

J

Max

(Note 6)

Units

LM2698

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Typical Performance Characteristics

LM2698

Efficiency vs Load Current

= 8V, fS= 600kHz)

(V

OUT

20012667 20012666

Iqvs VIN(600 kHz, non-switching) Iqvs VIN(600 kHz, switching)

Efficiency vs Load Current

(V

= 8V, fS= 1.25MHz)

OUT

20012618

Iqvs. VIN(1.25MHz, non-switching) Iqvs VIN(1.25MHz, switching)

20012622

20012619

20012617

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Typical Performance Characteristics (Continued)

LM2698

I

q(SHDN)

vs V

IN

20012616 20012621

R

DS(ON)

vs V

IN

Switching Frequency vs VIN(600kHz) Switching Frequency vs VIN(1.25MHz)

ICLvs. Ambient Temperature

V

IN

= 3.3V, V

=8V ICLvs. V

OUT

20012620 20012623

IN

20012641 20012642

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Operation

LM2698

Continuous Conduction Mode

FIGURE 1. Simplified Boost Converter Diagram

(a) First Cycle of Operation (b) Second Cycle Of Operation

The LM2698 is a current-mode, PWM boost regulator. A
boost regulator steps the input voltage up to a higher output
voltage. In continuous conduction mode (when the inductor
current never reaches zero at steady state), the boost regu­lator operates in two cycles.

In the first cycle of operation, shown in Figure 1 (a), the
transistor is closed and the diode is reverse biased. Energy
is collected in the inductor and the load current is supplied by

.

C

OUT

The second cycle is shown in Figure 1 (b). During this cycle,
the transistor is open and the diode is forward biased. The
energy stored in the inductor is transferred to the load and
output capacitor.

The ratio of these two cycles determines the output voltage.
The output voltage is defined as:

where D is the duty cycle of the switch.

20012602

Inductor

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20012605

FIGURE 2. (a) Inductor Current (b) Diode Current

The inductor is one of the two energy storage elements in a
boost converter. Figure 2 shows how the inductor current
varies during a switching cycle. The current through an
inductor is quantified as:

Operation (Continued)

If V

is constant, diL/ dt must be constant, thus the current

L(t)

in the inductor changes at a constant rate. This is the case in
DC/DC converters since the voltages at the input and output
can be approximated as a constant. The current through the
inductor of the LM2698 boost converter is shown in Figure
2(a). The important quantities in determining a proper induc­tance value are I
(the inductor current ripple). If ∆iLis larger than I
inductor current will drop to zero for a portion of the cycle and
the converter will operate in discontinuous conduction mode.

is smaller than I

If ∆i

L

above zero and the converter will operate in continuous
conduction mode (CCM). All the analysis in this datasheet
assumes operation in continuous conduction mode. To op­erate in CCM:

(the average inductor current) and ∆i

L(AVG)

, the inductor current will stay

L(AVG)

>

I

L(AVG)

∆i

L

L(AVG)

, the

LM2698

Current Limit

The current limit in the LM2698 is referenced to the peak
switch current. The peak currents in the switch of a boost
converter will always be higher than the average current
supplied to the load. To determine the maximum average
output current that the LM2698 can supply, use:

I

OUT(MAX)

Where ICLis the switch current limit (see Electrical Chara­teristics table and Typical Performance Curves). Hence, as

increases, the maximum current that can be supplied to

V

IN

the load increases, as shown in Figure 3.

L

=(ICL− ∆iL)*(1−D) = (ICL− ∆iL)*VIN/V

OUT

Choose the minimum I
CCM operation. A common choice is to set ∆i

.

I

L(AVG)

to determine the minimum L for

OUT

L

to 30% of

The inductance value will also affect the stability of the
converter. Because the LM2698 utilizes current mode con­trol, the inductor value must be carefully chosen. See the
COMPENSATION section for recommended inductance val­ues.

Choosing an appropriate core size for the inductor involves
calculating the average and peak currents expected through
the inductor. In a boost converter,

and
I

L(Peak)=IL(AVG)

+ ∆iL,

where

A core size with ratings higher than these values should be
chosen. If the core is not properly rated, saturation will
dramatically reduce overall efficiency.

20012673

FIGURE 3. Maximum Output Current vs Input Voltage

Diode

The diode in a boost converter such as the LM2698 acts as
a switch to the output. During the first cycle, when the
transistor is closed, the diode is reverse biased and current
is blocked; the load current is supplied by the output capaci­tor. In the second cycle, the transistor is open and the diode
is forward biased; the load current is supplied by the induc­tor.

Observation of the boost converter circuit shows that the
average current through the diode is the average load cur­rent, and the peak current through the diode is the peak
current through the inductor. The diode should be rated to
handle more than its peak current. To improve efficiency, a
low forward drop Schottky diode is recommended.

Input Capacitor

Due to the presence of an inductor at the input of a boost
converter, the input current waveform is continuous and
triangular. The inductor ensures that the input capacitor sees
fairly low ripple currents. However, as the inductor gets
smaller, the input ripple increases. The rms current in the
input capacitor is given by:

The input capacitor should be capable of handling the rms
current. Although the input capacitor is not so critical in boost
applications, a 10 µF or higher value, good quality capacitor
prevents any impedance interactions with the input supply.

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Operation (Continued)

A 0.1µF or 1µF ceramic bypass capacitor is also recom-

LM2698

mended on the V
be connected very close to pin 6 to effectively filter high
frequency noise. When operating at 1.25 MHz switching
frequency, a minimum bypass capacitance of 0.22 µF is
recommended.

Output Capacitor

The output capacitor in a boost converter provides all the
output current when the switch is closed and the inductor is
charging. As a result, it sees very large ripple currents. The
output capacitor should be capable of handling the maxi­mum RMS current. The RMS current in the output capacitor
is:

where,

and

The ESR and ESL of the output capacitor directly control the
output ripple. Use capacitors with low ESR and ESL at the
output for high efficiency and low ripple voltage. Surface
mount tantalums, surface mount polymer electrolytic, and
polymer tantalum, Sanyo OS-CON, or multi-layer ceramic
capacitors are recommended at the output.

pin (pin 6) of the IC. This capacitor must

IN

D=(V

OUT-VIN

)/V

OUT

Compensation

This section presents a step-by-step procedure to design the
compensation network at pin 1 (V

) of the LM2698. These

c

design methods will produce a conservative and stable con­trol loop.

There is a minimum inductance requirement in any current
mode converter. This is a function of V

, duty cycle, and

OUT

switching frequency, among other things. The graphs below
plot the recommended inductance range vs. duty cycle for

= 12V. The two lines represent the upper and lower

V

OUT

bounds of the recommended inductance range. The simpli­fied compensation procedure that follows assumes that the
inductance never drops below the Q = 5 line. Figure 4 plots
the equation:

(1)

where,

= 0.15,

R

DSON

*

Se = 0.072

fS,
and Q = 0.5 and 5
Use Q = 5 to calculate the minimum inductance recom-

mended for a stable design. Choosing an inductor between
the Q = 0.5 and Q = 5 values provides a good tradeoff
between size and stability. Note that as V
5V, R
Characteristics section (R
case R

increases, as shown in the Typical Performance

DS(ON)

DS(ON)

should be used when choosing the induc-

vs.VINcurve). The worst

DS(ON)

drops less than

IN

tance. To view plots for different Vout, multiply the Y axis by
a factor of V

/12, or plot Equation (1) for the respective

OUT

output voltage.

20012654

FIGURE 4. Minimum Inductance Requirements for (a) fS= 600kHz and (b) fS= 1.25MHz

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20012653

Operation (Continued)

The goal of the compensation network is to provide the best
static and dynamic performance while insuring stability over
line and load variations. The relationship of stability and

LM2698

performance can be best analyzed by plotting the magnitude
and phase of the open loop frequency response in the form
of a bode plot. A typical bode plot of the LM2698 open loop
frequency response is shown in Figure 5.

FIGURE 5. Bode plot of the LM2698 Frequency Response using the Typical Application Circuit

Poles are marked with an ’X’, and zeros are marked with a
’O’. The bolded ’O’ labeled ’f

’ is a right-half plane zero.

RHP

Right half plane zeros act like normal zeros to the magnitude
(+20dB/decade slope influence) and like poles to the phase
(−90˚ shift). Three curves are shown. The powerstage curve
is the frequency response of the powerstage, which includes
the switch, diode, inductor, output capacitor, and load. The
compensator curve is the frequency response of the com­pensator, which is the error amp combined with the compen­sation network. T is the product of the powerstage and the
compensator and is the complete open loop frequency re­sponse. The power stage response is fixed by line and load
constraints, while the compensator is set by the external
compensation network at pin 1. The compensator can be
designed in a few simple steps as follows.

Quick Compensator Design

Calculate:

where,

where R
Choose C

Choose

OUT

C1

20012657

= 875kΩ
= 4.7nF

Where,

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Operation (Continued)

LM2698

If the output capacitor is of high ESR (0.1Ω or higher), it may
be necessary to use C
1/(2πC
used. Choose C

where R

ESR) (Hz) is lower than fS/2 (Hz), CC2should be

OUT

(R

OUT

such that:

C2

C+ROUT

= output impedance of the error amp (875 kΩ).

Improving Transient Response Time

The above compensator design provides a loop gain with
high phase margin for a large stability margin. The transient
response time of this loop is limited by the lower mid­frequency gain necessary to achieve a high phase margin. If
it is desired to increase the transient response time, C
be decreased. Decreasing C
increasingly shorter transient response times, however the
loop phase margin will become progressively lower as C
decreased. When optimizing the loop gain for transient re­sponse time, it is recommended to keep the phase margin
above 40˚.

. A rule of thumb is that if

C2

)(C

ESR) / (RCR

OUT

by 2x, 4x, and 6x will yield

C1

OUT

) (F)

Additional Comments on the Open Loop Frequency Re­sponse

The procedure used here to pick the compensation network
will provide a good starting point. In most cases, these
values will be sufficient for a stable design. It is always
recommended to check the design in a real test setup. This
is easy to do with the aid of a dynamic load. Set the high and
low load values to your system requirements and switch
between the two at about 1kHz. View the output voltage with
an oscilloscope using AC coupling, and zoom in enough to
see the waveform react to the load change. Use the follow­ing table to determine if your design is stable. Remember to
use worst case conditions (V

IN(MIN),ROUT(MIN),ROUT(MAX)

).

Response Conclusion What to

Change

Underdamped,
weak attenuation

Underdamped,

Nearing instability Make C

larger

Stable Nothing

C1

strong attenuation

Critically damped Stable Nothing

may

C1

is

C1

Overdamped Stable Nothing

Application Information

FIGURE 6. 3.3V to 10V Boost Converter

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20012668

Application Information (Continued)

1.25MHz Boost Converter

Figure 6 shows the LM2698 boosting 3.3V to 10V at 300mA.
As discussed in the COMPENSATION section, the R
of the internal FET in the LM2698 raises as the input voltage
drops below 5V (see Typical Performance Characteristics).
The minimum input voltage for this application is 2.5V, at

DS(ON)

which point the R

is approximately 200mΩ. Substitut-

DS(ON)

ing these values in for Equation (1), it is found that either a
10 µH (1.25MHz operation) or a 22 µH (600kHz operation) is
necessary for a stable design. The circuit is operated at

1.25MHz to allow for a smaller inductance. From the Com­pensator Design equations, R

is calculated to be 18.6kΩ,

C

and a 20kΩ resistor is used.

LM2698

FIGURE 7. 3.3V SEPIC Converter

3.3V SEPIC

The LM2698 can be used to implement a SEPIC technology.
The advantages of the SEPIC topology are that it can step
up or step down an input voltage, and it has low input current
ripple.

The conversion ratio for the SEPIC is :

where

D’ = 1−D

Solving for D yeilds:

To avoid subharmonic oscillations, it is recommended that
inductors L1 and L2 be the same inductance. Currents con­ducted by the inductors are:

20012631

I

1=IOUT(VOUT/VIN

1=VIN

D/(2*L1*fs)

∆i
I

2=IOUT

)

∆i1=VIND/(2*L2*fs)
The switch sees a maximum current of I

1+I2

+ ∆i1+ ∆i2.If

L1 = L2 = L, the maximum switch current is given by:

I

OUT

(1+V

OUT/VIN

)+VIND/(L*fs)

The maximum load current is limited by this relationship to
the switch current.

The polarity of C

will change between each cycle, so a

SEPIC

ceramic capacitor should be used here. A high quality, low
ESR capacitor will directly improve efficiency because all the
load current passes through C

should be chosen using the same relationship as in the

C

IN

boost converter (see the C

IN

.

SEPIC

section). CINmust be able to

provide the necessary RMS current.

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Application Information (Continued)

LM2698

FIGURE 8. Level-Shifted SEPIC Converter

Level-Shifted SEPIC

The circuit shown in Figure 8 is similar to the SEPIC shown
in Figure 7, except that it is level shifted to provide a negative
output voltage. This is achieved by connecting the ground of
the LM2698 to the output. The circuit analysis for the level­shifted SEPIC is the same as the SEPIC. The voltage at the
input of the LM2698 will need to be clamped if the absolute
value of the output voltage plus the input voltage exceeds
12V, the absolute maximum rating for the V

pin. The sim-

IN

plest way to do this is with a zener diode, as shown in Figure

8. Likewise, if the FSLCT pin is pulled high to operate at 1.25
MHz, its voltage must not exceed 12V. To prevent any high
frequency noise from entering the LM2698’s internal cir­cuitry, a high frequency bypass capacitor must be placed as
close to pin 6 as possible. A good choice for this capacitor is
a 0.1µF ceramic capacitor.

Layout Consideration

The GND pin and the NC pin is recommended to be con­nected by a short trace as shown below.

Power Dissipation

The output power of the LM2698 is limited by its maximum
power dissipation. The maximum power dissipation is deter­mined by the formula

=(T

P

D

jmax-TA

where T
(125˚C), T

is the maximum specified junction temperature

jmax

is the ambient temperature, and θJAis the ther-

A

mal resistance of the package. θ

)/θ

JA

is dependant on the

JA

layout of the board as shown below.

20012643

20012611

20012612

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Application Information (Continued)

20012613

LM2698

20012615

20012614

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Physical Dimensions inches (millimeters)

unless otherwise noted

1.35A Boost Regulator

®

8-Lead Plastic MSOP

NS Package Number MUA08A

LM2698 SIMPLE SWITCHER

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.

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