These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset
voltage (BI-FET II
current yet maintain a large gain bandwidth product and fast
slew rate. In addition, well matched high voltage JFET input
devices provide very low input bias and offset currents. The
LF353 is pin compatible with the standard LM1558 allowing
designers toimmediatelyupgradethe overall performance of
existing LM1558 and LM358 designs.
These amplifiers may be used in applications such as high
speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew
rate and wide bandwidth. The devices also exhibit low noise
and offset voltage drift.
™
technology). They require low supply
Typical Connection
DS005649-14
Simplified Schematic
1/2 Dual
Features
n Internally trimmed offset voltage: 10 mV
n Low input bias current: 50pA
n Low input noise voltage: 25
n Low input noise current: 0.01
n Wide gain bandwidth: 4 MHz
n High slew rate: 13 V/µs
n Low supply current: 3.6 mA
n High input impedance: 10
n Low total harmonic distortion A
RL=10k, V
n Low 1/f noise corner: 50 Hz
n Fast settling time to 0.01%:2µs
=
20Vp−p, BW=20 Hz-20 kHz
O
12
Ω
=
10,:
V
Connection Diagrams
Metal Can Package
DS005649-15
Top View
Order Number LF353H
See NS Package Number H08A
Dual-In-Line Package
<
0.02
%
DS005649-17
Order Number LF353M or LF353N
See NS Package Number M08A or N08E
DS005649-16
BI-FET II™is a trademark of National Semiconductor Corporation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Power Dissipation(Note 2)
Operating Temperature Range0˚C to +70˚C
(MAX)150˚C
T
j
Differential Input Voltage
Input Voltage Range (Note 3)
Output Short Circuit DurationContinuous
Storage Temperature Range−65˚C to +150˚C
Lead Temp. (Soldering, 10 sec.)260˚C
Soldering Information
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
ESD Tolerance (Note 8)1700V
M PackageTBD
θ
JA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical
Characteristics state DC and AC electrical specifications under particular test
conditions which guarantee specific performance limits. This assumes that
the device is within the Operating Ratings. Specifications are not guaranteed
for parameters where no limit is given, however, the typical value is a good indication of device performance.
DC Electrical Characteristics
(Note 5)
SymbolParameterConditionsLF353Units
MInTypMax
V
OS
Input Offset VoltageR
=
S
Over Temperature13mV
∆V
/∆TAverage TC of Input Offset VoltageR
OS
I
OS
I
B
R
IN
A
VOL
Input Offset CurrentT
Input Bias CurrentT
Input ResistanceT
Large Signal Voltage GainV
=
S
=
25˚C, (Notes 5, 6)25100pA
j
T
≤70˚C4nA
j
=
25˚C, (Notes 5, 6)50200pA
j
T
≤70˚C8nA
j
=
25˚C10
j
=
S
=
V
O
Over Temperature15V/mV
V
O
V
CM
Output Voltage SwingV
Input Common-Mode VoltageV
=
S
=
S
Range−12V
CMRRCommon-Mode Rejection RatioR
≤ 10kΩ70100dB
S
PSRRSupply Voltage Rejection Ratio(Note 7)70100dB
I
S
Supply Current3.66.5mA
=
10kΩ,T
25˚C510mV
A
10 kΩ10µV/˚C
12
=
±
15V, T
25˚C25100V/mV
A
10V, R
15V, R
15V
L
L
=
=
2kΩ
10kΩ
±
±
±
12
13.5V
11+15V
±
±
±
Ω
AC Electrical Characteristics
(Note 5)
SymbolParameterConditionsLF353Units
MinTypMax
=
Amplifier to Amplifier CouplingT
SRSlew RateV
GBWGain Bandwidth ProductV
e
n
i
n
Note 2: For operating at elevated temperatures, the device must be derated based on a thermal resistance of 115˚C/W typ junction to ambient for the N package,
and 158˚C/W typ junction to ambient for the H package.
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Equivalent Input Noise VoltageT
Equivalent Input Noise CurrentT
25˚C, f=1 Hz−20 kHz−120dB
A
(Input Referred)
=
S
=
S
=
25˚C, R
A
=
f
1000 Hz
=
25˚C, f=1000 Hz0.01
j
±
15V, T
±
15V, T
=
25˚C8.013V/µs
A
=
25˚C2.74MHz
A
=
100Ω,16
S
Page 3
AC Electrical Characteristics (Continued)
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: The power dissipation limit, however, cannot be exceeded.
Note 5: These specifications apply for V
Note 6: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, T
production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation, P
mended if input bias current is to be kept to a minimum.
Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. V
±
6V to±15V.
Note 8: Human body model, 1.5 kΩ in series with 100 pF.
=
±
15V and 0˚C≤TA≤+70˚C. VOS,IBand IOSare measured at V
S
D.Tj
=
where θjAis the thermal resistance from junction to ambient. Use of a heat sink is recom-
T
A+θjAPD
=
0.
CM
. Due to the limited
j
S
Typical Performance Characteristics
=
Input Bias Current
DS005649-18
Positive Common-Mode Input
Voltage Limit
Negative Current Limit
DS005649-21
Input Bias Current
DS005649-19
Negative Common-Mode Input
Voltage Limit
DS005649-22
Voltage Swing
Supply Current
DS005649-20
Positive Current Limit
DS005649-23
Output Voltage Swing
DS005649-24
DS005649-25
DS005649-26
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Page 4
Typical Performance Characteristics (Continued)
Gain Bandwidth
DS005649-27
Distortion vs Frequency
DS005649-30
Common-Mode Rejection Ratio
Bode Plot
DS005649-28
Undistorted Output Voltage Swing
DS005649-31
Power Supply Rejection Ratio
Slew Rate
DS005649-29
Open Loop Frequency Response
DS005649-32
Equivalent Input Noise Voltage
DS005649-33
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DS005649-34
DS005649-35
Page 5
Typical Performance Characteristics (Continued)
Open Loop Voltage Gain (V/V)
DS005649-36
Pulse Response
Small Signaling Inverting
Output Impedance
DS005649-4
DS005649-37
Large Signal Inverting
Inverter Settling Time
DS005649-38
DS005649-6
Small Signal Non-Inverting
DS005649-5
Large Signal Non-Inverting
DS005649-7
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Page 6
Pulse Response (Continued)
Current Limit (R
Application Hints
These devices are op amps with an internally trimmed input
offset voltage and JFET input devices (BI-FET II). These
JFETs have large reverse breakdown voltages from gate to
source and drain eliminating the need for clamps across the
inputs. Therefore, large differential input voltages can easily
be accommodated without a large increase in input current.
The maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced
to a high state.
The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within
3V of the negative supply, an increase in input offset voltage
may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation on
plies. Supply voltages less than these may result in lower
gain bandwidth and slew rate.
±
6V power sup-
=
100Ω)
L
DS005649-8
The amplifiers will drivea2kΩload resistance to
the full temperature range of 0˚C to +70˚C. If the amplifier is
forced to drive heavier load currents, however, an increase
in input offset voltage may occur on the negative voltage
swing and finally reach an active current limit on both positive and negative swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) toAC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3
dB frequency of the closed loop gain and consequently there
is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3
dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal
to the original feedback pole time constant.
±
10V over
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Page 7
Detailed Schematic
Typical Applications
DS005649-9
Three-Band Active Tone Control
DS005649-39
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Page 8
Typical Applications (Continued)
Note 1: All controls flat.
Note 2: Bass and treble boost, mid flat.
Note 3: Bass and treble cut, mid flat.
Note 4: Mid boost, bass and treble flat.
Note 5: Mid cut, bass and treble flat.
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group