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xuanvinhbkt
4
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S06/S07 System Block Diagram
2
1
D D
Thermal
Mobile CPU
CLK GEN
C1 Stepping
ICS954226
03
DDR2
400/533Mhz
C C
Int
MIC In
27
AC'97
Ext
MIC In
LineOut
B B
Speaker
27
27
27
CODEC
ALC655
TPA6017
11,12
AC-Link
26
MODEM
MDC Card
2727
B1 Stepping
20
Dothan
04.05
400/533MHzHOST BUS
PM
Alviso
GM
GML
06,07,08,09,10
100MHzDMI I/F
ICH6-M
G768D
18
T8
MAX6510
18
PCI Express
RGB
LVDS
S-Video
PCI BUS
LAN
RTL8100C(L)
/RTL8110SB(L)
VRAM*4
VGA
Board
NV44M
Cardbus/1394
/Cardreader OZ711MP1
(OZ601T OPTION)
Mini-PCI
802.11A/B/G
DB
21,22
28
XFMR
24
25
RJ45
LPC BUS
USB*3
USB
3 PORT
33
A A
HDD
(master)
B2 Stepping
ODD
19
(slave)
5
4
14.15.16.17
PATA
19
Serial
Port*1
31
NS
87381
FIR
31
3
30
KBC
ENE
KB3910
29
Touch
32 32
Pad
XD
BIOS
4Mb
INT_KB
29
RGB
PWR SW
OZ2211S
25
2
LVDS
S-Video
21
CARDBUS
ONE SLOT
CARDReader
7 IN 1
1394*1
CRT
CONN
XGA/SXGA+
13
LCD
14
TV-OUT
13
21
23
22
PCB LAYER
Signal 1
L1:
L2:
VCC
L3: Signal 2
L4:
Signal 3
L5: GND
L6:
Signal 4
Title
Document Number Rev
Date: Sheet
SYSTEM DC/DC
MAX1999
INPUTS
DCBATOUT
SYSTEM DC/DC
OZ824
INPUTS OUTPUTS
DCBATOUT
SC486
DCBATOUT
DCBATOUT
CHARGER
OZ860
DCBATOUT
CPU DC/DC
SC451
INPUTS
DCBATOUT
Block Diagram
S06 MAINBOARD
1
36
OUTPUTS
5V_S5
3V_S5
5V_AUX
3D3V_AUX
37
1D05V_S0
1D5V_S0
38
1D8V_S3
0D9V_S0
OUTPUTSINPUTS
MBATA+
18V 4.0A
5V_AUX
5V 100mA
OUTPUTS
VCC_CORE
0.844~1.3V
27A
TECHNOLOGY COPR.
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Alviso Strapping Signals
and Configuration
Pin Name
D D
C C
CFG[2:0]
CFG[3:4]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG[13:12]
CFG[14:15]
CFG16
CFG17
CFG18
CFG19
CFG20
SDVO
CRTL_DATA
All strap signals are sampled with respect to the leading
NOTE:
edge of the Alviso GMCH PWORK In signal.
Strap Description
FSB Frequency Select
Reversed
DMI x2 Select
DDR I / DDR II
CPU Strap
Reversed
PCI Express Graphics
Lane reverse option
for layout convenience
Reversed
Reversed
XOR/ALL Z test
straps
Reversed
FSB Dynamic ODT 0 = Dynamic ODT Disabled
Reversed
GMCH core VCC
Select
CPU VTT Select
Reversed
SDVO Present
Configuration
000 = Reserved
001 = FSB533
101 = FSB400
011-111 = Reversed
0 = DMI x2
1 = DMI x4
0 = DDR II
1 = DDR I
0= Reserved
1=Dothan
0=Reverse Lanes
1=Normal Operation
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)
1 = Dynamic ODT Enabled
(Default)
0 = 1.05V
1 = 1.5V
0 = 1.05V
1 = 1.2V
0 = No SDVO device present
(Default)
1= SDVO device present
(Default)
(Default)
(Default)
(Default)
(Default)
page 7
(Default)
ICS954226 Spread Spectrum
Select
Byte 6b7
1
1
1
1
1
1
1
1
Byte 6b6
byte 6b5 Byte 6b4 Spread Mode Spread Amount%
00 0
00
00
1
0
11
0
1
0
11
1
1
11
1
1
0
0
Down
Down
Down
Down
Center
Center
Center
Center
PCI Routing
OZ711MP1
1394
MiniPCI
LAN
IRQ
25
21
23
REQ/GNTIDSEL
E
C
C
0
1
2
ICH6-M IDE Integrated Series
Termination Resistors
DIOR#,DIOW#,DD[15:0],
DDACK#, IORDY,
DCS3#,
IDEIRQ
DA[2:0],
DREQ,
DCS1#,
approximately 33 ohm
page 3
0.8
1.25
1.75
2.5
+-0.3
+-0.5
+-0.8
+-1.25
Pin17/18
Mhz
100
100
100
100
100
100
100
100
KBC Hardware Strap
B B
PinNumber PinName Function
125
A1
High:Enable the internal pull-up resistors on XIOCS [F:0] pins
Low:Disable the internal pull-up resistors on XIOCS [F:0]
128
A4
High: Diasble DMPP(Recommended)
Low : Enable DMPP
131
A5
High:Enable EMWB(Recommended for application using shared BIOS
Low:Disable EMWB
11
GPIO05
High:Test Mode
Low:32KHz clock in normal running(Recommend)
12
GPIO06
High:Test Mode(KSOUT0~15 become DPLL internal data outputs,
ICH6-M Integrated Pull-up
and Pull-down Resistors
EE_DIN,EE_DOUT,
GNT[4]#/GPO[48],
GNT[6]#/GPO[16],
LAD[3:0]#/FB[3:0]#,
LDRQ[0], LDRQ[1]/GPI[41],
PWRBTN#,
(Default)
ACZ_BITCLK,
DPRSLPVR,
USB[7:0][P,N]
DD[7],
LAN_CLK
GNT[3:0]
GNT[5]#/GPO[17],
GPIO[25]
LAN_RXD[2:0],
TP[3]
ACZ_RST#, ACZ_SDIN[2:0],
ACZ_SYNC,ACZ_SDOUT,
EE_CS,
SATALED#
DDREQ
PME#,
DPRSTP#
SPKR,
ICH6 internal 20K pull-ups
ICH6 internal 20K pull-downs
ICH6 internal 15K pull-downs
ICH6 internal 11.5K pull-downs
ICH6 internal 100K pull-downs
ICH6-M EDS 15851 1.5V1
ICH6-M Strapping Options
REF
R7F9
R7F8
R7F7
FUNCTION
No Reboot
A16 Swap
Override
Boot BIOS
DEFAULT
NO_STUFF
NO_STUFF
NO_STUFF
OPTIONAL OVERRIDE
STUFF
STUFF
STUFF
Super I/O (PC87381) Strapping Options
PinNumber PinName Function
Base Address.
No pull down(default) - the Index-Data pair at 164Eh-164Fh
10 K external pull-down resistor - the Index-Data pair at 2Eh-2Fh1
TRI-STATE Device
No pull-down resistor (default) - normal pin operation
10 K external pull-down resistor - floating device pins
TRIS is set to 0 (by an external pull-down resistor), TEST must be 1
XOR Tree Test Mode.
No pull-down resistor (default) - normal pin operation
10 K external pull-down resistor - pins configured as XOR tree.
When TEST is set to 0 (by an external pull-down resistor),
TRIS must be 1
47
48
2
BADDR
TRIS
TEST
KSO16 becomes internal power-on reset output
Low:Normal operation(Recommended)
A A
105
GPIO20
High:Normal operation(Recommended)
Low:Enable ISP mode during which the RD#,WR#,MEMSEL#,A[20:0]
andD[7:0}will be controlled by ISP COntroller
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Title
Document Number Rev
4
3
2
Date: Sheet
Table of content
S06 MAINBOARD
Page 3
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hocnghetructuyen.vn
3D3V_S0
D D
3D3V_S0
R10R0402
+/-5%
10V, Y5V, +80%/-20%
R0402
R2
0
+/-5%
3D3V_APWR_S0
BC1
4.7uF
*
C0805
3D3V_48MPWR_S0
BC11
4.7uF
*
C0805
10V, Y5V, +80%/-20%
BC2
0.1uF
*
16V, Y5V, +80%/-20%
C0402
BC12
0.1uF
*
16V, Y5V, +80%/-20%
C0402
ITP_EN 0=PCIEX_6 1=CPU_2_ITP
SS_SEL 0=LCDCLK 1=PCIEX/free running
3.3V PCI clock output
C C
3D3V_S0
R12
10K
+/-5%
R0402
Dummy
R15
10K
+/-5%
R0402
B B
CPU_SEL04
MCH_BSEL07
CPU_SEL14
MCH_BSEL17
3D3V_S0
A A
R42
10K
+/-5%
R0402
R45
10K
+/-5%
R0402
Dummy
FS_A
R13
10K
+/-5%
R0402
R16
10K
+/-5%
R0402
Dummy
ITP_EN
SS_SEL
R21 0
R0402
R23 1K
R0402
R27 0
R0402
R32 1K
R0402
5
1D05V_S0
+/-5%
+/-5%
1D05V_S0
+/-5%
+/-5%
FS_B
FS_C
0
0
0
0
1
1
0
0
1
1 100M
0
1
1
R18
1K
+/-5%
R0402
Dummy
R0402 +/-5%
R24
2.2K
+/-5%
R0402
Dummy
R26
1K
+/-5%
R0402
Dummy
BSEL1
R33
2.2K
+/-5%
R0402
Dummy
FS_A
0
01200M
1
00333M
1
0
R627 2.2K
FS_C
FS_B
CPU
266M
133M
166M
400M
4
PM_STPPCI#15
BSEL0
(Default)
4
3D3V_S0
BC13
C0603
BC14
C0603 50V, NPO, +/-5%
FB1 FB L0603 180 Ohm
PCLK_MINI28
PCLK_PCM21,43
PCLK_KBC29
PCLK_SIO30
PCLK_LAN24
CLK_ICHPCI15
VTT_PWRGD#39
CLK48_ICH15
DREFCLK7
DREFCLK#7
SMBC_ICH11,17
B_SMBD_ICH11,17
*
50V, NPO, +/-5%
33pF
*
1 2
33pF
CLK_ICH1415
SIO_14M30
21
X1
X-14D318MHz
BC3
10uF
*
10V, Y5V, +80%/-20%
C0805
3D3V_APWR_S0
3D3V_CLKGEN_S0
3D3V_S0
R626
10K
+/-5%
R0402
Dummy
R6 33 R0402 +/-5%
R7 33 R0402 +/-5%
R8 33 R0402 +/-5%
R9 33 R0402 +/-5%
R10 33 R0402 +/-5%
R11 33 R0402 +/-5%
H/L : CPU_ITP/SRC7
VTT_PWRGD#
R14 22R0402 +/-5%
RN7
1
33
2 3
@GM
R22 47R0402 +/-5%
R25 47R0402 +/-5%
3
3D3V_CLKGEN_S0
BC4
0.1uF
*
C0402
16V, Y5V, +80%/-20%
3D3V_48MPWR_S0
SS_SEL
ITP_EN
FS_A
4P2R0402V
4
+/-5%
X2_ICS
X1_ICS
BSEL0
BSEL1
R19
475
R0402
+/-1%
BC5
0.1uF
*
C0402
16V, Y5V, +80%/-20%
37
1
7
21
28
34
42
48
11
56
3
4
5
9
55
8
10
12
14
15
46
47
49
50
53
16
39
52
*
16V, Y5V, +80%/-20%
U1
VDDA
VDDPCI
VDDPCI
VDDPCIEX
VDDPCIEX
VDDPCIEX
VDDCPU
VDDREF
VDD_48
PCICLK2/REQ_SEL
PCICLK3
PCICLK4
PCICLK5
H/L: 100/96MHz
SELPCIEX_LCDCLK#/PCICLK_F1
PCI/SRC_STP#
ITP_EN/PCICLK_F0
VTT_PWRGD#/PD
USB_48/FS_A
DOT96T
DOT96C
SCLK
SDATA
XOUT
XIN
REF1/FS_C/TEST_SEL
FS_B/TEST_MODE
IREF
REF0
ICS954226
BC6
0.1uF
C0402
CPUT2_ITP/PCIEXT6
CPUC2_ITP/PCIEXC6
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
**
**
PEREQ2#/PCIEXC5
*
PEREQ1#/PCIEXT5
*
2
BC7
0.1uF
*
C0402
16V, Y5V, +80%/-20%
CPUT0
CPUC0
CPUT1
CPUC1
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
PCIEXC4
PCIEXT4
GND
GND
GND
GND
GND
GND
GNDA
54
44
43
41
40
36
35
17
18
19
20
22
23
24
25
26
27
30
31
32
33
13
51
45
29
2
6
38
CPU_STP#
SATACLKT
SATACLKC
*
16V, Y5V, +80%/-20%
CLK_XDP_CPU
CLK_XDP_CPU#
*internal Pull-Up resistors
**internal Pull-Down resistor
BSEL0
R518 22R0402 +/-5%
AC_CLK 26
To external AC'97 CLK
CLK_PCIE_ICH
CLK_PCIE_I CH#
DREFSSCLK#
DREFSSCLK PCLK_SIO
DREFCLK
DREFCLK#
R28 49.9R0402 +/-1%
R30 49.9R0402 +/-1%
R34 49.9R0402 +/-1%
R36 49.9R0402 +/-1% @GM
R38 49.9R0402 +/-1% @GM
R40 49.9R0402 +/-1%
3
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_PEG
CLK_PCIE_PEG#
R29 49.9R0402 +/-1%
R31 49.9R0402 +/-1%
R35 49.9R0402 +/-1%
R37 49.9R0402 +/-1%
R39 49.9R0402 +/-1%
R41 49.9R0402 +/-1%
R43 49.9R0402 +/-1% @PM
R44 49.9R0402 +/-1% @PM
2
1
BC8
0.1uF
C0402
RN1
33
RN2
33
RN3
33
RN4
33
RN5
33
RN6
33
1
2 3
1
2 3
2 3
1
2 3
1
2 3
1
2 3
1
*
16V, Y5V, +80%/-20%
TP1
1
TP2
1
@GM
@PM
DREFSSCLK
DREFCLK
BC9
0.1uF
C0402
4P2R0402V
4
+/-5%
4P2R0402V
4
+/-5%
4P2R0402V
+/-5%
4
4P2R0402V
+/-5%
4
4P2R0402V
+/-5%
4
4P2R0402V
+/-5%
4
BC10
0.1uF
*
C0402
16V, Y5V, +80%/-20%
PM_STPCPU# 15,39
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
DREFSSCLK 7
DREFSSCLK# 7
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_PEG 42
CLK_PCIE_PEG# 42
CLK_PCIE_ICH# 15
CLK_PCIE_ICH 15
R17 0
R0603 +/-5%
R20 0
R0603 +/-5%
@PM
@PM
1D5V_S0
1D5V_S0
EMI capacitor
CLK_ICH14
PCLK_PCM
PCLK_MINI
PCLK_KBC
CLK_ICHPCI
CLK48_ICH
SIO_14M
Title
Document Numbe r Rev
Date: Sheet
C1 10pF C0402 50V, NPO, +/-5% Dummy
*
C2 10pF C0402 50V, NPO, +/-5% Dummy
*
C3 10pF C0402 50V, NPO, +/-5% Dummy
*
C4 10pF C0402 50V, NPO, +/-5% Dummy
*
C5 10pF C0402 50V, NPO, +/-5% Dummy
*
C6 10pF C0402 50V, NPO, +/-5% Dummy
*
C7 10pF C0402 50V, NPO, +/-5% Dummy
*
C8 10pF C0402 50V, NPO, +/-5% Dummy
*
TECHNOLOGY COPR.
Clock Generator
S06 MAINBOARD
345Friday, December 17, 2004
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U2A
B_H_A#[31..3]6
D D
B_H_ADSTB#06
B_H_REQ#[4..0]6
C C
B B
B_H_ADSTB#16
H_A20M#14
H_FERR#14
H_IGNNE#14
H_STPCLK#14
H_INTR14
H_NMI14
H_SMI#14
CPU_PROCHOT#
XDP_TDI
XDP_TMS
XDP_TDO
H_CPURST#
XDP_DBRESET#
XDP_TCK
XDP_TRST#
B_H_A#3
P4
B_H_A#4
U4
B_H_A#5
V3
B_H_A#6
R3
B_H_A#7
V2
B_H_A#8
W1
B_H_A#9
T4
B_H_A#10
W2
B_H_A#11
Y4
B_H_A#12
Y1
B_H_A#13
U1
B_H_A#14
AA3
B_H_A#15
Y3
B_H_A#16
AA2
B_H_A#17
B_H_A#18
B_H_A#19
B_H_A#20
B_H_A#21
B_H_A#22
B_H_A#23
B_H_A#24
B_H_A#25
B_H_A#26
B_H_A#27
B_H_A#28
B_H_A#29
B_H_A#30
B_H_A#31
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
U3
R2
P3
T2
P1
T1
C2
D3
A3
C6
D1
D4
B4
B_H_REQ#0
B_H_REQ#1
B_H_REQ#2
B_H_REQ#3
B_H_REQ#4
R519 56 R0402 +/-5%
R47 150 +/-5%R0402
R48 39.2R0402 +/-1%
R52 54.9R0402 +/-1%
R55 54.9R0402 +/-1%
R57 150 +/-5%R0402
R59 27.4R0402 +/-1%
R60 680 R0402 +/-5%
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
Dothan_Socket479
1D05V_S0
All place within 2" to CPU
4
N2
ADS#
L1
BNR#
J3
BPRI#
L4
DEFER#
H2
DRDY#
M2
DBSY#
N4
BR0#
A4
IERR#
B5
ADDR GROUP 0
ADDR GROUP 1
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
HCLK THERM XTP/ITP SIGNALS CONTROL
J2
B11
H1
K1
L2
M3
K3
K4
C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
TP3
1
B_H_ADS# 6
B_H_BNR# 6
H_BPRI# 6
H_DEFER# 6
B_H_DRDY# 6
B_H_DBSY# 6
B_H_BREQ#0 6
H_INIT# 14
B_H_LOCK# 6
TP17
1
TP18
1
H_CPURST# 6
H_TRDY# 6
B_H_HIT# 6
B_H_HITM# 6
THERMDP1 18
THERMDN 18
PM_THRMTRIP# 7,14
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
H_RS#0
H_RS#1
H_RS#2
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
CPU_PROCHOT#
1D05V_S0
H_IERR#
H_RS#[2..0] 6
Put these Caps near
the thermal diode.
*
PM_THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing
3
R46
56
+/-5%
R0402
Place testpoint on
H_IERR# with a GND
0.1" away
THERMDP1
BC15
470pF
50V, X7R, +/-10%
C0402
THERMDN
( No stub)
To V-CORE SWITCH
1D05V_S0
R58
1K
+/-1%
R0402
R61
2K
+/-5%
R0402
2
B_H_D#[63..0] 6
U2B
B_H_D#0
A19
+/-5%
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
G25
L23
M26
H24
F25
G24
M23
N24
M25
H26
N25
K25
K24
L24
C16
C14
J23
J25
L26
J26
E1
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
B_H_D#1
B_H_D#2
B_H_D#3
B_H_D#4
B_H_D#5
B_H_D#6
B_H_D#7
B_H_D#8
B_H_D#9
B_H_D#10
B_H_D#11
B_H_D#12
B_H_D#13
B_H_D#14
B_H_DSTBN#06
B_H_DSTBP#06
B_H_DINV#06 B_H_DINV#2 6
B_H_DSTBN#16
B_H_DSTBP#16
TP20
CPU_SEL03
CPU_SEL13
B_H_D#15
B_H_D#16
B_H_D#17
B_H_D#18
B_H_D#19
B_H_D#20
B_H_D#21
B_H_D#22
B_H_D#23
B_H_D#24
B_H_D#25
B_H_D#26
B_H_D#27
B_H_D#28
B_H_D#29
B_H_D#30
B_H_D#31
Dummy
R49 0 R0402
1
MISC
C3
RSVD2
AF7
RSVD3
AC1
RSVD4
E26
GTLREF0 TEST1
Layout Note:
0.5" max length.
AD26
RSVD5
GTLREF0
Dothan_Socket479
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
DATA GRP 2
DATA GRP 0DATA GRP 1
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
DATA GRP 3
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
TEST1
TEST2
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20
P25
P26
AB2
AB1
G1
B7
C19
E4
A6
C5
F23
COMP0
COMP1
COMP2
COMP3
TEST2
R62
1K
+/-5%
R0402
Dummy
B_H_D#32
B_H_D#33
B_H_D#34
B_H_D#35
B_H_D#36
B_H_D#37
B_H_D#38
B_H_D#39
B_H_D#40
B_H_D#41
B_H_D#42
B_H_D#43
B_H_D#44
B_H_D#45
B_H_D#46
B_H_D#47
B_H_D#48
B_H_D#49
B_H_D#50
B_H_D#51
B_H_D#52
B_H_D#53
B_H_D#54
B_H_D#55
B_H_D#56
B_H_D#57
B_H_D#58
B_H_D#59
B_H_D#60
B_H_D#61
B_H_D#62
B_H_D#63
B_H_DSTBN#2 6
B_H_DSTBP#2 6
B_H_DSTBN#3 6
B_H_DSTBP#3 6
B_H_DINV#3 6B_H_DINV#16
R50 27.4R0402 +/-1%
R51 54.9R0402 +/-1%
R53 27.4R0402 +/-1%
R54 54.9R0402 +/-1%
H_DPRSLP# 14
H_DPSLP# 14
H_DPWR# 6
H_CPUSLP# 6,14
R63
1K
+/-5%
R0402
Dummy
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
1
1D05V_S0
R56
200
+/-1%
R0402
H_PWRGD 14
A A
TECHNOLOGY COPR.
Title
CPU(1 of 2)
S06 MAINBOARD
1
of
445Thursday, Dec e mbe r 1 6, 2004
A
5
Document Numbe r Rev
4
3
2
Date: Sheet
Page 5
5
hocnghetructuyen.vn
VCC_CORE_S0
U2C
AA11
VCC0
AA13
VCC1
AA15
VCC2
AA17
VCC3
AA19
VCC4
D D
C C
B B
A A
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21
VCC_CORE_S0
VCC_CORE_S0
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
Dothan_Socket479
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1
VCCA2
VCCA3
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VCCSENSE
VSSSENSE
Layout Note:
10V, Y5V, +80%/-20%
*
*
BC33
10uF C0805
10V, X7R, +/-10%
*
*
BC51
0.1uF C0402
Dummy
Dummy
5
VID0
VID1
VID2
VID3
VID4
VID5
BC34
BC52
VCC_CORE_S0
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
1D05V_S0
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
TP_VCCSENSE
TP_VSSSENSE
VCCSENSE and VSSSENSE lines
should be of equal length.
*
*
BC35
BC36
10uF C0805
10uF C0805
*
*
BC54
BC53
0.1uF C0402
0.1uF C0402
Dummy
Dummy
*
10uF C0805
*
0.1uF C0402
Dummy
AE7
AF6
1D05V_S0
1D5V_S0
+/-5%
10V, Y5V, +80%/-20%
H_VID0 39
H_VID1 39
H_VID2 39
H_VID3 39
H_VID4 39
H_VID5 39
R64
54.9
+/-1%
R0402
Dummy
*
BC37
BC38
10uF C0805
*
BC56
BC55
0.1uF C0402
Dummy
*
R504
0
R0603
3D3V_S0
Dummy
*
10uF C0805
*
0.1uF C0402
Dummy
BC16
R65
54.9
+/-1%
R0402
Dummy
BC39
BC57
4
*
*
BC17
BC18
0.1uF C0402
0.1uF C0402
BC26
BC27
10nF
*
BC552
C0603
10uF
*
10V, Y5V, +80%/-20%
C0402
C0805
1uF
*
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
*
*
10uF C0805
*
0.1uF C0402
Dummy
BC40
BC58
10uF C0805
*
0.1uF C0402
Dummy
4
BC41
BC59
*
*
BC19
0.1uF C0402
0.1uF C0402
I max = 120 mA
U27
1
SHDN#
2
GND
3
IN
G913C
Dummy
VCC_CORE_S0
*
BC28
*
*
BC42
10uF C0805
10uF C0805
*
*
BC60
0.1uF C0402
0.1uF C0402
Dummy
*
BC21
BC20
0.1uF C0402
1D5V_VCCA_S0
SET
OUT
*
*
BC29
BC30
10uF C0805
10uF C0805
VCC_CORE_S0
*
BC43
BC44
10uF C0805
*
BC62
BC61
10uF C0805
*
*
BC22
0.1uF C0402
0.1uF C0402
1D5V_VCCA_S0
5
4
*
*
BC31
10uF C0805
*
BC624
10uF C0805
*
*
BC45
10uF C0805
10uF C0805
*
*
BC63
10uF C0805
10uF C0805
*
BC23
0.1uF C0402
BC551
22pF
*
C0402
50V, NPO, +/-5%
Dummy
10V, Y5V, +80%/-20%
BC553
1uF
C0603
Dummy
*
C0805
BC32
10uF
10uF C0805
*
*
BC626
BC625
10uF C0805
*
BC46
10uF C0805
*
BC64
10uF C0805
3
*
BC24
0.1uF C0402
R599
11K
+/-1%
R0402
Dummy
R505
49.9K
+/-1%
R0402
Dummy
*
BC627
10uF C0805
*
BC47
10uF C0805
*
BC65
10uF C0805
3
TC1
220uF
*
2.5V, +/-20%
BC25
CTB
0.1uF C0402
Place these
and dummy
12K7R3F for
1D8V_VCCA_S0
12.7K 1.56V
11K 1.52V
*
BC628
10uF C0805
10uF C0805
*
*
BC49
BC48
10uF C0805
10uF C0805
*
BC66
BC67
10uF C0805
10uF C0805
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
2
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
Title
Document Numbe r Rev
2
Date: Sheet
CPU(2 of 2)
S06 MAINBOARD
U2D
A2
VSS0
A5
VSS1
A8
VSS2
A11
VSS3
A14
VSS4
A17
VSS5
A20
VSS6
A23
VSS7
A26
VSS8
AA1
VSS9
AA4
VSS10
AA6
VSS11
AA8
VSS12
AA10
VSS13
AA12
VSS14
AA14
VSS15
AA16
VSS16
AA18
VSS17
AA20
VSS18
AA22
VSS19
AA25
VSS20
AB3
VSS21
AB5
VSS22
AB7
VSS23
AB9
VSS24
AB11
VSS25
AB13
VSS26
AB15
VSS27
AB17
VSS28
AB19
VSS29
AB21
VSS30
AB23
VSS31
AB26
VSS32
AC2
VSS33
AC5
VSS34
AC8
VSS35
AC10
VSS36
AC12
VSS37
AC14
VSS38
AC16
VSS39
AC18
VSS40
AC21
VSS41
AC24
VSS42
AD1
VSS43
AD4
VSS44
AD7
VSS45
AD9
VSS46
AD11
VSS47
AD13
VSS48
AD15
VSS49
AD17
VSS50
AD19
VSS51
AD22
VSS52
AD25
VSS53
AE3
VSS54
AE6
VSS55
AE8
VSS56
AE10
VSS57
AE12
VSS58
AE14
VSS59
AE16
VSS60
AE18
VSS61
AE20
VSS62
AE23
VSS63
AE26
VSS64
AF2
VSS65
AF5
VSS66
AF9
VSS67
AF11
VSS68
AF13
VSS69
AF15
VSS70
AF17
VSS71
AF19
VSS72
AF21
VSS73
AF24
VSS74
B3
VSS75
B6
VSS76
B9
VSS77
B12
VSS78
B16
VSS79
B19
VSS80
B22
VSS81
B25
VSS82
C1
VSS83
C4
VSS84
C7
VSS85
BC50
10uF C0805
C10
C13
C15
C18
C21
C24
D11
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
D2
VSS92
D5
VSS93
D7
VSS94
D9
VSS95
VSS96
Dothan_Socket479
1
TECHNOLOGY COPR.
545Friday, December 17, 2004
1
of
A
Page 6
5
hocnghetructuyen.vn
H_XRCOMP
R66
24.9
+/-1%
R0402
D D
1D05V_S0
Place them near to the chip
R67
54.9
+/-1%
R0402
H_XSCOMP
B_H_D#[63..0]4
Place them near to the chip
1D05V_S0
R68
221
+/-1%
R0603
C C
R70
100
+/-5%
R0402
H_XSWING
BC68
0.1uF
*
10V, X7R, +/-10%
C0402
Place them near to the chip
H_YRCOMP
R72
24.9
+/-1%
R0402
Place them near to the chip
B B
A A
1D05V_S0
1D05V_S0
R73
54.9
+/-1%
R0402
H_YSCOMP
Place them near to the chip
R75
221
+/-1%
R0603
H_YSWING
BC70
R76
100
+/-5%
R0402
0.1uF
*
10V, X7R, +/-10%
C0402
4
U3A
B_H_D#0
B_H_D#1
B_H_D#2
B_H_D#3
B_H_D#4
B_H_D#5
B_H_D#6
B_H_D#7
B_H_D#8
B_H_D#9
B_H_D#10
B_H_D#11
B_H_D#12
B_H_D#13
B_H_D#14
B_H_D#15
B_H_D#16
B_H_D#17
B_H_D#18
B_H_D#19
B_H_D#20
B_H_D#21
B_H_D#22
B_H_D#23
B_H_D#24
B_H_D#25
B_H_D#26
B_H_D#27
B_H_D#28
B_H_D#29
B_H_D#30
B_H_D#31
B_H_D#32
B_H_D#33
B_H_D#34
B_H_D#35
B_H_D#36
B_H_D#37
B_H_D#38
B_H_D#39
B_H_D#40
B_H_D#41
B_H_D#42
B_H_D#43
B_H_D#44
B_H_D#45
B_H_D#46
B_H_D#47
B_H_D#48
B_H_D#49
B_H_D#50
B_H_D#51
B_H_D#52
B_H_D#53
B_H_D#54
B_H_D#55
B_H_D#56
B_H_D#57
B_H_D#58
B_H_D#59
B_H_D#60
B_H_D#61
B_H_D#62
B_H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
ALVISO-GM
71.0GMCH.08U
HCPURST#
HOST
HCPUSLP#
3
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HTRDY#
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
B_H_A#3
B_H_A#4
B_H_A#5
B_H_A#6
B_H_A#7
B_H_A#8
B_H_A#9
B_H_A#10
B_H_A#11
B_H_A#12
B_H_A#13
B_H_A#14
B_H_A#15
B_H_A#16
B_H_A#17
B_H_A#18
B_H_A#19
B_H_A#20
B_H_A#21
B_H_A#22
B_H_A#23
B_H_A#24
B_H_A#25
B_H_A#26
B_H_A#27
B_H_A#28
B_H_A#29
B_H_A#30
B_H_A#31
H_VREF
B_H_DINV#0
B_H_DINV#1
B_H_DINV#2
B_H_DINV#3
B_H_DSTBN#0
B_H_DSTBN#1
B_H_DSTBN#2
B_H_DSTBN#3
B_H_DSTBP#0
B_H_DSTBP#1
B_H_DSTBP#2
B_H_DSTBP#3
TP_H_EDRDY#
TP_H_PCREQ#
B_H_REQ#0
B_H_REQ#1
B_H_REQ#2
B_H_REQ#3
B_H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#_0
B_H_ADS# 4
B_H_ADSTB#0 4
B_H_ADSTB#1 4
B_H_BNR# 4
H_BPRI# 4
B_H_BREQ#0 4
H_CPURST# 4
CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3
B_H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
B_H_DRDY# 4
TP25
1
B_H_HIT# 4
B_H_HITM# 4
B_H_LOCK# 4
1
TP26
H_TRDY# 4
2
B_H_A#[31..3] 4
1D05V_S0
BC69
0.1uF
*
10V, X7R, +/-10%
C0402
Place them near to the chip
B_H_DINV#0 4
B_H_DINV#1 4
B_H_DINV#2 4
B_H_DINV#3 4
B_H_DSTBN#0 4
B_H_DSTBN#1 4
B_H_DSTBN#2 4
B_H_DSTBN#3 4
B_H_DSTBP#0 4
B_H_DSTBP#1 4
B_H_DSTBP#2 4
B_H_DSTBP#3 4
B_H_REQ#[4..0] 4
H_RS#[2..0] 4
R74 0 R0402 +/-5%
DUMMY FOR DOTHAN A STEPPING
R69
100
+/-5%
R0402
R71
200
+/-1%
R0402
H_CPUSLP# 4,14
1
Place them near to the chip
5
Title
TECHNOLOGY COPR.
Document Numbe r Rev
4
3
2
Date: Sheet
GMCH(1 of 5)
S06 MAINBOARD
1
of
645Thursday, Dec e mbe r 1 6, 2004
A
Page 7
5
hocnghetructuyen.vn
U3B
DMI_TXN0
DMI_TXN015
DMI_TXN115
DMI_TXN215
DMI_TXN315
DMI_TXP015
DMI_TXP115
R96
40.2
+/-1%
R0402
Dummy
*
*
BC96 2.2uF
C0805
R98 10K
R0402 +/-5%
R101 10K
R0402 +/-5%
R104
80.6
+/-1%
R0402
M_RCOMPN
M_RCOMPP
R110
80.6
+/-1%
R0402
DMI_TXP215
DMI_TXP315
DMI_RXN015
DMI_RXN115
DMI_RXN215
DMI_RXN315
DMI_RXP015
DMI_RXP115
DMI_RXP215
DMI_RXP315
CLK_DDR011
CLK_DDR111
CLK_DDR311
CLK_DDR411
CLK_DDR0#11
CLK_DDR1#11
CLK_DDR3#11
CLK_DDR4#11
M_CKE0_R#11
M_CKE1_R#11
M_CKE2_R#11
M_CKE3_R#11
M_CS0_R#11
M_CS1_R#11
M_CS2_R#11
M_CS3_R#11
M_OCDCOMP0
M_OCDCOMP1
*
BC98 2.2uF
BC97 0.1uF
C0402
PM_EXTTS#0
PM_EXTTS#1
M_ODT011
M_ODT111
M_ODT211
M_ODT311
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
*
BC99 0.1uF
C0402
C0805
5
D D
C C
R95
40.2
+/-1%
R0402
Dummy
DDR_VREF
B B
2D5V_S0
VDIMM
A A
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
AA31
AB35
AC31
AD35
AA35
AB31
AC35
AA33
AB37
AC33
AD37
AA37
AB33
AC37
AM33
AE11
AJ34
AC10
AN33
AE10
AJ33
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AE27
AE28
AF10
Y31
Y33
AL1
AF6
AK1
AF5
AD1
AF9
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
ALVISO-GM
71.0GMCH.08U
DMI
DDR MUXING
CLK
CFG/RSVD
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PM
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP
NC
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
PWROK
RSTIN#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
4
G16
H13
G14
F16
TP_CFG4
F15
CFG5
G15
CFG6
E16
CFG7
D17
CFG8
J16
D15
TP_CFG10
E15
D14
E14
H12
TP_CFG14
C14
H15
CFG16
J15
H14
CFG18
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
PM_EXTTS#0
J21
PM_EXTTS#1
H22
F5
AD30
R94 100
AE29
R0402 +/-5%
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
4
R81 10K R0402+/-5%
MCH_BSEL1 3
MCH_BSEL0 3
1
1
TP31
1
TP32
1
PM_BMBUSY# 15
NB_CORE_S0
R77 0
1D05V_S0
TP29
TP30
PM_THRMTRIP# 4,14
VROK 15,16
PLT_RST1# 15,17,29,30,42
DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3
R0402 +/-5%
R78 0
R0402 +/-5%
R79 1K
R0402 +/-1%
R82 1K
R0402 +/-1%
CFG18
R632 2.2K R0402+/-5% @GM,@PM
CFG5
R102 2.2K R0402+/-5% Dummy
CFG6
R103 2.2K R0402+/-5%
CFG7
R105 2.2K R0402+/-5% Dummy
CFG8
R108 2.2K R0402+/-5% Dummy
CFG16
R109 2.2K R0402+/-5% Dummy
NB_CORE_S0
R116 0
R0402 +/-5%
@PM
3
GMCH_DDCCLK
@PM
B_GMCH_DDCDATA
@PM
@PM
@PM
GMCH_TV_COM12
GMCH_TV_LUMA12
GMCH_TV_CRMA12
VSYNC
HSYNC
R84
150
+/-5%
R0402
GMCH_HSYNC12
150@GM,0@PM
GMCH_VSYNC12
NB_CORE_S0
2D5V_S0
Layout Note:place this six
resistors beside GMCH in 0.5 iches
For NB_CORE=1.5V Strap
For DDR2 Strap
GMCH_BLUE
GMCH_GREEN
GMCH_RED
R113
150
+/-5%
R0402
150@GM,0@PM
R114
150
+/-5%
R0402
150@GM,0@PM
3
150@GM,0@PM
Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die
CLK_MCH_3GPLL#3
CLK_MCH_3GPLL3
R85
150
+/-5%
R0402
GMCH_LCDVDD_ON13
NO STUFF
1
1
1
@PM
@PM
LBKLT_CRTL13
GMCH_BL_ON29
GMCH_TXACLK-42
GMCH_TXACLK+42
GMCH_TXAOUT0-42
GMCH_TXAOUT1-42
GMCH_TXAOUT2-42
GMCH_TXAOUT0+42
GMCH_TXAOUT1+42
GMCH_TXAOUT2+42
150@GM,0@PM
LCTLA_CLK
LCTLB_DATA
GMCH_BL_ON
LBKLT_CRTL
LIBG
150@GM,0@PM
GMCH_DDCCLK12
B_GMCH_DDCDATA12
GMCH_BLUE12
GMCH_GREEN12
GMCH_RED12
R88 39R0402 +/-5% @GM
R89 39R0402 +/-5% @GM
R90 255 R0402 +/-1% @GM
R91 0
R0402 +/-5%
R93 0
R0402 +/-5%
TP33
TP34
TP35
R115
150
+/-5%
R0402
R118
0
R0402
+/-5%
@GM
R83 4.99K +/-1%
R86
4.99K@GM,0@PM
150
+/-5%
R0402
VSYNC
HSYNC
CRTIREF
R92 0
R0402 +/-5%
LCTLA_CLK
LCTLB_DATA
LDDC_NB_CLK
B_LDDC_NB_DATA
LIBG
L_LVBG
L_VREFH
L_VREFL
R111 2.2KR0402 +/-5% @GM
R112 2.2KR0402 +/-5% @GM
R117 100KR0402+/-5% @GM
R119 100KR0402+/-5% @GM
R120 1.5KR0603 +/-1% @GM
2
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
AB29
GCLKN
AC29
GCLKP
A15
TVDAC_A
C16
TVDAC_B
A17
TVDAC_C
J18
TV_REFSET
B15
TV_IRTNA
B16
TV_IRTNB
B17
TV_IRTNC
E24
DDCCLK
E23
DDCDATA
E21
BLUE
D21
BLUE#
C20
GREEN
B20
GREEN#
A19
RED
B19
RED#
H21
VSYNC
G21
HSYNC
J20
REFSET
@GM
E25
LBKLT_CRTL
F25
LBKLT_EN
C23
LCTLA_CLK
C22
LCTLB_DATA
F23
LDDC_CLK
F22
LDDC_DATA
F26
LVDD_EN
C33
LIBG
C31
LVBG
F28
LVREFH
F27
LVREFL
B30
LACLKN
B29
LACLKP
C25
LBCLKN
C24
LBCLKP
B34
LADATAN0
B33
LADATAN1
B32
LADATAN2
A34
LADATAP0
A33
LADATAP1
B31
LADATAP2
C29
LBDATAN0
D28
LBDATAN1
C27
LBDATAN2
C28
LBDATAP0
D27
LBDATAP1
C26
LBDATAP2
LDDC_NB_CLK
B_LDDC_NB_DATA
2
U3G
ALVISO-GM
71.0GMCH.08U
PEG_COMP
D36
EXP_COMPI
EXP_ICOMPO
MISCTVVGALVDS
PCI-EXPRESS GRAPHICS
2D5V_S0 2D5V_S0 3D3V_S0
R107
R106
2.2K
2.2K
+/-5%
+/-5%
R0402
R0402
@GM
@GM
2D5V_S0
D34
PEG_RXN0
E30
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
Q19
@GM
2N7002EPT
Title
Document Number Rev
Date: Sheet
PEG_RXN1
F34
PEG_RXN2
G30
PEG_RXN3
H34
PEG_RXN4
J30
PEG_RXN5
K34
PEG_RXN6
L30
PEG_RXN7
M34
PEG_RXN8
N30
PEG_RXN9
P34
PEG_RXN10
R30
PEG_RXN11
T34
PEG_RXN12
U30
PEG_RXN13
V34
PEG_RXN14
W30
PEG_RXN15
Y34
PEG_RXP0
D30
PEG_RXP1
E34
PEG_RXP2
F30
PEG_RXP3
G34
PEG_RXP4
H30
PEG_RXP5
J34
PEG_RXP6
K30
PEG_RXP7
L34
PEG_RXP8
M30
PEG_RXP9
N34
PEG_RXP10
P30
PEG_RXP11
R34
PEG_RXP12
T30
PEG_RXP13
U34
PEG_RXP14
V30
PEG_RXP15
W34
16V, Y5V, +80%/-20%
BC72 0.1uF C0402
E32
BC73 0.1uF C0402 @PM
F36
BC74 0.1uF C0402 @PM
G32
BC75 0.1uF C0402 @PM
H36
BC76 0.1uF C0402 @PM
J32
BC77 0.1uF C0402 @PM
K36
BC78 0.1uF C0402 @PM
L32
BC79 0.1uF C0402 @PM
M36
BC80 0.1uF C0402 @PM
N32
BC81 0.1uF C0402 @PM
P36
BC82 0.1uF C0402 @PM
R32
BC83 0.1uF C0402 @PM
T36
BC84 0.1uF C0402 @PM
U32
BC85 0.1uF C0402 @PM
V36
BC86 0.1uF C0402 @PM
W32
BC87 0.1uF C0402 @PM
Y36
BC88 0.1uF C0402 @PM
D32
BC89 0.1uF C0402 @PM
E36
BC90 0.1uF C0402 @PM
F32
BC91 0.1uF C0402 @PM
G36
BC92 0.1uF C0402 @PM
H32
BC93 0.1uF C0402 @PM
J36
BC94 0.1uF C0402 @PM
K32
BC95 0.1uF C0402 @PM
L36
BC100 0.1uF C0402 @PM
M32
BC101 0.1uF C0402 @PM
N36
BC102 0.1uF C0402 @PM
P32
BC103 0.1uF C0402 @PM
R36
BC104 0.1uF C0402 @PM
T32
BC105 0.1uF C0402 @PM
U36
BC106 0.1uF C0402 @PM
V32
BC107 0.1uF C0402 @PM
W36
R506
2.2K
+/-5%
R0402
@GM
G
Q18
DS
2N7002EPT
G
@GM
DS
GMCH(2 of 5)
S06 MAINBOARD
R80 24.9
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R507
2.2K
+/-5%
R0402
LDDC_CLK
LDDC_DATA
1D5V_PCIE_S0
R0402
+/-1%
R508
2.2K
+/-5%
R0402
1
PEG_RXN[15..0] 42
PEG_RXP[15..0] 42
PEG_TXN0
@PM
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
LDDC_CLK 13,42
LDDC_DATA 13,42
TECHNOLOGY COPR.
1
745Friday, Decemb er 17 , 2004
PEG_TXN[15..0]42
PEG_TXP[15..0]42
A
of
Page 8
5
hocnghetructuyen.vn
4
3
2
1
M_A_DQ[63:0] 11
U3C
D D
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6 M_A_DM2
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34 M_B_A2
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
ALVISO-GM
AK15
SA_BS0#
AK16
SA_BS1#
AL21
SA_BS2#
AJ37
SA_DM0
AP35
SA_DM1
AL29
SA_DM2
AP24
SA_DM3
AP9
SA_DM4
AP4
SA_DM5
AJ2
SA_DM6
AD3
SA_DM7
AK36
SA_DQS0
AP33
SA_DQS1
AN29
SA_DQS2
AP23
SA_DQS3
AM8
SA_DQS4
AM4
SA_DQS5
AJ1
SA_DQS6
AE5
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_WE#
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
DDR SYSTEM MEMORY A
SA_RCVENIN#
SA_RCVENOUT#
M_A_DM0
M_A_DM1
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
M_A_BS#0 11
M_A_BS#1 11
M_A_BS#2 11
M_A_DM[7:0] 11
M_A_DQS[7:0] 11
M_A_DQS#[7:0] 11
M_A_A[13:0] 11
M_A_CAS# 11
M_A_RAS# 11
M_A_WE# 11
TP40
1
TP42
1
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQ[63:0] 11
U3D
AE31
SBDQ0
AE32
SBDQ1
AG32
SBDQ2
AG36
SBDQ3
AE34
SBDQ4
AE33
SBDQ5
AF31
SBDQ6
AF30
SBDQ7
AH33
SBDQ8
AH32
SBDQ9
AK31
SBDQ10
AG30
SBDQ11
AG34
SBDQ12
AG33
SBDQ13
AH31
SBDQ14
AJ31
SBDQ15
AK30
SBDQ16
AJ30
SBDQ17
AH29
SBDQ18
AH28
SBDQ19
AK29
SBDQ20
AH30
SBDQ21
AH27
SBDQ22
AG28
SBDQ23
AF24
SBDQ24
AG23
SBDQ25
AJ22
SBDQ26
AK22
SBDQ27
AH24
SBDQ28
AH23
SBDQ29
AG22
SBDQ30
AJ21
SBDQ31
AG10
SBDQ32
AG9
SBDQ33
AG8
SBDQ34
AH8
SBDQ35
AH11
SBDQ36
AH10
SBDQ37
AJ9
SBDQ38
AK9
SBDQ39
AJ7
SBDQ40
AK6
SBDQ41
AJ4
SBDQ42
AH5
SBDQ43
AK8
SBDQ44
AJ8
SBDQ45
AJ5
SBDQ46
AK4
SBDQ47
AG5
SBDQ48
AG4
SBDQ49
AD8
SBDQ50
AD9
SBDQ51
AH4
SBDQ52
AG6
SBDQ53
AE8
SBDQ54
AD7
SBDQ55
AC5
SBDQ56
AB8
SBDQ57
AB6
SBDQ58
AA8
SBDQ59
AC8
SBDQ60
AC7
SBDQ61
AA4
SBDQ62
AA5
SBDQ63
ALVISO-GM
AJ15
SB_BS0#
AG17
SB_BS1#
AG21
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
DDR SYSTEM MEMORY B
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
M_B_DM0
AF32
M_B_DM1
AK34
M_B_DM2
AK27
M_B_DM3
AK24
M_B_DM4
AJ10
M_B_DM5
AK5
M_B_DM6
AE7
M_B_DM7
AB7
M_B_DQS0
AF34
M_B_DQS1
AK32
M_B_DQS2
AJ28
M_B_DQS3
AK23
M_B_DQS4
AM10
M_B_DQS5
AH6
M_B_DQS6
AF8
M_B_DQS7
AB4
M_B_DQS#0
AF35
M_B_DQS#1
AK33
M_B_DQS#2
AK28
M_B_DQS#3
AJ23
M_B_DQS#4
AL10
M_B_DQS#5
AH7
M_B_DQS#6
AF7
M_B_DQS#7
AB5
M_B_A0
AH17
M_B_A1
AK17
AH18
M_B_A3
AJ18
M_B_A4
AK18
M_B_A5
AJ19
M_B_A6
AK19
M_B_A7
AH19
M_B_A8
AJ20
M_B_A9
AH20
M_B_A10
AJ16
M_B_A11
AG18
M_B_A12
AG20
M_B_A13
AG15
AH14
AK14
TP_MB_RCVENIN#
AF15
TP_MB_RCVENOUT#
AF14
AH16
M_B_BS#0 11
M_B_BS#1 11
M_B_BS#2 11
M_B_DM[7:0] 11
M_B_DQS[7:0] 11
M_B_DQS#[7:0] 11
M_B_A[13:0] 11
M_B_CAS# 11
M_B_RAS# 11
M_B_WE# 11
Place Test PAD Near to Chip
ascould as possible
1
1
TP41
TP43
A A
TECHNOLOGY COPR.
Title
GMCH(3 of 5)
S06 MAINBOARD
1
of
845Thursday, Dec e mbe r 1 6, 2004
A
5
Document Numbe r Rev
4
3
2
Date: Sheet
Page 9
5
hocnghetructuyen.vn
4
3
2
1
1D5V_S0
D1
2 1
SSM5818
@GM
F17
E17
VCCA_TVDACA0
D18
C18
VCCA_TVDACA1
VCCA_TVDACB0
F18
E18
VCCA_TVDACB1
VCCA_TVDACC0
1D5V_TVDAC_S0
1D5V_QTVDAC_S0
1D5V_DLVDS_S0 VDIMM
2D5V_ALVDS_S0
H17
B26
B25
D19
VCCD_TVDAC
VCCD_LVDS0
VCCDQ_TVDAC
A25
A35
VCCA_LVDS
VCCD_LVDS1
VCCD_LVDS2
B22
VCCHV0
H18
VCCA_TVBG
VCCA_TVDACC1
G18
VSSA_TVBG
B21
A21
VCCHV1
VCCHV2
*
*
*
BC124
0.1uF
C0402
*
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
AM37
AH37
AP29
VCCSM0
VCCSM1
BC110
0.1uF
C0402
@GM,0Ohm@PM
BC115
0.1uF
C0402
@GM,0Ohm@PM
BC127
0.1uF
C0402
AD28
AD27
VCCSM2
VCCSM3
R128 0 R0603 +/-5%
Note: All VCCSM
pins shorted
internally
BC133
0.1uF
C0402
AC27
AP26
AN26
VCCSM4
VCCSM5
VCCSM6
@GM
2D5V_TVDAC_S0
*
BC119
0.1uF
C0402
*
AM26
AL26
AK26
AJ26
AH26
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
R123 0 R0603 +/-5%
AG26
AF26
VCCSM13
VCCSM14
BC112
0.1uF
*
10V, X7R, +/-10%
C0402
@GM,0Ohm@PM
BC116
0.1uF
*
10V, X7R, +/-10%
C0402
@GM,0Ohm@PM
BC123
0.1uF
*
10V, X7R, +/-10%
C0402
@GM,0Ohm@PM
BC126
0.1uF
*
10V, X7R, +/-10%
C0402
@GM,0Ohm@PM
1D5V_S0_L
3D3V_TVDACA_S0
3D3V_TVDACB_S0
3D3V_TVDACC_S0
3D3V_ATVBG_S0
R121 10 R0603+/-5%
@GM
D D
C C
R126 0 R0603 +/-5%
@GM
3D3V_S0
R130 0 R0603 +/-5%
@GM
R136 0 R0603 +/-5%
@GM
R138 0 R0603 +/-5%
@GM
Route ASSATVBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane
1D5V_S0
@GM
R134 0 R0603 +/-5%
BC120
10uF
*
10V, Y5V, +80%/-20%
C0805
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
POWER
AH25
AG25
AF25
AE25
VCCSM22
VCCSM23
VCCSM24
VCCSM25
1D5V_S0
R122 0 R0603 +/-5%
2D5V_S0 2D5V_ALVDS_S0
R129 0 R0603 +/-5%
2D5V_S0
2D5V_S0 2D5V_TXLVDS_S0
R135 0 R0603 +/-5%
1.8v_s3
*
*
BC132
BC131
AE24
AE23
AE22
AE21
VCCSM26
VCCSM27
VCCSM28
10uF C0805
10uF C0805
AE20
VCCSM29
VCCSM30
10V, Y5V, +80%/-20%
AE19
VCCSM31
10V, Y5V, +80%/-20%
AE18
AE17
AE16
AE15
AE14
AP13
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
BC108
0.1uF
C0402
BC113
0.1uF
C0402
BC121
0.1uF
C0402
BC554
10uF
*
10V, Y5V, +80%/-20%
C0805
AN13
AM13
AL13
AK13
AJ13
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
*
*
*
AH13
AG13
VCCSM43
VCCSM44
1D5V_DLVDS_S0
*
*
*
AF13
AE13
AP12
AN12
VCCSM45
VCCSM46
VCCSM47
VCCSM48
BC549
10uF
10V, Y5V, +80%/-20%
C0805
BC114
10uF
10V, Y5V, +80%/-20%
C0805
BC122
4.7uF
10V, Y5V, +80%/-20%
C0805
Note: All VCCSM
pins shorted
internally
BC134
0.1uF
C0402
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
Note:VCCASM: 0.76A
1D5V_S01D5V_DDRDLL_S0
*
1D5V_PCIE_S0
*
BC111
0.1uF
C0402
BC117
10uF
C0805
*
*
BC118
10uF
C0805
TC2
220uF
2.5V, +/-20%
CTB
*
R125 0
TC3
10uF
10V, Y5V, +80%/-20%
C0805
+/-5%
R0805
R133 0 R0805 +/-5%
1D5V_S0
Note:3GIO: 1A
*
BC125
0.1uF
C0402
*
BC128
0.1uF
C0402
*
AD11
2D5V_TXLVDS_S0
V1.8_DDR_CAP3
V1.8_DDR_CAP4
V1.8_DDR_CAP6
B28
A28
AC11
AB11
AB10
AB9
VCCSM57
VCCSM58
VCCSM59
VCCSM60
A27
AP8
AM1
AE1
VCCSM61
VCCSM62
VCCSM63
VCCSM64
VCCTX_LVDS0
VCCTX_LVDS1
AF20
VCCA_SM0
VCCTX_LVDS2
AE37
W37
U37
AP19
AF19
AF18
VCC3G0
VCC3G1
VCCA_SM1
VCCA_SM2
VCCA_SM3
R37
N37
VCC3G2
VCC3G3
*
L37
J37
VCC3G4
VCC3G5
1D5V_3GPLL_S0
BC129
0.1uF
C0402
Y29
Y28
VCC3G6
VCCA_3GPLL0
BC130
10uF
*
10V, Y5V, +80%/-20%
C0805
2D5V_3GBG_S0 2D5V_S0
R141 0 R0603 +/-5%
BC135
*
0.1uF
C0402
F37
Y27
G37
VSSA_3GBG
VCCA_3GBG
VCCA_3GPLL2
VCCA_3GPLL1
1D5V_S0
R140 0 R0805 +/-5%
U3E
ALVISO-GM
71.0GMCH.08U
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCC_SYNC
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
J29
T29
B B
NB_CORE_S0
*
*
*
BC137
BC136
A A
5
10uF C0805
10V, Y5V, +80%/-20%
10uF C0805
10V, Y5V, +80%/-20%
*
BC138
BC139
10uF C0805
10V, Y5V, +80%/-20%
R29
*
BC140
0.1uF C0402
T28
K29
V28
N29
U28
M29
*
BC141
0.1uF C0402
1D5V_S0
J28
L28
P28
R28
N28
M28
*
BC142
0.1uF C0402
Dummy
T27
K28
V27
H28
U27
G28
0.1uF C0402
10V, X7R, +/-10%
4
P27
R27
L2
*
L0805 1uH
L3
*
L0805 1uH
L4
*
L0805 1uH
L5
*
L0805 1uH
J27
K27
K26
H27
*
*
*
*
J25
K25
K24
K23
K22
K21
H26
BC555
10uF
10V, Y5V, +80%/-20%
C0805
BC556
10uF
10V, Y5V, +80%/-20%
C0805
BC557
10uF
10V, Y5V, +80%/-20%
C0805
BC558
10uF
10V, Y5V, +80%/-20%
C0805
W20
U20
*
BC148
*
BC150
*
BC154
*
BC155
T20
K20
V19
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
T18
K19
V18
K18
U19
W18
1D5V_DPLLA_S0
10V, X7R, +/-10%
1D5V_DPLLB_S0
10V, X7R, +/-10%
1D5V_HPLL_S0
10V, X7R, +/-10%
1D5V_MPLL_S0
10V, X7R, +/-10%
K17
AC2
3
F19
B23
E19
C35
AA1
AA2
AC1
@GM,0Ohm@PM
L27
N27
M27
J13
K13
K12
V11
H20
G19
VCC_SYNC
C0402
*
BC149
Layout Notes: VSSA_CRTDAC
Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.
U11
W11
2D5V_CRTDAC_S0
R145 0
R0402
@GM
0.1uF
L11
T11
*
BC147
+/-5%
R11
C0402
@GM
P11
0.1uF
N11
T10
K11
V10
U10
M11
Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
R10
W10
R143 0 R0603 +/-5%
@PM
R144 0 R0603 +/-5%
@GM
J10
P10
K10
N10
M10
2
R146
10
R0402
+/-5%
NB_CORE_S0
2D5V_S0
16V, Y5V, +80%/-20%
VCCP_GMCH_CAP1
16V, Y5V, +80%/-20%
BC144
BC143
0.47uF
C0603
NB_CORE_S0_L
*
*
0.47uF
C0603
1D05V_S0
BC151
*
4.7uF
C0805
2 1
SSM5818
Title
Document Number Rev
Date: Sheet
G1
VCCP_GMCH_CAP4
VCCP_GMCH_CAP3
VCCP_GMCH_CAP2
BC1460.22uF
BC145
*
*
0.22uF
BC152
2.2uF
C0805
NB_CORE_S0
D2
16V, Y5V, +80%/-20%
BC153
0.1uF
*
*
10V, X7R, +/-10%
C0402
GMCH(4 of 5)
S06 MAINBOARD
1
TECHNOLOGY COPR.
of
945Thursday, December 16, 2004
A
Page 10
5
hocnghetructuyen.vn
D D
W29
V29
U29
P29
L29
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W27
G27
E27
B27
J26
G26
E26
A26
AN24
AL24
U3F
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
4
AJ29
AG29
AD29
AA29
VSS100
VSS101
VSS102
VSS103
AE30
AC30
AB30
AA30
Y30
C30
AM29
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
J31
H31
G31
F31
E31
D31
AP30
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
T31
R31
P31
N31
M31
L31
K31
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
A32
AL31
AG31
AD31
W31
V31
U31
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
3
AD34
AC34
AB34
AA34
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
2
AN36
AL36
AJ36
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
E37
VSS8
1
AG37
Y37
V37
T37
P37
M37
K37
H37
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
J24
F24
B24
D24
AJ24
AF23
AG24
ALVISO-GM
71.0GMCH.08U
VSS259P2VSS258T2VSS257V2VSS256
VSS255
VSS254
VSS253
VSS252
VSS251A3VSS250C3VSS249
VSS248
VSS247
VSS246
AA3
AB3
AC3
VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239
AJ3
VSSALVDS
B36
VSS260L2VSS268J2VSS269G2VSS270D2VSS271
Y1
AL2
AE2
AD2
AH2
AN2
VSS238
VSS237E5VSS236W5VSS235
VSS234
VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228
VSS227
VSS226
VSS225
VSS224G7VSS223V7VSS222
VSS221
VSS220
VSS219
VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213
VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
J12
AL5
AF4
AP5
AN4
AJ6
AA6
AE6
AA7
AC6
AK7
AG7
AL8
AN7
L10
F11
Y11
Y10
D10
AA9
AE9
AC9
AH9
H11
AN9
AA10
AJ11
AL11
AF11
AA11
AN11
AG11
J14
F14
B12
A14
B14
K14
K15
A16
D12
AJ14
AL14
AG14
K16
C15
D16
H16
C17
G17
AJ17
AL16
AN14
AF17
AN17
J19
A18
T19
B18
U18
C19
H19
AL18
F20
A20
E20
V20
D20
C21
W19
G20
AN19
AG19
AK20
J22
F21
A22
E22
D22
H23
AF21
AL22
AN21
AH22
1.8v_s3
VDIMM
C C
Dummy
AB13
AD12
AC12
AB12
U3H
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
B B
ALVISO-GM
71.0GMCH.08U
AC13
VCCSM_NCTF28
BC156
*
AD13
VCCSM_NCTF27
BC157
*
10uF
10V, Y5V, +80%/-20%
Dummy
AC17
AD16
AC16
AD15
AC15
AD14
AC14
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
1D05V_S0
Place these Hi-Freq decoupling caps near GMCH
BC161
VCCSM_NCTF10
VTT_NCTF16
BC159
*
AD22
AC22
VCCSM_NCTF9
VTT_NCTF15
P12
N12
VCCSM_NCTF8
VTT_NCTF14
BC160
*
*
10uF
10V, Y5V, +80%/-20%
Dummy
AC26
AD25
AC25
AD24
AC24
AD23
AC23
VCCSM_NCTF2
VCCSM_NCTF3
VCCSM_NCTF4
VCCSM_NCTF5
VCCSM_NCTF6
VCCSM_NCTF7
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
L13
T12
V12
R12
U12
M13
W12
10uF
10uF
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
Dummy
V17
U17
T17
P17
N17
M17
L17
AD26
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
VCCSM_NCTF0
VCCSM_NCTF1
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
T13
P13
V13
N13
R13
U13
W13
10uF
AD17
BC158
*
10uF
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
Dummy
Dummy
AD21
AC21
AD20
AC20
AD19
AC19
AD18
AC18
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
VTT_NCTF17
L12
M12
*
Dummy
L18
W17
VCC_NCTF70
VCC_NCTF71
BC162
0.1uF C0402
N18
M18
VCC_NTTF69
Y12
BC164
BC163
*
*
0.1uF C0402
Dummy
Dummy
L20
Y19
R19
P19
N19
M19
L19
Y18
R18
P18
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
BC165
*
0.1uF C0402
0.1uF C0402
Dummy
P21
N21
M21
L21
Y20
R20
P20
N20
M20
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
W21
V21
U21
T21
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
U22
T22
R22
P22
N22
M22
L22
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
R23
P23
N23
M23
L23
W22
V22
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
N24
M24
L24
W23
V23
U23
T23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
L25
W24
V24
U24
T24
R24
P24
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
V25
U25
T25
R25
P25
N25
M25
W25
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
NB_CORE_S0
W26
V26
U26
T26
R26
P26
N26
M26
L26
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
NCTF
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
L14
Y13
AA12
T14
P14
N14
R14
M14
AA13
L15
V14
Y14
U14
W14
AA14
T15
P15
N15
R15
M15
AB14
L16
V15
Y15
U15
W15
AA15
T16
P16
V16
Y16
N16
R16
U16
M16
AB15
Y17
R17
W16
AA16
AB16
AA17
AB17
AA18
NB_CORE_S0 1D05V_S0
AB18
AA19
AB19
AA20
R148 0
R1206 +/-5%
R630 0
R1206 +/-5%
R631 0
R1206 +/-5%
Y21
R21
AB20
AA21
@GML
@GM,@PM
@GM,@PM
Y22
Y23
Y24
Y25
AB21
AA22
AB22
AA23
AB23
1D5V_S0
Y26
AA24
AB24
AA25
AB25
AA26
AB26
GML: NB_CORE=1.05V
GM/PM: NB_CORE=1.5V
A A
TECHNOLOGY COPR.
5
Title
Document Number Rev
4
3
2
Date: Sheet
GMCH(5 of 5)
S06 MAINBOARD
1
A
of
10 45Thursday, December 16, 2004
Page 11
5
hocnghetructuyen.vn
CN1
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
10V, Y5V, +80%/-20%
BC583
2.2uF
C0603
M_A_DQS[7:0] 8
M_A_DQS#[7:0] 8
M_A_DM[7:0] 8
*
VDIMM
BC582
C0402
M_A_A[13:0]8
D D
M_A_BS#28
M_A_BS#08
M_A_BS#18
M_A_DQ[63:0]8
C C
B B
M_CS0_R#7
M_CS1_R#7
M_CKE0_R#7
M_CKE1_R#7
DDR_VREF
B_SMBD_ICH3,17
10V, X7R, +/-10%
BC588
*
*
0.1uF
C0402
M_A_RAS#8
M_A_CAS#8
M_A_WE#8
SMBC_ICH3,17
BC589
2.2uF
C0603
M_A_A0
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
107
106
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
50
69
83
120
163
110
115
79
80
108
113
109
197
195
114
119
1
201
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
VDD_SPD
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LOW 4.0mm DDRII SDRAM SO-DIMM (200P)
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
CS0#
CS1#
CKE0
CKE1
RAS#
CAS#
WE#
SCL
SDA
ODT0
ODT1
VREF
GND
DDR_SO-DIMM
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_ODT07
M_ODT17
10V, Y5V, +80%/-20%
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
CK0#
CK1#
GND
M_A_DQS0
13
M_A_DQS1
31
M_A_DQS2
51
M_A_DQS3
70
M_A_DQS4
131
M_A_DQS5
148
M_A_DQS6
169
M_A_DQS7
188
M_A_DQS#0
11
M_A_DQS#1
29
M_A_DQS#2
49
M_A_DQS#3
68
M_A_DQS#4
129
M_A_DQS#5
146
M_A_DQS#6
167
M_A_DQS#7
186
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
30
CK0
32
164
CK1
166
SA0_DIM1
198
SA0
SA1_DIM1
200
SA1
199
81
VDD
82
VDD
87
VDD
88
VDD
95
VDD
96
VDD
103
VDD
104
VDD
111
VDD
112
VDD
117
VDD
118
VDD
2
VSS
3
VSS
8
VSS
9
VSS
12
VSS
15
VSS
18
VSS
21
VSS
24
VSS
27
VSS
28
VSS
33
VSS
34
VSS
39
VSS
40
VSS
41
VSS
42
VSS
47
VSS
48
VSS
53
VSS
54
VSS
59
VSS
60
VSS
65
VSS
66
VSS
71
VSS
72
VSS
77
VSS
78
VSS
121
VSS
122
VSS
127
VSS
128
VSS
132
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
149
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
165
VSS
168
VSS
171
VSS
172
VSS
177
VSS
178
VSS
183
VSS
184
VSS
187
VSS
190
VSS
193
VSS
196
VSS
202
CLK_DDR0 7
CLK_DDR0# 7
CLK_DDR1 7
CLK_DDR1# 7
0.1uF
*
10V, X7R, +/-10%
+/-1%
+/-1%
R0402
4
3D3V_S0
R0402
3
M_B_A[13:0]8
M_B_BS#28
M_B_BS#08
M_B_BS#18
M_CS2_R#7
M_CS3_R#7
CLK_DDR37
CLK_DDR3#7
CLK_DDR47
CLK_DDR4#7
M_CKE2_R#7
M_CKE3_R#7
M_B_CAS#8
R0402
R520 10K
3D3V_S0
R52110K
R52310K
R522 10K
R0402
M_B_RAS#8
M_B_WE#8
+/-1%
+/-1%
SMBC_ICH3,17
B_SMBD_ICH3,17
M_B_DM[7:0]8
M_B_DQS[7:0]8
M_B_DQS#[7:0]8
*
DDR_VREF
10V, X7R, +/-10%
BC586
0.1uF
*
C0402
10V, X7R, +/-10%
M_ODT27
M_ODT37
3D3V_S0
BC580
0.1uF
C0402
*
10V, Y5V, +80%/-20%
VDIMM
BC587
2.2uF
C0603
*
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
SA0_DIM2
SA1_DIM2
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
BC581
2.2uF
C0603
CN2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16_BA2
107
BA0
106
BA1
110
S0#
115
S1#
30
CK0
32
CK0#
164
CK1
166
CK1#
79
CKE0
80
CKE1
113
CAS#
108
RAS#
109
WE#
198
SA0
200
SA1
197
SCL
195
SDA
114
ODT0
119
ODT1
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
11
DQS#0
29
DQS#1
49
DQS#2
68
DQS#3
129
DQS#4
146
DQS#5
167
DQS#6
186
DQS#7
112
VDD1
111
VDD2
117
VDD3
96
VDD4
95
VDD5
118
VDD6
81
VDD7
82
VDD8
87
VDD9
103
VDD10
88
VDD11
104
VDD12
199
83
120
50
69
163
1
201
202
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
24
18
162
HIGH 9.0mm DDRII SDRAM SO-DIMM (200P)
VDDSPD
NC1
NC2
NC3
NC4
NCTEST
VREF
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS17
VSS16
VSS57
DDR_SO-DIMM
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
M_B_DQ0
5
DQ0
M_B_DQ1
7
DQ1
M_B_DQ2
17
DQ2
M_B_DQ3
19
DQ3
M_B_DQ4
4
DQ4
M_B_DQ5
6
DQ5
M_B_DQ6
14
DQ6
M_B_DQ7
16
DQ7
M_B_DQ8
23
DQ8
M_B_DQ9
25
DQ9
M_B_DQ10
35
M_B_DQ11
37
M_B_DQ12
20
M_B_DQ13
22
M_B_DQ14
36
M_B_DQ15
38
M_B_DQ16
43
M_B_DQ17
45
M_B_DQ18
55
M_B_DQ19
57
M_B_DQ20
44
M_B_DQ21
46
M_B_DQ22
56
M_B_DQ23
58
M_B_DQ24
61
M_B_DQ25
63
M_B_DQ26
73
M_B_DQ27
75
M_B_DQ28
62
M_B_DQ29
64
M_B_DQ30
74
M_B_DQ31
76
M_B_DQ32
123
M_B_DQ33
125
M_B_DQ34
135
M_B_DQ35
137
M_B_DQ36
124
M_B_DQ37
126
M_B_DQ38
134
M_B_DQ39
136
M_B_DQ40
141
M_B_DQ41
143
M_B_DQ42
151
M_B_DQ43
153
M_B_DQ44
140
M_B_DQ45
142
M_B_DQ46
152
M_B_DQ47
154
M_B_DQ48
157
M_B_DQ49
159
M_B_DQ50
173
M_B_DQ51
175
M_B_DQ52
158
M_B_DQ53
160
M_B_DQ54
174
M_B_DQ55
176
M_B_DQ56
179
M_B_DQ57
181
M_B_DQ58
189
M_B_DQ59
191
M_B_DQ60
180
M_B_DQ61
182
M_B_DQ62
192
M_B_DQ63
194
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
M_B_DQ[63:0] 8
2
10V, X7R, +/-10%
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
10V, X7R, +/-10%
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
*
C0402
1
VTT_MEM
RN67
BC5590.1uF
BC5600.1uF
BC5610.1uF
BC5620.1uF
BC5630.1uF
BC5640.1uF
BC5650.1uF
BC5660.1uF
BC5670.1uF
BC5680.1uF
BC5690.1uF
BC5700.1uF
BC5710.1uF
BC5720.1uF
BC5730.1uF
BC5740.1uF
BC5750.1uF
BC5760.1uF
BC5770.1uF
BC5780.1uF
BC5790.1uF
BC5840.1uF
BC5850.1uF
BC5900.1uF
BC5910.1uF
BC5920.1uF
1
*
3
5
7 8
RN68
1
*
3
5
7 8
RN69
1
*
3
5
7 8
RN70
1
*
3
5
7 8
RN71
1
*
3
5
7 8
RN72
1
*
3
5
7 8
RN73
1
*
3
5
7 8
RN74
1
*
3
5
7 8
RN75
1
*
3
5
7 8
R524 56
R0402 +/-5%
R525 56
R0402 +/-5%
RN76
1
*
3
5
7 8
RN77
1
*
3
5
7 8
RN78
1
*
3
5
7 8
R526 56
R0402 +/-5%
R527 56
R0402 +/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
56 8P4R0402+/-5%
56 8P4R 0402+/-5%
56 8P4R 0402+/-5%
M_B_A9
2
M_B_A12
4
M_B_BS#2
6
M_CKE2_R#
M_B_A1
2
M_B_A3
4
M_B_A5
6
M_B_A8
M_B_CAS#
2
M_B_WE#
4
M_B_BS#0
6
M_B_A10
M_CKE3_R#
2
M_B_A11
4
M_B_A7
6
M_B_A6
M_ODT1
2
M_A_CAS#
4
M_A_BS#0
6
M_A_WE#
M_A_RAS#
2
M_CS0_R#
4
M_ODT0
6
M_A_A13
M_B_A4
2
M_B_A2
4
M_B_A0
6
M_B_BS#1
M_B_RAS#
2
M_CS2_R#
4
M_ODT2
6
M_B_A13
M_CKE1_R#
2
M_A_A11
4
M_A_A7
6
M_A_A6
M_CS3_R#
M_ODT3
M_A_A8
2
M_A_A12
4
M_A_A9
6
M_A_BS#2
M_A_A4
2
M_A_A2
4
M_A_A0
6
M_A_BS#1
M_A_A10
2
M_A_A3
4
M_A_A1
6
M_A_A5
M_CKE0_R#
M_CS1_R#
A A
VDIMM
*
10V, Y5V, +80%/-20%
5
BC605
2.2uF
C0603
VDIMM
BC607
BC606
2.2uF
0.1uF
*
*
C0603
C0402
BC609
BC608
2.2uF
0.1uF
*
*
C0603
C0402
BC611
BC610
0.1uF
*
C0402
BC612
2.2uF
0.1uF
*
*
C0603
C0402
4
BC614
BC615
BC613
0.1uF
2.2uF
*
*
C0402
C0603
BC616
0.1uF
C0402
10V, X7R, +/-10%
*
TC15
220uF
2.5V, +/-20%
CTX
2.2uF
*
*
C0603
BC594
BC593
2.2uF
0.1uF
*
*
C0603
C0402
10V, Y5V, +80%/-20%
3
BC596
BC595
0.1uF
2.2uF
*
*
C0402
C0603
BC598
BC599
BC597
0.1uF
2.2uF
*
*
C0402
C0603
BC600
2.2uF
0.1uF
*
*
C0603
C0402
BC602
BC601
0.1uF
2.2uF
*
*
C0402
C0603
2
VDIMM
BC604
BC603
0.1uF
2.2uF
*
*
C0402
C0603
10V, X7R, +/-10%
Title
DDR2_SOCKET
Document Number Rev
Date: Sheet
S06 MAINBOARD
1
TECHNOLOGY COPR.
of
11 45Friday, De ce mb e r 17, 2004
A
Page 12
5
hocnghetructuyen.vn
CRT I/F & CONNECTOR
D D
GMCH_RED7
EX_RED42
GMCH_GREEN7
EX_GREEN42
GMCH_BLUE7
EX_BLUE42
R170 0
R0402 +/-5%
R171 0
R0402 +/-5%
R174 0
R0402 +/-5%
R175 0
R0402 +/-5%
R176 0
R0402 +/-5%
R177 0
R0402 +/-5%
Layout Note:
C C
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
Hsync & Vsync level shift
GMCH_HSYNC7
EX_HSYNC42
GMCH_VSYNC7
B B
EX_VSYNC42
@GM
@PM
@GM
@PM
@GM
@PM
R187 0
R0402 +/-5%
R189 0
R0402 +/-5%
R191 0
R0402 +/-5%
R192 0
R0402 +/-5%
@GM
@PM
@GM
@PM
R178
R179
150
150
R0402
+/-5%
+/-5%
R0402
Layout Note:
Place these resistors
close to the CRT-out
connector
1
5
U39
2 4
74HCT1G125
3
R180
150
+/-5%
R0402
5V_S0
1
5
U38
2 4
3
*
50V, NPO, +/-0.25pF
BC251
0.1uF
*
C0402
74HCT1G125
4
Ferrite bead impedance: 47ohm@100MHz
CRT_G_1
CRT_B_1
*
C9
3.3pF
C0402
Dummy
HSYNC_5
VSYNC_5
*
50V, NPO, +/-0.25pF
16V, Y5V, +80%/-20%
C10
3.3pF
C0402
Dummy
R181 0 R0402
R183 0 R0402
C11
3.3pF
C0402
Dummy
50V, NPO, +/-0.25pF
+/-5%
+/-5%
L6
21
FB L0603 47 Ohm
L7
21
FB L0603 47 Ohm
L8
21
FB L0603 47 Ohm
JVGA_HS
JVGA_VS
*
50V, NPO, +/-0.25pF
C12
3.3pF
C0402
Dummy
CRT_R
CRT_G
CRT_B
*
50V, NPO, +/-0.25pF
3
This page
Modified by Ke-Cheng 0923 am
*
C13
3.3pF
C0402
Dummy
C14
3.3pF
C0402
Dummy
50V, NPO, +/-0.25pF
3D3V_S0
21
D5
BAV99
3
21
D6
BAV99
3
21
D7
BAV99
3
CRT_B
CRT_RCRT_R_1
CRT_G
2
BC249
33pF
C0603
5V_CRT_S05V_S0
BC248
10nF
*
25V, X7R, +/-10%
C0402
19
17
5
15
10
4
14
9
3
13
8
2
12
7
1
11
BC250
33pF
*
C0603
50V, NPO, +/-5%
6
16
18
CLK_DDC1_5
JVGA_VS
CRT_B
JVGA_HS
CRT_G
DAT_DDC1_5
CRT_R
50V, NPO, +/-5%
C15
100pF
C0402
D4
CH501H-40
2 1
R172
3.3K
+/-5%
R0402
*
50V, NPO, +/-5%
F1
*
F1210_1.1A
R173
3.3K
+/-5%
R0402
C16
*
*
100pF
C0402
50V, NPO, +/-5%
DDC_CLK & DATA level shift
3D3V_S02D5V_S0
R612
0
R0402
+/-5%
@GM
Dummy
R613 0
+/-5%
R0402
R185
2.2K
+/-5%
R0402
B_GMCH_DDCDATA7
EX_DDCDATA42
GMCH_DDCCLK7
EX_DDCCLK42
R188 0
R0402 +/-5%
R190 0
R0402 +/-5%
R193 0
R0402 +/-5%
R194 0
R0402 +/-5%
@GM
@PM
@GM
@PM
@GM
R186
2.2K
+/-5%
R0402
Q1
@GM
DDCDATA DAT_DDC1_5
2N7002EPT
DDCCLK
Pull High IN THE
EXT-Graphic Card
R184
2.2K
+/-5%
R0402
G
DS
G
Q2
2N7002EPT
1
CN3
VGA15P
Change VCC from
3.3V to 2.5V 10/27
03'
CLK_DDC1_5
DS
5V @ ext. CRT side
33pF
BC252
C0603
50V, NPO, +/-5%
*
*
*
*
L9
1 2
BLM21B102SPT
BC253
150pF
C0603
BC255
*
L10
1 2
BLM21B102SPT
BC257
150pF
C0603
BC260
*
L11
1 2
BLM21B102SPT
BC262
150pF
C0603
3
*
33pF
C0603
50V, NPO, +/-5%
*
33pF
C0603
50V, NPO, +/-5%
*
BC254
270pF
50V, X7R, +/-10%
C0402
BC258
270pF
50V, X7R, +/-10%
C0402
BC263
270pF
50V, X7R, +/-10%
C0402
TV_COMP
TV_CRMA
TV OUT CONN
5V_S0
5V_S0
3
D8
BAV99
*
21
D10
BAV99
BC256
0.1uF
16V, Y5V, +80%/-20%
C0402
BC261
0.1uF
*
16V, Y5V, +80%/-20%
C0402
5
TV_COMP
5V_S0
3
BC259
D9
BAV99
0.1uF
*
16V, Y5V, +80%/-20%
C0402
21
21
TV_LUMA
A A
3
TV_CRMA
GMCH_TV_LUMA7
EX_TV_LUMA42
GMCH_TV_COM7
EX_TV_COPM42
GMCH_TV_CRMA7
EX_TV_CRMA42
4
R195 0
R0402 +/-5%
R196 0
R0402 +/-5%
R198 0
R0402 +/-5%
R199 0
R0402 +/-5%
R201 0
R0402 +/-5%
R202 0
R0402 +/-5%
@GM
@PM
@GM
@PM
@GM
@PM
GMCH_TV_LUMA_1
R197
150
R0402
+/-5%
GMCH_TV_COM_1
R200
150
+/-5%
R0402
GMCH_TV_CRMA_1
R203
150
+/-5%
R0402
TV1
4
2
6
MINI DIN 7
TV_LUMA
7
3
89
1
5
TECHNOLOGY COPR.
Title
Document Number Rev
2
Date: Sheet
CRT/S-Video
S06 MAINBOARD
1
A
of
12 45Thursday, December 16, 2004
Page 13
5
hocnghetructuyen.vn
4
3
2
1
R212
330
+/-5%
R0603
12
D12
LED_Yellow
MEDIA_LED#
3D3V_S0
4
CHG_LED#
3 5
R214
330
+/-5%
R0603
12
D14
LED_Yellow
CHG_LED2#
U5
1
2
NC7SZ32
Y
D15
802.11_LINK 28
802.11_ACT 28
R205
R204
100K
100K
+/-5%
+/-5%
R0402
R0402
TXAOUT1-42
TXAOUT1+42
LDDC_CLK7,42
LDDC_DATA7,42
DCBATOUT
BC264
10uF
25V, Y5V, +80%/-20%
R215
330
+/-5%
R0603
12
34
G
LED_Yellow Green
CAPS#
R217
R216
330
330
+/-5%
+/-5%
R0603
R0603
12
12
D16
D17
LED_Yellow
LED_Yellow
NUM#
EC_BLON29
MEDIA_LED#19
NUM#29
CAPS#29
CHG_LED2#29
CHG_LED#29
PWR_LED#29
*
C1210
MEDIA_LED#
BRIGHTNESS_PWM_1
PWR_LED#
3D3V_S0
FB L0805 300 Ohm
FB9
BC271
*
1nF
C0402
25V, Y5V, +80%/-20%
*
21
BC286
C0603
TXAOUT1TXAOUT1+
TXACLK-42
TXACLK+42
LDDC_DATA BRIGHTNESS_PWM_1
INVT_PWR
BC265
0.1uF
BC273
1nF
C0402
1nF
*
*
*
C0402
Dummy
BC692
1nF
C0402
BC275
*
1nF
C0402
*
LCD / INVERTER
CN17
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
BC277
1nF
C0402
29
BC267
*
1nF
C0402
BC266
0.1uF
C0603
*
BC276
1nF
C0402
*
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
31
Header_2X15_LCD
BC278
*
1nF
C0402
EC_BLONLDDC_CLK
CVR1
4
Header_1X2
LCDVDD_S0LCDVDD_S0
AC
NC
NC
29
30
123
TXAOUT0- 42
TXAOUT0+ 42
TXAOUT2- 42
TXAOUT2+ 42
R208 0
R0402 +/-5%
R206 0
R0402 +/-5%
R623 0
R0402 +/-5%
R209
0
R0402
+/-5%
Dummy
TOP VIEW
LCD CONN
C17
*
1nF
50V, X7R, +/-10%
C0402
Dummy
Dummy
1
2
Pull High IN EC page
WLANONLED#
WLANONLED
2
Q3
DTC144EUA
1 3
D D
LED
3D3V_S0 3D3V_S5 3D3V_S0 3D3V_S03D3V_S5 3D3V_S0
R211
330
+/-5%
C C
PWR_LED#
PWR: Green,KPT-1608SGC
CHG_LED#: Orang/Green KPTB-1615YSGC
B B
Other: Yellow, KPT-1608YC
R0603
12
D11
LED_Bright Green
WLANONLED#
LED Status Table
Power/Suspend
LED
Power LED
Storage
Access LED
Caps
Lock LED
Number
Lock LED
A A
WirelessLAN
LED
S0/S3 S4 Enter/Resume
Stay On(Green) Need blinking
AC MODE
Full
Charging
Discharging Charging
Green X Orange
Critical
Full
Low
Charging
X X X X Or ange
Yellow
Yellow
Yellow
Yellow(Stay On when Enable)
Battery Only
Discharging
Charging
Critical
Low
Flash
SI3865_R2
R222
47K
+/-5%
R0402
LCDVDD_S0
Layout 40 mil
BC282
1uF
*
10V, Y5V, +80%/-20%
C0603
3D3V_S0
R219 100K
GMCH_LCDVDD_ON7
EX_LCDVDD_ON42
R220 1K
R0402 +/-5%
R221 0
R0402 +/-5%
@GM
@PM
R0402 +/-5%
*
BC280
1uF
C0603
*
SI3865_R1C1
BC281
0.1uF
16V, Y5V, +80%/-20%
C0402
BC279 5.6nF
C0603 50V, X7R, +/-10%
6
R1/C1
5
ON/OFF
4
S2
U6
Si3865DV
*
1
R2
2
D2
3
D2
LCDVDD_S0
*
PWM from KBC
BRIGHTNESS_PWM 29
LBKLT_CRTL 7
PWM from Alviso
EX_BRIGHTNESS 42
BC269
PWM from EX_Graphic
0.1uF
16V, Y5V, +80%/-20%
*
C0402
COVERUPCOVER_SW#
C18
0.22uF
R218
*
100
16V, Y5V, +80%/-20%
R0402
C0603
+/-5%
COVER_SW#
BC283
10uF
*
C0805
COVERUP 29
BC284
0.1uF
C0402
3D3V_S5
3
BC285
0.1uF
*
C0402
21
D18
BAV99
Dummy
5
Title
TECHNOLOGY COPR.
LCD/Inverter
Document Number Rev
S06 MAINBOARD
4
3
2
Date: Sheet
1
13 45Thursday, December 16, 2004
A
of
Page 14
5
hocnghetructuyen.vn
RTC circuitry
4
BC287 4 . 7pF
C0402 50V, NPO, +/-0.25pF
3
2
1
*
3D3V_S0
LDRQ1J
H_A20GATE 29
1D05V_S0
H_RCIN# 29
1D05V_S0
R228
10K
+/-5%
R0402
R511
56
+/-5%
R0402
Dummy
1D05V_S0
R241
75
+/-5%
R0402
NO_STUFF
R234
56
+/-5%
R0402
H_FERR# 4
PM_THRMTRIP# 4,7
2 3
41
X2
XTAL-32.768kHz
ACZ_RST#_R
ACZ_SDATAIN026
ACZ_SDATAIN120
TP44
IDE_IORDY19
IDE_IRQ1419
IDE_DACK#19
IDE_IOW#19
IDE_IOR#19
R227
10M
+/-5%
R0402
X1_RCT
X2_RCT
RCT_RST#
INTRUDER#
ACZ_SYNC_R
1
ACZ_SDATAOUT_R
AA2
AA3
AA5
D12
B12
D11
B11
E12
E11
C13
C12
C11
E13
C10
A10
B10
AC19
AE3
AD3
AG2
AF2
AD7
AC7
AF6
AG6
AC2
AC1
AG11
AF11
AF16
AB16
AB15
AC14
AE16
F13
F12
F11
F10
Y1
Y2
B9
C9
RTCX1
RTCX2
RTCRST#
INTRUDER#
INTVRMEN
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LANRXD[0]
LANRXD[1]
LANRXD[2]
LANTXD[0]
LANTXD[1]
LANTXD[2]
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN[0]
ACZ_SDIN[1]
ACZ_SDIN[2]
ACZ_SDO
SATALED#
SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP
SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
U7A
LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]
LPC
RTCLAN
LDRQ[0]#
LDRQ[1]#/GPI[41]
LFRAME#/FWH[4]
A20GATE
CPUSLP#
DPRSLP#
DPSLP#
CPU
CPUPWRGD/GPO[49]
IGNNE#
INIT3_3V#
STPCLK#
THRMTRIP#
SATA AC-97/AZALIA
IDE
DDREQ
ICH6-M
A20M#
FERR#
INIT#
INTR
RCIN#
NMI
SMI#
DA[0]
DA[1]
DA[2]
DCS1#
DCS3#
DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]
P2
N3
N5
N4
N6
P4
P3
AF22
AF23
AE27
AE24
AD27
AF24
AG25
AG26
AE22
AF27
AG24
AD23
AF25
AG27
AE26
AE23
AC16
AB17
AC17
AD16
AE17
AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13
AB14
B_LPC_LAD0
B_LPC_LAD1
B_LPC_LAD2
B_LPC_LAD3
LPC_LDRQ0# 30
LDRQ1J
B_LPC_LFRAME# 29,30
H_A20M# 4
H_CPUSLP# 4,6
H_DPRSLP#
H_DPSLP#
H_FERR_R
H_PWRGD 4
H_IGNNE# 4
H_INIT# 4
H_INTR 4
H_RCIN#_1
H_NMI 4
H_SMI# 4
H_THERMTRIP_R
H_STPCLK# 4
IDE_A0 19
IDE_A1 19
IDE_A2 19
IDE_CS#0 19
IDE_CS#1 19
IDE_D0 19
IDE_D1 19
IDE_D2 19
IDE_D3 19
IDE_D4 19
IDE_D5 19
IDE_D6 19
IDE_D7 19
IDE_D8 19
IDE_D9 19
IDE_D10 19
IDE_D11 19
IDE_D12 19
IDE_D13 19
IDE_D14 19
IDE_D15 19
IDE_DREQ 19
B_LPC_LAD0 29,30
B_LPC_LAD1 29,30
B_LPC_LAD2 29,30
B_LPC_LAD3 29,30
H_A20GATE_1
H_DPRSLP# 4
H_DPSLP# 4
R243
56
R0402
+/-5%
3D3V_S0
R232
10K
+/-5%
R0402
D21
21
CH501H-40
R236 56
R0402 +/-5%
3D3V_S0
R237
10K
+/-5%
R0402
D22
21
CH501H-40
Layout Note: R632 needs to placed
within 2" of ICH6, R634 must be placed
within 2" of R632 w/o stub.
H_DPSLP#
3D3V_AUX_S5
D D
R231
1K
+/-5%
R0402
RTCJ1
Header_1X3
C C
B B
1
BAT_D
2
BAT
12345
D37
3
BAT54C
R229 180K
R0402 +/-5%
R230 1M
R0402 +/-5%
RTC_SENSE# 29
R625
100K
+/-5%
R0402
RTC_AUX_S5
C19
1uF
*
10V, Y5V, +80%/-20%
C0603
3D3V_S0
BC289
0.1uF
*
16V, Y5V, +80%/-20%
C0402
ACZ_BITCLK26
ACZ_SYNC20,26
ACZ_RST#20,26
ACZ_SDATAOUT20,26
*
BC288 4.7pF
C0402 50V, NPO, +/-0.25pF
ACZ_BITCLK
R239 39 R0402 +/-5%
R240 39 R0402 +/-5%
R242 39 R0402 +/-5%
A A
TECHNOLOGY COPR.
Title
ICH6(1 of 4)
Document Numbe r Rev
5
S06 MAINBOARD
of
4
3
2
Date: Sheet
14 45Friday, December 17, 2004
1
A
Page 15
5
hocnghetructuyen.vn
4
3
2
1
R295
10K
+/-5%
R0402
Dummy
R299
10K
+/-5%
R0402
U7C
H25
PERn[1]
H24
PERp[1]
G27
PETn[1]
G26
PETp[1]
K25
PERn[2]
K24
PERp[2]
J27
PETn[2]
J26
PETp[2]
M25
PERn[3]
M24
PERp[3]
L27
PETn[3]
L26
PETp[3]
P24
PCI-EXPRESSDirect Media Interface
PERn[4]
P23
PERp[4]
N27
PETn[4]
N26
PETp[4]
T25
DMI[0]RXN
T24
DMI[0]RXP
R27
DMI[0]TXN
R26
DMI[0]TXP
V25
DMI[1]RXN
V24
DMI[1]RXP
U27
DMI[1]TXN
U26
DMI[1]TXP
Y25
DMI[2]RXN
Y24
DMI[2]RXP
W27
DMI[2]TXN
W26
DMI[2]TXP
AB24
DMI[3]RXN
AB23
DMI[3]RXP
AA27
DMI[3]TXN
AA26
DMI[3]TXP
AD25
DMI_CLKN
AC25
DMI_CLKP
F24
F23
C23
D23
C25
C24
C27
OC[0]#
B27
OC[1]#
B26
OC[2]#
C26
OC[3]#
C21
USBP[0]N
D21
USBP[0]P
A20
USBP[1]N
B20
USBP[1]P
D19
USBP[2]N
C19
USBP[2]P
A18
USBP[3]N
B18
USBP[3]P
E17
USBP[4]N
D17
USBP[4]P
B16
USBP[5]N
A16
USBP[5]P
C15
USBP[6]N
D15
USBP[6]P
A14
USBP[7]N
B14
USBP[7]P
A22
USBRBIAS#
B22
USBRBIAS
ICH6-M
GPIO
DMI_ZCOMP
DMI_IRCOMP
OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]
USB
POWER MGT CLOCKS
Planar
ID(2,1,0)
SA: 0,0,0
SB: 0,0,1
SC: 0,1,0
SD: 0,1,1
DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7
DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7
DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7
DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7
CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3
DMI_IRCOMP_R
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
B_USB_PN0 33
B_USB_PP0 33
B_USB_PN1 33
B_USB_PP1 33
B_USB_PN7 33
B_USB_PP7 33
USB_RBIAS_PN
Place within 500 mils of ICH
ICH6-M Strapping Options
FUNCTION
REF
No Reboot
R7F9
A16 Swap
R7F8
Override
Boot BIOS
R7F7
1D5V_S0
Place within 500 mils of ICH
R261
24.9
+/-1%
R0402
RN57
*
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
3D3V_S5
R285 22.6
R0402 +/-1%
1
2
3
4
5
10K 10P8R0603 +/-5%
3D3V_S0
R275 1K
R0402 +/-5%
R279 1K
R0402 +/-5%
R282 1K
R0402 +/-5%
R513 1K
R0402 +/-5%
R603 1K
R0402 +/-5%
DEFAULT OPTIONAL OVERRIDE
NO_STUFF
NO_STUFF
NO_STUFF
Dummy
Dummy
Dummy
Dummy
Dummy
STUFF
STUFF
STUFF
USB_OC#7
USB_OC#6
USB_OC#5
USB_OC#4
R7F9
ICH_SPKR
R7F8
FWH_WP#
R7F7
PCI_GNT#5
PCI_GNT#4
PCI_GNT#3
3D3V_S5
10
9
8
7
6
R255
33
+/-5%
R0402
*
B_PM_CLKRUN#
R262
10K
+/-5%
R0402
Dummy
PWRBTN#_ICH29
DS
Q4
2N7002EPT
Dummy
3D3V_S0
R254 10K R0402 +/-5% @GM
R256 10K R0402 +/-5% @GM
B_SMB_CLK17
R257
33
+/-5%
R0402
Dummy
BC290
33pF
50V, NPO, +/-5%
C0603
Dummy
B_SMB_DATA17
ICH_SPKR26
PM_SUS_STAT#29
SMC_RUNTIME_SCI#29
SMC_WAKE_SCI#_R29
PM_STPPCI#3
PM_STPCPU#3,39
GMODULE_RST#42
TP64
CLOSE TO SB
B_PM_CLKRUN#21,24,28,29,30,43
3D3V_S0
PM_SUS_CLK17
PM_SLP_S3#_ICH29
PM_SLP_S4#_ICH29
PWROK18
R281 100 R0402 +/-5%
D24 CH501H-40
2 1
PLT_RST1#
3D3V_S5
PLANARID0
PLANARID1
PLANARID2
PM_BMBUSY#7
INT_SERIRQ21,28,29,30,43
THRM#18
CLK_ICH143
CLK48_ICH3
R260 0
R0402 +/-5%
1
VROK7,16
PWRBTN#_ICH-1
R287
10K
+/-5%
R0402
Dummy
3D3V_S0
SMB_LINK_ALERT#
DBRESET#
TP65
GM/PM
TP73
PM_DPRSLPVR_R
PM_BATLOW#_R
R288
10K
+/-5%
R0402
R293
10K
+/-5%
R0402
Dummy
R297
10K
+/-5%
R0402
PM_RI#
SATA0_R0
ICH_GID1
ICH_GID0
PLANARID2
SMLINK0
SMLINK1
MCH_SYNC#
SMB_ALERT#
ICH_GPI22
Dummy
GRST#
1
PLANARID0
PLANARID1
PCIE_WAKE#
1
R289
100K
+/-5%
R0402
Dummy
R294
10K
+/-5%
R0402
Dummy
R298
10K
+/-5%
R0402
T2
RI#
AF17
SATA[0]GP/GPI[26]
AE18
SATA[1]GP/GPI[29]
AF18
SATA[2]GP/GPI[30]
AG18
SATA[3]GP/GPI[31]
Y4
SMBCLK
W5
SMBDATA
Y5
LINKALERT#
W4
SMLINK[0]
U6
SMLINK[1]
AG21
MCH_SYNC#
F8
SPKR
W3
SUS_STAT#/LPCPD#
U2
SYS_RESET#
AD19
BMBUSY#
AE19
GPI[7]
R1
GPI[8]
W6
SMBALERT#/GPI[11]
M2
GPI[12]
R6
GPI[13]
AC21
STP_PCI#
AB21
GPO[19]
AD22
STP_CPU#
AD20
GPO[21]
AD21
GPO[23]
V3
GPIO[24]
P5
GPIO[25]
R3
GPIO[27]
T3
GPIO[28]
AF19
CLKRUN#
AF20
GPIO[33]
AC18
GPIO[34]
U5
WAKE#
AB20
SERIRQ
AC20
THRM#
AF21
VRMPWRGD
E10
CLK14
A27
CLK48
V6
SUSCLK
T4
SLP_S3#
T5
SLP_S4#
T6
SLP_S5#
AA1
PWROK
AE20
DPRSLPVR
V2
BATLOW#
U1
PWRBTN#
V5
LAN_RST#
Y3
RSMRST#
B_PCI_AD[31..0]21,24,28,43
D D
B_PCI_FRAME#21,24,28,43
C C
B_PCI_FRAME#
B_PCI_IRDY#
B_PCI_TRDY#
B_PCI_STOP#
3D3V_S0
B_PCI_SERR#
INT_PIRQH#
B_PCI_PERR#
PCI_LOCK#
3D3V_S0
PCI_REQ#0
THRM#
B B
PCI_REQ#5
MCH_SYNC#
3D3V_S0
A A
INT_PIRQC#24,28
R263 100 R0402 +/-5%
R265 100 R0402 +/-5%
R266 100 R0402 +/-5%
RN58
*
1
2
3
4
5
10K 10P8R0603 +/-5%
RN59
*
1
2
3
4
5
10K 10P8R0603 +/-5%
RN60
*
1
2
3
4
5
10K 10P8R0603 +/-5%
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
10
9
8
7
6
10
9
8
7
6
10
9
8
7
6
B_PCI_AD0
B_PCI_AD1
B_PCI_AD2
B_PCI_AD3
B_PCI_AD4
B_PCI_AD5
B_PCI_AD6
B_PCI_AD7
B_PCI_AD8
B_PCI_AD9
B_PCI_AD10
B_PCI_AD11
B_PCI_AD12
B_PCI_AD13
B_PCI_AD14
B_PCI_AD15
B_PCI_AD16
B_PCI_AD17
B_PCI_AD18
B_PCI_AD19
B_PCI_AD20
B_PCI_AD21
B_PCI_AD22
B_PCI_AD23
B_PCI_AD24
B_PCI_AD25
B_PCI_AD26
B_PCI_AD27
B_PCI_AD28
B_PCI_AD29
B_PCI_AD30
B_PCI_AD31
AC5
AD5
AF4
AG4
AC9
3D3V_S0
INT_PIRQD#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
3D3V_S0
B_PCI_DEVSEL#
PCI_REQ#2
PCI_REQ#3
B_PM_CLKRUN#
3D3V_S0
INT_PIRQB#
INT_PIRQC#
INT_PIRQA#
INT_SERIRQ
E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4
J3
N2
L2
M1
L3
U7B
PCI
REQ[4]#/GPI[40]
GNT[4]#/GPO[48]
REQ[5]#/GPI[1]
GNT[5]#/GPO[17]
REQ[6]#/GPI[0]
GNT[6]#/GPO[16]
DEVSEL#
PLTRST#
PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#/GPI[4]
PIRQ[H]#/GPI[5]
ICH6-M
PM_RI#
SMB_ALERT#
SMB_LINK_ALERT#
SMLINK0
SMLINK1
PCIE_WAKE#
PM_BATLOW#_R
DBRESET#
ICH_GPI22
R290
33
+/-5%
R0402
Dummy
BC292
33pF
50V, NPO, +/-5%
C0603
Dummy
R296
10K
+/-5%
R0402
GM/PM
@GM
R300
0
H :GM L:PM
+/-5%
R0402
@PM
REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#
C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#
IRDY#
PAR
PCIRST#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
PCICLK
PME#
RSVD[6]
RSVD[7]
RSVD[8]
TP[3]
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
FRAME#
Interrupt I/F
PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#
RESERVED
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
ICH6 Pullups
*
3D3V_S5
PCI_REQ#0
L5
C1
PCI_REQ#1
B5
B6
PCI_REQ#2
M5
F1
PCI_REQ#3
B8
PCI_GNT#3
C8
PCI_REQ#4
F7
PCI_GNT#4
E7
PCI_REQ#5
E8
PCI_GNT#5
F6
PCI_REQ#6
B7
FWH_WP#
D8
J6
H6
G4
G2
A3
E1
R258 47 R0402 +/-5%
R2
C3
E3
PCI_LOCK#
C5
G5
J1
J2
R259 47 R0402 +/-5%
R5
G6
P6
Int. PH
INT_PIRQE#
D9
INT_PIRQF#
C7
INT_PIRQG#
C6
INT_PIRQH#
M3
AD9
AF8
AG8
U3
R267 10K
R0402 +/-5%
R269 10K
R0402 +/-5%
R271 10K
R0402 +/-5%
R273 10K
R0402 +/-5%
R276 10K
R0402 +/-5%
R277 1K
R0402 +/-5%
R278 8.2K
R0402 +/-5%
R280 10K
R0402 +/-5%
R512 10K
R0402 +/-5%
CLK_ICH14CLK48_ICH
R291
33
+/-5%
R0402
Dummy
BC293
33pF
*
50V, NPO, +/-5%
C0603
Dummy
PURE_HW_SHUT DOW N#18
PCI_REQ#0 21,43
PCI_GNT#0 21,43
PCI_REQ#1 28
PCI_GNT#1 28
PCI_REQ#2 24
PCI_GNT#2 24
this group not use!
TP59
1
B_PCI_C/BE#0 21,24,28,43
B_PCI_C/BE#1 21,24,28,43
B_PCI_C/BE#2 21,24,28,43
B_PCI_C/BE#3 21,24,28,43
B_PCI_IRDY# 21,24,28,43
B_PCI_DEVSEL# 21,24,28,43
B_PCI_PERR# 21,24,28
B_PCI_SERR# 21,24,28
B_PCI_STOP# 21,24,28,43
B_PCI_TRDY# 21,24,28,43
B_ICH_PME#_1
R264 100 R0402 +/-5%
D23
CH501H-40
INT_PIRQE# 21,43
3D3V_S5
PCI_REQ#6
PCI_REQ#1
PCI_REQ#4
3D3V_S5
R286
4.7K
+/-5%
R0402
T=22ms
R292
100K
+/-5%
R0402
HW_SHUT18
CLK_ICHPCI
B_PCI_PAR 21,24,28,43
PCIRST1# 21,24,28,43
PLT_RST1# 7,17,29,30,42
CLK_ICHPCI 3
21
B_ICH_PME# 22,24,29
R268 10K
R0402 +/-5%
R270 10K
R0402 +/-5%
R272 10K
R0402 +/-5%
PM_DPRSLPVR39
21
D38
CH501H-40
PM_RSMRST#
BC291
4.7uF
*
10V, Y5V, +80%/-20%
C0805
D26
2 1
CH501H-40
G
5
Title
TECHNOLOGY COPR.
ICH6(2 of 4)
Document Number Rev
S06 MAINBOARD
4
3
2
Date: Sheet
1
15 45Friday, Decemb er 17 , 2004
A
of
Page 16
5
hocnghetructuyen.vn
Layout Note:
Place above caps within
100 mils of ICH near F27, P27, AB27
1D5V_S0
Layout Note:
IDE decoupling
BC311
*
0.1uF
C0603
Layout Note:
PCI decoupling
NO_STUFF
*
*
0.1uF
BC355
10uF
C0805
Dummy
TC9
220uF
*
2.5V, +/-20%
CTX
BC312
*
0.1uF
C0603
BC322
10uF
*
*
C0805
Dummy
1D5V_S0
Place within 100
mils of ICH
near pin AG9
*
1D5V_S0
R305 0
R0603 +/-5%
Place within 100
mils of ICH
pin AE1
Place within 100
mils of ICH
pin A13
3D3V_S5
BC299
*
0.1uF
C0603
BC313
*
0.1uF
C0603
NO_STUFF
BC323
10uF
C0805
Dummy
BC329
*
0.1uF
C0603
1D5V_S0
BC335
*
0.1uF
C0603
1D5V_GPLL_ICH_S0
BC340
0.1uF
16V, X7R, +/-10%
C0603
1D5V_ICH_S0
BC343
0.1uF
C0603
BC350
0.1uF
C0603
R307 0
R0603 +/-5%
*
1D5V_S0
Dummy
BC330
*
0.1uF
C0603
BC336
*
0.1uF
C0603
*
3D3V_S0
*
V3D3A_VCCPSUS
BC360
*
0.1uF
C0603
BC300
0.1uF
C0603
BC314
*
0.1uF
C0603
BC351
0.1uF
C0603
Place within 100
mils of ICH
pin V7
D D
3D3V_S0
3D3V_S0
NO_STUFF
BC319
*
0.1uF
C0603
C C
B B
A A
Dummy
1D5V_S0
Place within 100
mils of ICH
Place within 100
mils of ICH
pin AG10
BC352
*
0.1uF
C0603
Dummy
Dummy
R303
Place within 100
mils of ICH
near E26, E27
BC353
*
0.1uF
C0603
BC310
*
0.1uF
C0603
NO_STUFFNO_STUFF
BC320
BC321
*
0.1uF
0.1uF
C0603
C0603
Dummy
Dummy
Place within 100
mils of ICH
near pin AG5
1D5V_GPLL_ICH_S0
0R0603 +/-5%
BC339
10uF
*
C0805
3D3V_S0
3D3V_S0
BC346
*
0.1uF
C0603
1D5V_S0
BC354
*
*
0.1uF
C0603
Dummy
BC342
C0603
BC301
0.1uF
C0603
BC331
0.1uF
C0603
BC337
0.1uF
C0603
*
4
U7E
AA22
VCC1_5_B
AA23
VCC1_5_B
AA24
*
*
*
VCC1_5_B
AA25
VCC1_5_B
AB25
VCC1_5_B
AB26
VCC1_5_B
AB27
VCC1_5_B
F25
VCC1_5_B
F26
VCC1_5_B
F27
VCC1_5_B
G22
VCC1_5_B
G23
VCC1_5_B
G24
VCC1_5_B
G25
VCC1_5_B
H21
VCC1_5_B
H22
VCC1_5_B
J21
VCC1_5_B
J22
VCC1_5_B
K21
VCC1_5_B
K22
VCC1_5_B
L21
VCC1_5_B
L22
VCC1_5_B
M21
VCC1_5_B
M22
VCC1_5_B
N21
VCC1_5_B
N22
VCC1_5_B
N23
VCC1_5_B
N24
VCC1_5_B
N25
VCC1_5_B
P21
VCC1_5_B
P25
VCC1_5_B
P26
VCC1_5_B
P27
VCC1_5_B
R21
VCC1_5_B
R22
VCC1_5_B
T21
VCC1_5_B
T22
VCC1_5_B
U21
VCC1_5_B
U22
VCC1_5_B
V21
VCC1_5_B
V22
VCC1_5_B
W21
VCC1_5_B
W22
VCC1_5_B
Y21
VCC1_5_B
Y22
VCC1_5_B
AA6
VCC1_5_A
AB4
VCC1_5_A
AB5
VCC1_5_A
AB6
VCC1_5_A
AC4
VCC1_5_A
AD4
VCC1_5_A
AE4
VCC1_5_A
AE5
VCC1_5_A
AF5
VCC1_5_A
AG5
VCC1_5_A
AA7
VCC1_5_A
AA8
VCC1_5_A
AA9
VCC1_5_A
AB8
VCC1_5_A
AC8
VCC1_5_A
AD8
VCC1_5_A
AE8
VCC1_5_A
AE9
VCC1_5_A
AF9
VCC1_5_A
AG9
VCC1_5_A
AC27
VCCDMIPLL
E26
VCC3_3
AE1
VCCSATAPLL
AG10
VCC3_3
A13
VCCLAN3_3/VCCSUS3_3
F14
VCCLAN3_3/VCCSUS3_3
G13
VCCLAN3_3/VCCSUS3_3
G14
VCCLAN3_3/VCCSUS3_3
A11
VCCSUS3_3
U4
VCCSUS3_3
V1
VCCSUS3_3
V7
VCCSUS3_3
W2
VCCSUS3_3
Y7
VCCSUS3_3
A17
VCCSUS3_3
B17
VCCSUS3_3
C17
VCCSUS3_3
F18
VCCSUS3_3
G17
VCCSUS3_3
G18
VCCSUS3_3
COREIDEPCI
PCIE
SATA
USB CORE USB
PCI/IDE
REF
VCCLAN1_5/VCCSUS1_5
VCCLAN1_5/VCCSUS1_5
ICH6-M
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCSUS1_5
VCCSUS1_5
VCCSUS1_5
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC2_5
VCC2_5
V5REF
V5REF
V5REF_SUS
VCCUSBPLL
VCCSUS3_3
VCCRTC
V_CPU_IO
V_CPU_IO
V_CPU_IO
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19
AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12
P1
M7
L7
L4
J7
H7
H1
E4
B1
A6
U7
R7
G19
G20
F20
E24
E23
E22
E21
E20
D27
D26
D25
D24
G8
AB18
P7
AA18
A8
F21
A25
A24
AB3
G11
G10
AG23
AD26
AB22
G16
G15
F16
F15
E16
D16
C16
BC356
C0603
3
BC294
BC295
*
0.1uF
0.1uF
C0603
C0603
BC302
*
0.1uF
C0603
Dummy
Place within 100
mils of ICH pin
AG13, AG16
Layout Note:
Distribute in PCI section
near pin A2-A6 near D1-H1
BC324
0.1uF
C0603
BC338
0.1uF
C0603
V5REF_S0
V5REF_S5
BC345
*
0.1uF
C0603
3D3V_ICH_S5
*
0.1uF
BC296
*
0.1uF
C0603
BC303
*
0.1uF
C0603
Dummy
3D3V_S0
BC315
BC316
*
0.1uF
C0603
BC333
0.1uF
C0603
*
BC357
C0603
*
0.1uF
C0603
BC325
*
*
0.1uF
C0603
1D5V_S5
1D5V_S0
*
*
V2D5S_PCI_IDE
R304 0
R0603 +/-5%
Layout Note:
Place near AB18
1D5V_S0
Place within 100
mils of ICH
pin G10 Place near AB3
BC349
*
0.1uF
C0603
*
0.1uF
NO_STUFF NO_STUFF
BC297
*
*
0.1uF
*
0.1uF
BC332
C0603
2D5V_S0
1D05V_S0
*
0.1uF
C0603
Dummy
3D3V_S0
0.1uF
BC344
C0603
*
BC305
0.1uF
C0603
*
*
3D3V_ICH_S5
0.1uF
BC359
0.1uF
C0603
Dummy
*
BC304
0.1uF
C0603
Dummy
ALL NO_STUFF Caps do
not have layout
requirements but if
layout allows then place
next to ICH6
BC326
C0603
BC327
C0603
BC334
0.1uF
C0603
Place both
within 100 mils
of ICH near D27
Layout Note:
Place near AG23
BC358
0.1uF
C0603
Dummy
BC306
*
C0603
Dummy
BC328
0.1uF
C0603
1D5V_S5
Place within 100
mils of ICH
Place within 100
mils of ICH
*
Layout Note:
BC347
0.1uF
C0603
R306 0
R0603 +/-5%
*
1D5V_S0
BC298
10nF
*
25V, X7R, +/-10%
C0402
*
0.1uF
VRMPWRGD39
1D5V_ICH_S0
BC341
*
0.1uF
C0603
RTC_AUX_S5
BC348
*
*
0.1uF
C0603
3D3V_S5
Place within 100
mils of ICH
pin A17
2
Layout Note:
Place near pin AA19
BC307
22uF
*
6.3V, X5R, +/-10%
C1206
Dummy
Layout Note:
Place near ICH6
V5REF_S0
16V, Y5V, +80%/-20%
V5REF_S5
16V, Y5V, +80%/-20%
*Within a gi ven well, 5VREF needs to be up before the
corresponding 3.3V rail
5V_S03D3V_S0
R301
100
+/-5%
R0402
BC309
1uF
*
10V, Y5V, +80%/-20%
C0603
5V_S53D3V_S5
R302
10
+/-5%
R0402
BC318
1uF
*
10V, Y5V, +80%/-20%
C0603
3D3V_S0
U35
53
1
2
NC7SZ08
Dummy
R601
10K
R0402
+/-5%
Dummy
BC308
0.1uF
C0402
BC317
0.1uF
C0402
R600
0
R0402
+/-5%
D27
CH501H-40
2 1
*
D28
CH501H-40
2 1
*
BC677
12
1uF
*
10V, Y5V, +80%/-20%
C0402
Dummy
1
4
VROK 7,15
5
Title
TECHNOLOGY COPR.
ICH6(3 of 4)
Document Number Rev
S06 MAINBOARD
4
3
2
Date: Sheet
1
16 45Friday, Decemb er 17 , 2004
A
of
Page 17
5
hocnghetructuyen.vn
4
3
U7D
2
1
E27
VSS
32K suspend clock output
3D3V_S5
D D
PM_SUS_CLK15
PLT_RST1#7,15,29,30,42
C C
S0_EN20,29,36,37,38,40,42
R514 0
R0603 +/-5%
Dummy
R515 0
R0603 +/-5%
Dummy
2 4
2 4
5
3
5V_S0
5
3
1
1
U37
U8
32KHZ
NC7SZ126
74HCT1G125
R309
240K
+/-5%
R0603
R311
10K
+/-5%
R0402
R308
10
R0402
+/-5%
R310
33
R0402
+/-5%
CLK32_G768 18
RSTDRV#_5 19
PCIRST# 3V to 5V level shift for HDD & CDROM
SMBUS
3D3V_S5
B B
R314
R313
10K
10K
+/-5%
+/-5%
R0402
B_SMB_CLK15
B_SMB_DATA15
A A
Q5 & Q6 connect SMLINK and
SMBUS in S) for SMBus 2.0
compliance
R0402
3D3V_S0
R312
2.2K
+/-5%
R0402
Q5
G
D S
2N7002EPT
R315
4.7K
+/-5%
R0402
G
Q6
D S
2N7002EPT
3D3V_S0
R316
4.7K
+/-5%
R0402
SMBC_ICH 3,11
B_SMBD_ICH 3,11
Y27
Y26
Y23
W25
W24
W23
V27
V26
V23
U25
U24
U23
U15
U13
R25
R24
R23
R17
R16
R15
R14
R13
R12
R11
P22
P16
P15
P14
P13
P12
N17
N16
N15
N14
N13
N12
N11
M27
M26
M23
M16
M15
M14
M13
M12
K27
K26
K23
H27
H26
H23
G21
G12
W7
W1
T27
T26
T23
T16
T15
T14
T13
T12
L25
L24
L23
L15
L13
J25
J24
J23
Y6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T1
VSS
R4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N1
VSS
M4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K7
VSS
VSS
VSS
VSS
K1
VSS
J4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G9
VSS
G7
VSS
VSS
VSS
G1
VSS
ICH6-M
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1
5
Title
TECHNOLOGY COPR.
ICH6(4 of 4)
Document Numbe r Rev
S06 MAINBOARD
of
4
3
2
Date: Sheet
17 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 18
5
hocnghetructuyen.vn
4
3
2
1
Put these two Caps near the thermal diode.
THERMDP2
THERMDN
BC361
470pF
*
50V, X7R, +/-10%
C0402
E C
B
Q8
MMBT3904
D D
SYSTEM SENSOR
R321 0 R0603+/-5%
THERMDP1
*
THERMDN
THERMDP1/DP2/THERMDN ON THE SAME LAYER
W/S = 10/5 MIL, 12 MIL AWAY FROM OTHERS
CAPS CLOSE T O G768B
HW thermal shut down tempature
setting 95 degree . Put Near CPU .
C C
BC364
2.2nF
50V, X7R, +/-10%
C0402
THERMDP2
THERMDN
BC365
2.2nF
*
50V, X7R, +/-10%
C0402
@PM
PWROK15
4
NC7SZ08
3D3V_S0
U10
5 3
@GM
2
1
R0603 +/-5%
R325
Dummy
0
5V_S0 5V_G768_S0
R317
0
R0603
16V, Y5V, +80%/-20%
+/-5%
VCC_FAN
VGA_PWROK 42
THERMDP14
THERMDN4
R326
20K
+/-5%
R0402
J6
NC
345
2
NC
1
Header_1X3
THERMDP1
THERMDN
THERMDP2
R324 10K
R0402
+/-5%
BC362
0.1uF
C0402
FAN_FB
VCC_FAN
*
G768_RST#RUNPWROK
5V_S0
R327
10K
+/-5%
R0402
21
D29
CH501H-40
Reserve for G768B
works at High
Speed
*
U9
1
OUT1
2
VCC
3
DXP1
4
DXN
5
DXP2
6
RESET#
7
GND
8
GND
G768D
BC363
10uF
10V, Y5V, +80%/-20%
C0805
16
OUT2
15
VCC
14
SMBCLK
13
FG2
12
SMBDATA
11
ALERT#
10
FG1
9
CLK
*Layout* 15 mil
BC366
16V, Y5V, +80%/-20%
0.1uF
C0402
5V_S0
G768_HW_SHDN
FAN_FB
*
R319
R320
10K
10K
+/-5%
+/-5%
R0402
R0402
THRM# 15
CLK32_G768 17
BC367
10uF
*
10V, Y5V, +80%/-20%
C0805
B_KBC_SCL1 29,42
B_KBC_DAT1 29,42
VCC_FAN
5V_S0
1
5
U36
2 4
Dummy
3
R318
10K
+/-5%
R0402
Dummy
74HCT1G125
BC368
2.2nF
*
50V, X7R, +/-10%
C0402
DS
Q7 2N7002EPT
Dummy
G
HW_SHUT
R322
100
R0402
+/-5%
Dummy
RUNPWROK
R323
10K R0402
+/-5%
Dummy
HW_SHUT 15
B B
U12
GND
NC7SZ14
1
NC
SHUTDOWN_S5#
2
A
3
5
VCC
SHUTDOWN_S536
A A
4
Y
PURE_HW_SHUTDOWN#15
U13
NC7SZ08
5V_AUX_S55V_AUX_S5
53
PURE_HW _ SHUT DOW N#
4
1
2
5V_AUX_S5
S5_EN 29,37,41
R330
10K
+/-5%
R0402
R328 18K
R0402 +/-1%
CPU_THSET
HW thermal shut down tempature
setting 95 degree . Put Near CPU .
U11
1
SET
2
GND
3
OUT#
MAX6510HAUT-T
16V, X7R, +/-10%
OUTSET
VCC
HYST
BC369
0.1uF
C0603
*
6
5
4
5V_AUX_S5
CPU_TH_HYST
R331
0
R0603
+/-5%
Dummy
5V_AUX_S5
R329
0
R0603
+/-5%
R332
0
R0603
+/-5%
Dummy
TECHNOLOGY COPR.
Title
THERMAL G768
Document Number Rev
5
S06 MAINBOARD
4
3
2
Date: Sheet
1
18 45Friday, Decemb er 17 , 2004
A
of
Page 19
5
hocnghetructuyen.vn
HDD Connector
HDD1
4
3
2
1
D D
IDE_D814
IDE_D914
IDE_D1014
High for Slave
Low for Master
R337
470
+/-5%
R0402
C C
B B
IDE_D1114
IDE_D1214
IDE_D1314
IDE_D1414
IDE_D1514
HDDCSEL1
IDE_A214
IDE_CS#114
5V_S0
DIAG
*
16V, Y5V, +80%/-20%
BC370
0.1uF
C0402
Dummy
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
HEADER_2X 2 2 ( HDD)
BC371
*
0.1uF
C0402
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
BC372
*
10uF
C0805
PBRSTDRV1#_5
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
PBIDDACK#
21
D30
SSM22LLPT
IDE_D7 14
IDE_D6 14
IDE_D5 14
IDE_D4 14
IDE_D3 14
IDE_D2 14
IDE_D1 14
IDE_D0 14
IDE_DREQ 14
IDE_IOW# 14
IDE_IOR# 14
IDE_A1 14
IDE_A0 14
IDE_CS#0 14
R333 33
R0402 +/-5%
R336 33
R0402 +/-5%
MEDIA_LED#
Master
R339
2.7K
+/-5%
R0402
Dummy
R340
10K
+/-5%
R0402
5V_S0
BC373
0.1uF
C0402
3D3V_S05V_S0
R334
4.7K
+/-5%
R0402
*
RSTDRV#_5 17
R335
4.7K
+/-5%
R0402
IDE_IORDY 14
IDE_DACK# 14
IDE_IRQ14 14
MEDIA_LED# 13
CDROM
CN6
52
49
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_DREQ
IDE_IOR#
IDE_DACK# IDE_IORDY
BAY_ID0
TP80
1
DIAG
IDE_CS#1
BC374
0.1uF
C0402
BC375
*
0.1uF
C0402
*
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
51
CD-ROM-50P
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
CD_GND
RSTDRV#_5
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
IDE_IOW#
IDE_IRQ14
IDE_A1
IDE_A0IDE_A2
IDE_CS#0
CSEL
High for Slave
Low for Master
CD_AUDL 26CD_AUDR26
CD_GND 26
MEDIA_LED# 13
CDROM_CSEL
SLAVE
R338 8.2K
R0402 +/-5%
R341 10K
R0402 +/-5%
R342 10K
R0402 +/-5%
Dummy
3D3V_S0
5V_S0
5V_S0
A A
25V, Y5V, +80%/-20%
5
4
BC376
0.1uF
C0603
BC377
*
3
10uF
*
10V, Y5V, +80%/-20%
C0805
Title
TECHNOLOGY COPR.
HDD/CDROM
Document Numbe r Rev
S06 MAINBOARD
of
2
Date: Sheet
19 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 20
5
hocnghetructuyen.vn
D D
4
3
2
1
CN7
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
H131H2
0.8P BTB_SMT 30P
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
26
28
30
24
26
28
30
32
R344 0 +/-5%
R345 0 +/-5%
S0_EN17,29,36,37,38,40,42
MDM_AUD_OUT 26
Dummy
Q9
R346
10K
+/-5%
R0402
Dummy
G
2N7002EPT
Dummy
ACZ_SYNC 14,26
ACZ_SDATAIN1 14
ACZ_BTCLK_MDC 26
DS
MDC_RINGJ 29
3D3V_S5
3D3V_S0
ACZ_RST#14,26
R624 0 +/-5%
Dummy
MDM_AUD_IN26
C C
ACZ_SDATAOUT14,26
B B
A A
TECHNOLOGY COPR.
Title
MDC
Document Numbe r Rev
5
S06 MAINBOARD
of
4
3
2
Date: Sheet
20 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 21
8
hocnghetructuyen.vn
3D3V_S0
3D3V_S0
D D
B_PCI_AD[31..0]15,24,28,43
B_PCI_C/BE#315,24,28,43
B_PCI_C/BE#215,24,28,43
B_PCI_C/BE#115,24,28,43
B_PCI_C/BE#015,24,28,43
B_PCI_AD25
B_PCI_DEVSEL#15,24,28,43
B_PCI_FRAME#15,24,28,43
B_PCI_IRDY#15,24,28,43
B_PCI_TRDY#15,24,28,43
B_PCI_STOP#1 5,24,28,43
B_PCI_PAR15,24, 28, 43
B_PCI_PERR#15,24,28
B_PCI_SERR#15,24,28
PCI_REQ#015,43
PCI_SPKR26,43
B_PM_CLKRUN#15,24, 28, 29, 30, 43
INT_SERIRQ15,28,29,30,43
*
*
@OZ711
@OZ711
@OZ711
PCLK_PCM3,43
PCI_GNT#015,43
CBUS_PME#22,28,43
INT_PIRQE#15,43
PCIRST1#15,24,28,43
BC385
4.7uF
C0805
BC389
4.7uF
C0805
CCLK_1
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CCD1#
CCD2#
CAUDIO
CSTSCHG
CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#
TP81
TP82
@OZ711
@OZ711
CCLK_143
CFRAME#43
CIRDY#43
CTRDY#43
CDEVSEL#43
CSTOP#43
CPAR43
CPERR#43
CSERR#43
CREQ#43
CGNT#43
CINT#43
CBLOCK#43
CCLKRUN#43
CRST#43
R2_D243
R2_D1443
R2_A1843
CVS143
CVS243
C C
B B
A A
CCD1#43
CCD2#43
CAUDIO43
CSTSCHG43
CC/BE3#43
CC/BE2#43
CC/BE1#43
CC/BE0#43
PME#, CLKRUN#, IRQSER# AND INTA#
MUST BE PULLED-UP ON THE MLB.
@OZ711
3D3V_S0
8
7
CVS1
CVS2
@OZ711
R350 100 R0402 +/-5%
R351 33 R 0402 +/-5%
@OZ711
1
1
BC387
BC386
0.1uF
0.1uF
*
*
*
C0402
BC390
0.1uF
C0402
@OZ711
*
7
C0402
BC391
0.1uF
C0402
U30A
PG1CSP
B_PCI_AD31
B_PCI_AD30
B_PCI_AD29
B_PCI_AD28
B_PCI_AD27
B_PCI_AD26
B_PCI_AD25
B_PCI_AD24
B_PCI_AD23
B_PCI_AD22
B_PCI_AD21
B_PCI_AD20
B_PCI_AD19
B_PCI_AD18
B_PCI_AD17
B_PCI_AD16
B_PCI_AD15
B_PCI_AD14
B_PCI_AD13
B_PCI_AD12
B_PCI_AD11
B_PCI_AD10
B_PCI_AD9
B_PCI_AD8
B_PCI_AD7
B_PCI_AD6
B_PCI_AD5
B_PCI_AD4
B_PCI_AD3
B_PCI_AD2
B_PCI_AD1
B_PCI_AD0
BC388
0.1uF
*
C0402
R10
P10
N10
T11
P11
R12
P14
R14
P13
T13
N11
T10
F5
F4
G7
G5
G4
H7
H6
H5
J5
J4
K5
K6
L6
L7
M4
M5
T5
R6
T6
N7
R7
N8
P8
R8
N9
R9
T9
H4
M6
T4
T8
J7
L4
P4
M7
N4
N6
P5
R5
P6
R4
D4
E4
K7
H8
@OZ711
6
F13
AD31
GNDE9GND
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
SERR#
REQ#
GNT#
PCI_RST#
RI_OUT#/PME#
SPKR_OUT#
SKTA_ACTV
ODR_ACTV
MF6(CLKRUN#)
MF4(MS_CD#)
MF3(SIRQ#)
MF0(INTA#)
6
GNDG6GND
5
VCC5_OZ2211
VCC3_OZ2211
R347
22K
R348
22K
J15
K19
L5
K4
G15
L14
F11
J6
GND
GND
PCI_VCCP9PCI_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCCE7CORE_VCC
XD_WE#/SC_3V#
SD_CD#T7XD_WPI/SD_WP
XD_ALE/SD_CMD/MS_BS
XD_RE#/SD/MS_3V#
XD_WPO/SC_5V#
XD/SC_CD#
U7
U9
U5
T14
N12
U11
R0402
+/-1%
R0402
+/-1%
T15
P12
N5
CORE_VCC
CORE_VCC
XD/SD/MS_D0
XD_CLE/SD/MS_CLK/VPPD1
XD_R/B#/SC_CLK
C5
T12
R11
R15
T16
R16
SKT_VCC
CAD31
CAD30
CAD29
VCCD1#/SCLK
VPPD0/SLATCH
VCCD0#/SDATA
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CCLK
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD1#
CCD2#
CAUDIO
CSTSCHG
CC/BE3#
CC/BE2#
CC/BE1#
XD/SD/MS_D3
XD/SD/MS_D2
XD/SD/MS_D1
XD_D5/SC_IO
C7
K16
N14
C15
5
CC/BE0#
XD_D7/SC_C8
XD_D6/SC_RSTC9XD_D4/SC_FCB
SC_VCC/XD_VCC
C13
C11
XD_DATA7 23
XD_DATA6 23
XD_DATA5 23
XD_DATA4 23
SD/MS/XD_DATA3 23
SD/MS/XD_DATA2 23
SD/MS/XD_DATA1 23
SD/MS/XD_DATA0 23
XD_R/B 23
SD/MS_CLK/XD_CLE 23
SD_CMD/MS_BS/XD_ALE 23
SD_WP/XD_WPI 23
XD_WPO 23
XD_WE# 23
XD_RE# 23
SD_CD# 23
XD_CD# 23
MS_CD# 23
VCC5_OZ2211 43
VCC3_OZ2211 43
CAD[31:0] 43
VCC5_OZ2211
VCC3_OZ2211
D10
E5
F6
E6
D6
F7
D9
G10
F10
D11
G11
D12
F12
D13
E13
G13
H15
J13
H16
J16
J14
K13
K14
K15
L15
L13
M14
M15
N16
M13
N13
N15
P16
E15
E14
D15
D16
E16
F15
G16
F16
D8
E11
F14
G9
G14
G8
E12
D5
M16
H13
F9
G12
P15
D7
E8
F8
E10
D14
H14
L16
4
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CCLK_1
3D3V_S03D3V_S0
4
ODR_VCC3# 23,43
BC380
4.7uF
*
*
C0805
SKT_VCC
R349 33
R0402 +/-5%
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD1#
CCD2#
CAUDIO
CSTSCHG
CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#
CCLK
CardBus-68-SKT
OPTIONAL DEDICATED
MMC/SD/SDIO/MS/MSPRO/SM/XD
FLASH MEDIA READER
3
3D3V_S0
5V_S0
BC381
4.7uF
C0805
BC382
4.7uF
*
*
C0805
CBSKT1
51
VCC
17
VCC
52
VPP
18
VPP
19
CCLK (A16)
54
CFRAME# (A23)
20
CIRDY# (A15)
53
CTRDY# (A22)
50
CDEVSEL# (A21)
49
CSTOP# (A20)
13
CPAR (A13)
14
CPERR# (A14)
59
CSERR# (WAIT*)
60
CREQ# (INPACK*)
15
CGNT# (WE*)
16
CINT# (IRQ*)
48
CBLOCK# (A19)
33
CCLKRUN# (IO16*)
58
CRESET# (RESET)
32
RFU (R2_D2)
40
RFU (R2_D14)
47
RFU (R2_A18)
43
CVS1
57
CVS2
36
CCD1# (CD1*)
67
CCD2# (CD2*)
62
CAUDIO (BVD2/SPKR*)
63
CSTSCHG (BVD1/RI*)
61
CC/BE3# (REG*)
21
CC/BE2# (A12)
12
CC/BE1# (A8)
7
CC/BE0# (CE1*)
3
2
BC378
4.7uF
*
C0805
U31
3
+3.3VIN
4
+3.3VIN
5
+5VIN
6
+5VIN
9
+12VIN
1
VCC5#
2
VCC3#
15
VPP_PGM
14
VPP_VCC
OZ2211S
BC383
BC384
*
0.1uF
0.1uF
C0402
C0402
CAD[31:0]
GND69GND70GND71GND72GND73GND74GND75GND76GND77GND78GND79GND80GND81GND82GND83GND
NC85NC
86
O2MICRO OZ2211 16PIN
SINGLE SLOT PARALLEL
BC379
*
POWER SWITCH
0.1uF
C0402
NOTE:
THIS IMPLEMENTATION DOES
NOT SUPPORT 12V VPP.
84
(IOWR*) CAD15
(IORD*) CAD13
shield
shield89shield
shield
88
90
87
VCC
VCC
VCC
VPP
OC#
SHDN#
GND
(D10) CAD31
(D9) CAD30
(D1) CAD29
(D8) CAD28
(D0) CAD27
(A0) CAD26
(A1) CAD25
(A2) CAD24
(A3) CAD23
(A4) CAD22
(A5) CAD21
(A6) CAD20
(A25) CAD19
(A7) CAD18
(A24) CAD17
(A17) CAD16
(A9) CAD14
(A11) CAD12
(OE*) CAD11
(CE2*) CAD10
(A10) CAD9
(D15) CAD8
(D7) CAD7
(D13) CAD6
(D6) CAD5
(D12) CAD4
(D5) CAD3
(D11) CAD2
(D4) CAD1
(D3) CAD0
GND
GND
GND
GND
SKT_VCC
13
12
11
10
8
16
7
CAD31
66
CAD30
65
CAD29
31
CAD28
64
CAD27
30
CAD26
29
CAD25
28
CAD24
27
CAD23
26
CAD22
25
CAD21
24
CAD20
23
CAD19
56
CAD18
22
CAD17
55
CAD16
46
CAD15
45
CAD14
11
CAD13
44
CAD12
10
CAD11
9
CAD10
42
CAD9
8
CAD8
41
CAD7
6
CAD6
39
CAD5
5
CAD4
38
CAD3
4
CAD2
37
CAD1
3
CAD0
2
68
35
34
1
TECHNOLOGY COPR.
Title
24_Cardbus
Document Numbe r Rev
S06 MAINBOARD
Date: Sheet
2
1
of
21 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 22
5
hocnghetructuyen.vn
4
3
2
1
D D
C C
B B
A A
@OZ711
3D3V_AVCC
3D3V_S0
FB1 MAY NOT BE NEEDED
AND CAN BE REPLACED BY 0 OHM RESISTOR
*
BC393 10pF
C040250V, NPO, +/-5%
X3
BC395
4.7uF
C0805@OZ711
BC397
0.1uF
C0402
@OZ711
1 2
*
X-24D576MHz
@OZ711
BC396
0.1uF
C0402
@OZ711
*
BC394 10pF
C040250V, NPO, +/-5%
@OZ711
*
*
3D3V_S0
U30B
PG1CSP
R358 5.9K
@OZ711
+/-1%R0603
R352 0
R0402 +/-5%
@OZ711
M19
CPS
N19
RI1
J19
XI
H19
XO
G1
TEST_PHY
J1
NC
R13
NC
U13
NC
U15
NC
@OZ711
3D3V_AVCC
AVCCM1AVCC
K1
3D3V_S0
F1
H1
CORE_VCC
CORE_VCC
GNDP1GNDP7GND
GND
GND
F19
P19
G19
TPA0+
TPA0-
TPB0+
TPB0-
TPA1+
TPA1-
TPB1+
TPB1-
TPBIAS0
TPBIAS1
VR_CPR
VR_CPR
C20
1uF
10V, Y5V, +80%/-20%
W13
W12
W11
W10
W9
W8
W7
W6
W14
N1
L1
L19
C0402
@OZ711
@OZ711
C22
22uF
*
6.3V, X5R, +/-10%
C1206
@OZ711
*
1 2
R354
56
+/-1%
R0402
@OZ711
C21
12
1uF
*
C0402
10V, Y5V, +80%/-20%
@OZ711
R353
5.1K
+/-1%
R0603
@OZ711
R355
56
+/-1%
R0402
@OZ711
TPA0+
TPA0- TPA0-_R
TPB0+
TPB0-
R356
56
+/-1%
R0402
@OZ711
BC392
270pF
*
C0402
50V, X7R, +/-10%
@OZ711
R357
56
+/-1%
R0402
B_ICH_PME#15,24,29 CBUS_PME# 21,28,43
L13 L14 IS FOR EMI PURPOSE
@OZ711
R532 0 R0402 +/-5%
R533 0 R0402 +/-5%
@OZ711
L13
1
4 3
Dummy
Common Choke 90 Ohm 2L
L14
1
4 3
Dummy
Common Choke 90 Ohm 2L
R534 0 R0402 +/-5%
R535 0 R0402 +/-5%
@OZ711
@OZ711
2
2
3D3V_S0
R605
10K
+/-5%
R0402
Dummy
G
Q20
D S
2N7002EPT Dummy
R6070R0402
+/-5%
Dummy
TPA0+_R
TPB0+_R
TPB0-_R
R606
10K
+/-5%
R0402
CBUS_PME#B_ICH_PME#
4
3
2
1
1394CN1
TPA+
TPATPB+
TPB-
1394 CONN
@OZ711
GND
GND
GND
GND
8
7
6
5
5
Title
TECHNOLOGY C OPR.
25_1394
Document Number Rev
S06 MAINBOARD
4
3
2
Date: Sheet
22 45Thursday, Decem be r 1 6, 2004
1
A
of
Page 23
8
hocnghetructuyen.vn
7
6
5
4
3
2
1
@OZ711
@OZ711
@OZ711
@OZ711
@OZ711
@OZ711
@OZ711
3D3V_S0
SD
Si2301DS
Q10
G
ODR_VCC
10V, Y5V, +80%/-20%
C23
12
1uF
*
C0402 @OZ711
@OZ711
C24
4.7uF
@OZ711
*
C0805
SD/MS_CLK/XD_CLE 21
SD/MS/XD_DATA3 21
SD/MS/XD_DATA2 21
SD/MS/XD_DATA1 21
SD/MS/XD_DATA0 21
SD_CMD/MS_BS/XD_ALE 21
D D
R361 10K
R0402 +/-5%
@OZ711
SM
XD
R359
22K
R360
22K
@OZ711
SD/MMC
MS
3D3V_S0
3D3V_S0
CR1
XD_CD#21
ODR_VCC
XD_DATA421
SD/MS/XD_DATA321
XD_DATA521
SD/MS/XD_DATA221
C C
SD_CMD/MS_BS/XD_ALE21
B B
SD_CMD/MS_BS/XD_ALE21
XD_DATA621
SD/MS/XD_DATA121
XD_DATA721
SD/MS/XD_DATA021
XD_WPO21
XD_WE#21
XD_R/B21
XD_RE#21
SD/MS_CLK/XD_CLE21
ODR_VCC
SD_WP/XD_WPI21
XD_WPO21
XD_WE#21
SD/MS_CLK/XD_CLE21
XD_RE#21
XD_R/B21
XD_CD#21
40
SM_11P(CD)
41
SM_12P(VCC)
42
SM_10P(GEN)
43
SM_13P(D5)
44
SM_9P(D4)
45
SM_14P(D6)
46
SM_8P(D3)
47
SM_15P(D7)
48
SM_7P(D2)
49
SM_16P(D8)
50
SM_6P(D1)
51
SM_17P(LVD)
52
SM_5P(WP)
53
SM_18P(GND)
54
SM_4P(WE)
55
SM_19P(R/B)
56
SM_3P(ALE)
57
SM_20P(RE)
58
SM_2P(CLE)
59
SM_21P(CE)
60
SM_1P(VSS)
61
SM_22P(VCC)
63
SM_CD
65
SM_GND
66
SM_WP
67
GND
68
GND
69
GND
22
XD_8P(WP#)
24
XD_7P(WP#)
26
XD_6P(ALE)
28
XD_5P(CLE)
30
XD_4P(CE#)
32
XD_3P(RE#)
34
XD_2P(R/B#)
36
XD_1P(CD)
38
XD_1P(GND)
CR7in1 @OZ711
SD_CD
SD_D0
SD_D1
SD_D2
SD_D3/CD
SD_CMD
SD_VCC
SD_WP
SD_CLK
SD_VSS
SD_VSS
SD_GND
MS_BS
MS_INS
MS_SCLK
MS_SDIO
MS_RESERVE
MS_RESERVE
MS_VCC
MS_VCC
MS_VSS
MS_VSS
XD_18P(VCC)
XD_17P(D7)
XD_16P(D6)
XD_15P(D5)
XD_14P(D4)
XD_13P(D3)
XD_12P(D2)
XD_11P(D1)
XD_10P(D0)
XD_9P(GND)
R0402
+/-1%
R0402
+/-1%
SD_CD#
MS_CD#
1
SD/MS/XD_DATA0_R
5
SD/MS/XD_DATA1_R
3
SD/MS/XD_DATA2_R
39
SD/MS/XD_DATA3_R
37
SD_CMD/MS_BS/XD_ALE_R
35
11
62
SD/MS_CLK/XD_CLE_R
9
7
33
64
SD_CMD/MS_BS/XD_ALE_R
15
23
SD/MS_CLK/XD_CLE_R
27
SD/MS/XD_DATA0_R
19
SD/MS/XD_DATA3_R
25
SD/MS/XD_DATA2_R
21
29
17
31
13
2
4
6
8
10
12
14
16
18
20
ODR_VCC
SD_WP/XD_WPI 21
MS_CD# 21
SD/MS/XD_DATA1_R
XD_DATA7 21
XD_DATA6 21
XD_DATA5 21
XD_DATA4 21
SD/MS/XD_DATA3 21
SD/MS/XD_DATA2 21
SD/MS/XD_DATA1 21
SD/MS/XD_DATA0 21
ODR_VCC3#21,43
SD_CD# 21
ODR_VCC
SD/MS_CLK/XD_CLE_R
SD/MS/XD_DATA3_R
SD/MS/XD_DATA2_R
SD/MS/XD_DATA1_R
SD/MS/XD_DATA0_R
SD_CMD/MS_BS/XD_ALE_R
ODR_VCC
R362 33 R 0402 +/-5%
R363 33 R 0402 +/-5%
R364 33 R 0402 +/-5%
R365 33 R 0402 +/-5%
R366 33 R 0402 +/-5%
R367 33 R 0402 +/-5%
A A
TECHNOLOGY COPR.
Title
26_CardReader
Document Numbe r Rev
8
S06 MAINBOARD
of
7
6
5
4
3
Date: Sheet
2
23 45Friday, December 17, 2004
1
A
Page 24
5
hocnghetructuyen.vn
LAN_XTAL1
LAN_XTAL2
D D
C C
3D3V_S0
B B
A A
DTC144EUA
B_ICH_PME#15,22,29
TRDP025
TRDN025
TRDP125
TRDN125
TRDP225
TRDN225
TRDP325
TRDN325
R376 1K
R0603 +/-5%
R377 15K
R0402 +/-5%
INT_PIRQC#15,28
PCIRST1#15,21,28,43
PCLK_LAN3
PCI_GNT#215
PCI_REQ#215
*
BC398 27pF C0603 50V, NPO, +/-5%
X4
XTAL-25MHz
Q12
R0402 +/-5%
@8110SB(L)
R375
R0402 +/-5%
R382 0
R0603 +/-5%
5
*
BC401 27pF C0603 50V, NPO, +/-5%
*
3D3V_LAN_S5
2
13
R372 0
Dummy
AVDDL_3.3V
GND
AVDDL_3.3V
CTRL25
GND
AVDDH
0
HSDAC+
V_12P
GND
AVDDL_3.3V
GND
AVDDL_3.3V
GND
GND
LAN_EN
DVDD_1.8V_2.5V
3D3V_LAN_S5
PME#_LAN
DVDD_1.8V_2.5V
B_PCI_AD31
B_PCI_AD30
GND
B_PCI_AD29
B_PCI_AD28
GND
B_PCI_C/BE#315,21,28,43
B_PCI_AD2315,21,28,43
R370
10K
R0402
+/-5%
PME#_LAN
R373
2.49K
+/-1%
R0603
5.6K@8100C(L)
R598 22
R0402 +/-5%
LAN_RSET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SPEED1000_LED25
LINK_LEDJ25
ACTIVE_LED25
GND
GND
GND
CTRL18
DVDD_A_1.8V_2.5V
U17
MDI0+
MDI0AVDDL
VSS
MDI1+
MDI1AVDDL
CTRL25
VSS
AVDDH
HSDAC+
HSDACVSS
MDI2+
MDI2AVDDL
VSS
MDI3+
MDI3AVDDL
VSSPST
GND
ISOLATEB
VDD18
INTAB
VDD33
RSTB
CLK
GNTB
REQB
PMEB
VDD18
AD31
AD30
GND
AD29
AD28
VSSPST
124
126
127
125
128
LV2
LG2
VSS
RSET
CTRL18
AD2739AD2640VDD3341AD2542AD2443CBE3B44VDD1845IDSEL46AD2347GND48AD2249AD2150VSSPST51GND52AD2053VDD1854AD1955VDD3356AD1857AD1758AD1659CBE2B60FRAMEB61GND62IRDYB63VDD18
B_PCI_AD25
B_PCI_AD27
B_PCI_AD24
B_PCI_AD26
B_PCI_C/BE#3
3D3V_LAN_S5
123
4
R369 3.6K
R0603+/-5%
EECS
EESK
EEDI/AUX
EEDO
only used @8110SB(L)&AT93C56
GND
GND
AVDDH
LAN_XTAL2
LAN_XTAL1
121
122
119
118
120
HV
HG
XTAL1
XTAL2
VSSPST
GND
B_PCI_AD23
B_PCI_AD22
DVDD_1.8V_2.5V
GND
EESK
EEDO
GND
111
3D3V_LAN_S5
DVDD_1.8V_2.5V
110
EESK
B_PCI_AD18
EECS
EEDI/AUX
B_PCI_AD0
B_PCI_AD1
3D3V_LAN_S5
105
109
106
103
104
107
108
AD1
AD0
EEDI
EECS
EEDO
VDD33
VDD18
LWAKE
AD2
VSSPST
GND
VDD18
AD3
AD4
AD5
AD6
VDD33
AD7
CBE0B
VSSPST
AD8
AD9
M66EN
AD10
AD11
AD12
VDD33
AD13
AD14
VSSPST
GND
AD15
VDD18
CBE1B
PAR
SERRB
SMBDATA
GND
SMBCLK
VDD33
PERRB
STOPB
DEVSELB
TRDYB
VSSPST
CLKRUNB
64
GND
B_PCI_AD16
B_PCI_AD17
DVDD_1.8V_2.5V
LINK_LEDJ
ACTIVE_LED
SPEED1000_LED
DVDD_1.8V_2.5V
113
114
115
117
116
112
GND
LED3
LED2
LED1
LED0
VDD18
RTL8110SB(L)-HS
GND
GND
B_PCI_AD20
B_PCI_AD21
B_PCI_AD19
DVDD_1.8V_2.5V
4
U16
1
2
3
4
AT93C46-2.7V
R371 10K
R0402 +/-5%
102
101
100
DVDD_1.8V_2.5V
99
98
97
96
95
3D3V_LAN_S5
94
93
92
91
90
89
88
87
86
85
3D3V_LAN_S5
84
83
82
81
80
79
DVDD_1.8V_2.5V
78
77
76
75
74
73
72
3D3V_LAN_S5
71
70
69
68
67
66
65
B_PCI_IRDY# 15,21,28,43
B_PCI_FRAME# 15,21,28,43
B_PCI_C/BE#2 15,21,28,43
CS
SK
DI
DO
B_PCI_AD2
GND
GND
B_PCI_AD3
B_PCI_AD4
B_PCI_AD5
B_PCI_AD6
B_PCI_AD7
GND
B_PCI_AD8
B_PCI_AD9
B_PCI_AD10
B_PCI_AD11
B_PCI_AD12
B_PCI_AD13
B_PCI_AD14
GND
GND
B_PCI_AD15
GND
GND
3
3D3V_LAN_S5
8
VCC
7
NC
6
ORG
5
GND
B_PCI_C/BE#0 15,21,28,43
B_PCI_C/BE#1 15,21,28,43
B_PCI_PAR 15,21,28,43
B_PCI_SERR# 15,21,28
B_PCI_PERR# 15,21,28
B_PCI_STOP# 15,21,28,43
B_PCI_DEVSEL# 15,21,28,43
B_PCI_T R D Y # 15,21,28,43
B_PM_CLKRUN# 15,21,28,29,30,43
3
GND
3D3V_LAN_S5
3D3V_LAN_S5
BC402
0.1uF
*
16V, Y5V, +80%/-20%
C0402
AVDDL_3.3V
B_PCI_AD[31..0] 15,21,28,43
DVDD_1.8V_2.5V
BC413 0 . 1uF C0402
BC414 0 . 1uF C0402
*
BC415 0 . 1uF C0402
*
BC416 0 . 1uF C0402
*
*
3D3V_LAN_S5
BC419 10uF C0805
BC420 0 . 1uF C0402
*
BC421 0 . 1uF C0402
*
BC422 0 . 1uF C0402
*
BC423 0 . 1uF C0402
*
*
3D3V_LAN_S5
BC424 0 . 1uF C0402
BC425 0 . 1uF C0402
*
BC426 0 . 1uF C0402
*
BC427 0 . 1uF C0402
*
*
DVDD_1.8V_2.5V
BC430 0 . 1uF C0402
BC431 0 . 1uF C0402
*
BC432 0 . 1uF C0402
*
BC433 0 . 1uF C0402
*
*
2
3D3V_S5
CTRL25
3D3V_LAN_S5
@8110S,Dummy default
R596 0
R0805 +/-5%
@8110SB(L)
R597 0
R0805 +/-5%
CTRL18 CTRL25
TX close to Lan Chip
RX close to Transform
Title
Document Numbe r Rev
2
Date: Sheet
3D3V_LAN_S5
Reserved
R368 0
R0805 +/-5%
3D3V_LAN_S5
Maybe Use FB
23
Q11
1
PBSS5350X
6.3V, X5R, +/-10%
@8110SB(L)
BC403
BC404
10uF
*
AVDDL_R
1
DVDD_A_1.8V_2.5V
DVDD_1.8V_2.5V
@8100C(L),FB OPTION@8110SB(L)
0.1uF
*
C0402
C0805
23
Q13
PBSS5350X
@8110SB(L)
BC409
22uF
*
C1206
@8100C(L),FB OPTION@8110SB(L)
R374 0
R0805
BC417 10nF
C0603
*
25V, Y5V, +80%/-20%
BC428 10nF
C0603
*
25V, Y5V, +80%/-20%
@8110SB(L)
LAN_RTL8110S/8100C
S06 MAINBOARD
R0805 +/-5%
3D3V_LAN_S5
R609
0 R0805
+/-5%
@8100C(L)
BC405
0.1uF
*
C0402
BC410
0.1uF
*
C0402
R610 0
R0805 +/-5%
V_12P
+/-5%
R378
49.9
+/-1%
R0402
TRD_UL1
R383
49.9
+/-1%@8110SB(L)
R0402
TRD_UL3
1
Maybe Use FB
R608 0
@8110SB(L)
BC406
0.1uF
*
C0402
3D3V_LAN_S5
EC
Q14
B
PBSS5140T
@8100C(L)
R611 0
R0805 +/-5%
@8110SB(L)
TRDP0
TRDN0
TRDP1
TRDN1
R379
R380
49.9
49.9
+/-1%
+/-1%
R0402
R0402
TRD_UL2
BC418
TRDP2
TRDN2
TRDP3
TRDN3
R385
R384
49.9
49.9
+/-1%
+/-1%
R0402
R0402
@8110SB(L)
@8110SB(L)
TRD_UL4
1
AVDDH
BC400
BC399
0.1uF
0.1uF
*
*
AVDDL_3.3V
DVDD_A_1.8V_2.5V
DVDD_1.8V_2.5V
25V, Y5V, +80%/-20%
BC429
25V, Y5V, +80%/-20%
C0402
BC408
0.1uF
*
C0402
AVDDH
*
R381
49.9
+/-1%
R0402
10nF
C0603
*
R386
49.9
+/-1%
R0402
@8110SB(L)
10nF
C0603
*
@8110SB(L)
C0402
BC412
0.1uF
C0402
TECHNOLOGY COPR.
of
24 45Friday, December 17, 2004
A
Page 25
5
hocnghetructuyen.vn
For Modem Cable from MDC
R388 0 R0603+/-5%
J1
NC
2
D D
4
NC
3
Header_1X2
1
Maybe Use FB
R390 0
R0603
+/-5%
TIP_RJ11
RING_RJ11
Co-Layout with L52
C C
4
BC436
1.5nF
*
2kV, X7R, +/-10%
C1808
1.route on bottom as differential pairs.
3
MX0+
MX0MX1+
MX1-
TIP_RJ11
RING_RJ11
BC437
1.5nF
*
2kV, X7R, +/-10%
C1808
MX2+
MX2-
MX3+
MX3-
RJ45RJ11CN1
1
TX+/0+
2
TX-/0-
3
RX+/1+
4
NC1/2+
5
NC2/2-
6
RX-/1-
7
NC/3+
8
NC4/3-
9
TIP
10
RING
RJ45_RJ11
GREEN
A3A1-
AMBER
YELLOW
B3- B1+
A2+
GND1
GND2
A2+
B1+
A3-
A1-
B3-
13
3D3V_LAN_S5_A
12
11
14
15
B2
16
17
18
2
3D3V_LAN_S5
3D3V_LAN_S5_B
R387
29.4
+/-1%
R0603
Dummy
*
*
*
*
Note: NOT Need Lan LED
R389 330
Dummy
R0603 +/-5%
Dummy
R391 330
R0603 +/-5%
Dummy
3D3V_LAN_S5
ACTIVE_LED 24
BC434
1nF
50V, X7R, +/-10%
C0402
Dummy
BC435
1nF
50V, X7R, +/-10%
C0402
Dummy
R392 330
R0603 +/-5%
BC438
1nF
50V, X7R, +/-10%
C0402
Dummy
BC439
1nF
50V, X7R, +/-10%
C0402
Dummy
1
LINK_LEDJ 24
SPEED1000_LED 24
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be eq ual lengths.
5.6mil trace width,12mil separation.
BC440
0.1uF
*
C0402
16V, Y5V, +80%/-20%
BC441
10nF
*
C0402
25V, X7R, +/-10%
BC443
1.5nF
*
C1808
2kV, X7R, +/-10%
Dummy
B B
3D3V_LAN_S5
BC442
0.1uF
*
C0402
16V, Y5V, +80%/-20%
*
BC679
10nF
C0402
@8110SB(L)
*
BC680
10nF
C0402
10nF@8110SB(L),0.1uF@8100C(L)
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.
TF_V_DAC
MDI2+
MDI2-
TF_V_DAC
MDI3+
MDI3-
TF_V_DAC
MDI1+
MDI1-
TF_V_DAC
MDI0+
MDI0-
*
BC445
10nF
C0402
@8110SB(L)
BC446
10nF
*
25V, X7R, +/-10%
C0402
@8110SB(L)
TRDP224
TRDN224
TRDP324
TRDN324
TRDP124
TRDN124
TRDP024
TRDN024
L18
1
2
3
4
5
6
7
8
9
10
11
12
TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-
XFMR 350uH
MCT1
MX1+
MX1-
MCT2
MX2+
MX2-
MCT3
MX3+
MX3-
MCT4
MX4+
MX4-
24
MX2+
23
MX2-
22
21
MX3+
20
MX3-
19
18
MX1+
17
MX1-
16
15
MX0+
14
MX0-
13
H5062@8110S(B),H1285@8100C(L)
@8110SB(L)
@8110SB(L)
R39375 R0402+/-5%
R39475 R0402+/-5%
R39575 R0402+/-5%
R39675 R0402+/-5%
BC444
1.5nF
*
2kV, X7R, +/-10%
C1808
AVDDL_3.3V
A A
TF_V_DAC
R397 0
R0402
+/-5%
@8110SB(L)
TECHNOLOGY COPR.
Title
RJ45/RJ11 & Transformer
Document Numbe r Rev
5
S06 MAINBOARD
of
4
3
2
Date: Sheet
25 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 26
5
hocnghetructuyen.vn
4
3
2
1
FAE suggest
Layout close to Pin6
*Layout*
BC450
C0402
1uF
5V_S0
12
*
AUD_AGND
PCI_SPKR21,43
ICH_SPKR15
KBC_SPKR29
MIC_IN_A27
CD_AUDR19
CD_GND19
CD_AUDL19
D D
10V, Y5V, +80%/-20%
C C
B B
40 mil
U19
1
SHDN#
2
GND
3
IN
MAX8863
FB8
2 1
Dummy
FB L0603 180 Ohm
DUMMY
*
BC629 22pF
C0402
50V, NPO, +/-5%
Dummy
*
BC630 22pF
C0402
50V, NPO, +/-5%
Dummy
Dummy
BC689 0.47uF
C0603
*
16V, Y5V, +80%/-20%
BC690 0.47uF
C0603
*
16V, Y5V, +80%/-20%
BC691 0.47uF
C0603
*
16V, Y5V, +80%/-20%
CD_AUDR
CD_GND
CD_AUDL CSD_CD_L_2
SET
OUT
12
X7
X-24D576MHz
R618 47K
R0402 +/-5%
R0402 +/-5%
R0402 +/-5%
R413 0
Dummy
R0603 +/-5%
R414 0
Dummy
R0603 +/-5%
Dummy
R0603 +/-5%
50V, NPO, +/-5%
5
4
10V, Y5V, +80%/-20%
AC_CLK3
R619
R620
BC448
22pF
*
C0402
5VA_AUD_S0
BC45110uF
BC4520.1uF
*
*
C0402
C0805
10V, Y5V, +80%/-20%
ACZ_SDATAOUT14,20
ACZ_SDATAIN014
47K
R621
47K
22K
+/-1%
R0402
AUD_AGND
5VA_AUD_S0
R400
28.7K
+/-1%
R0603
R403
10K
+/-5%
R0402
3D3V_S0
BC453
10uF
*
*
C0805
R516 0
R0603 +/-5%
AC97_BTCLK
R406 47
R0402 +/-5%
ACZ_SYNC14,20
ACZ_RST#14,20
MDM_AUD_OUT20
*Layout*
20 mil
Low for external CLK
NC for internal CLK
5VA_AUD_S0
R405
0
Reserved,Dummy@Crystal
+/-5%
R0603
AUD_AGND
BC454
0.1uF
16V, Y5V, +80%/-20%
C0402
1
DVDD1
X1_AUDIO
2
XTL-IN
X2_AUDIO
3
XTL-OUT
4
DVSS1
5
SDATA-OUT
6
BIT-CLK
7
AC97_SDIN AFLT1
C39
BEEP
CSD_CD_R_2
CSD_GND_2
1uF
10V, Y5V, +80%/-20%
1 2
C0402
*
BC475
*
0.1uF C0402
16V, Y5V, +80%/-20%
BC476
0.1uF
*
16V, Y5V, +80%/-20%
C0402
Dummy
AUD_AGND
BC478 1uF
C0603 10V, Y5V, +80%/-20%
BC479 1uF
C0603 10V, Y5V, +80%/-20%
BC480 1uF
C0603 10V, Y5V, +80%/-20%
BC481 1uF
C0603 10V, Y5V, +80%/-20%
DVSS2
8
SDATA-IN
9
DVDD2
10
SYNC
11
RESET#
12
PC-BEEP
PHONE
Dummy
*
Dummy
*
Dummy
*
DummyR415 0
*
46
45
44
47
48
SPDIFO
SPDIFI/EAPD
PHONE13AUX-L14AUX-R15JD2/VIDEO-L16JD1/VIDEO-R17CD-L18CD-GND19CD-R20MIC121MIC222LINE-IN-L23LINE-IN-R
MIC1_1
CSD_CD_R_1
CSD_GND_1
CSD_CD_L_1
43
LFE-OUT
CEN-OUT
JD0/GPIO0
XTLSEL/ID1#
42
AVSS2
39
41
SURR-OUT-R/HP-OUT-R
40
38
NC
FRONT-OUT-R
FRONT-OUT-L
SURR-OUT-L/HP-OUT-L
FRONT-MIC2/VRDA
37
AVDD2
MONO-O
FRONT-MIC1
VREFOUT2
VRDA/VRAD
AFILT2
AFILT1
VREFOUT
AVSS1
AVDD1
24
MIC2_1
VREF
C0603
U20
ALC655
BC477
If use this circuit,R621 change to 1K
36
35
34
33
32
VRDA
31
AFLT2
30
29
28
27
26
25
*
AUD_AGND
1uF
*
10V, Y5V, +80%/-20%
Dummy
AC97_BTCLK
MDM_AUD_IN 20
5VA_AUD_S0
BC620
10uF
BC468
*
0.1uF
C0805
C0402
MIC2 27
3D3V_S03D3V_S0
BC455
1nF
50V, X7R, +/-10%
*
C0402
AUD_AGNDAUD_AGND
BC462 1uF
C0603 10V, Y5V, +80%/-20%
*
BC463 1nF
C0402 50V, X7R, +/-10%
*
BC464 1nF
C0402 50V, X7R, +/-10%
*
ALC100_VREF
BC470
10uF
BC471
*
*
0.1uF
C0805
C0402
10V, Y5V, +80%/-20%
BC456
1nF
*
50V, X7R, +/-10%
C0402
ALC100_VREF
R50912.1R0402+/-1%
R51012.1R0402+/-1%
SOUND_R
SOUND_L
*
AUD_REF
ACZ_BITCLK 14
ACZ_BTCLK_MDC 20
SOUND_R 27
SOUND_L 27
BC472
BC678
10uF
*
0.1uF
C0805
C0402
AUD_AGND
AUD_REF
AUD_AGND
1 2
JUMPER1
SHORT1
A A
ICH_SPKR15
KBC_SPKR29
5
4
53
1
2
U29
NC7SZ86Dummy
3
NORMAL:LOWNORMAL:LOW
PCI_SPKR21,43
4
53
1
2
U28
NC7SZ86Dummy
R537 10K
4
R0402 +/-5%
Dummy
BEEP
2
BC621
*
0.1uF
C0402
Dummy
AUD_AGND
Title
TECHNOLOGY COPR.
AUDIO_AC97_ALU655-U
Document Number Rev
S06 MAINBOARD
Date: Sheet
1
of
26 45Thursday, December 16, 2004
A
Page 27
R0402
hocnghetructuyen.vn
R0402
45k15.6 dB
25k21.6 dB
MUTE_EN29
5
+/-5% Dummy
+/-5%
R425
1K
+/-5%
R0402
Dummy
AUD_AGND AUD_AGND
SOUND_L
SOUND_R
BC622 0.47uF
C0603 16V, Y5V, +80%/-20%
BC623 0.47uF
C0603 16V, Y5V, +80%/-20%
5V_OP_S0
GAIN0
GAIN1
R426
1K
+/-5%
R0402
*
*
BC499
10uF
*
C0805
10V, Y5V, +80%/-20%
R433 100K
R0402 +/-5%
2
3
LIN- SOUND_R
RIN-
5V_OP_S0
BC500
*
0.1uF
C0402
AUD_AGNDAUD_AGND
1 3
DTC144EUA
Q15
BYPASS
SHUTDOWNJ
AUD_AGND
15
16
12
10
19
20
13
11
5V_OP_S0
R422 100K
R423 100K
GAIN0 GAIN1 AV(inv) INPUT IMPEDANCE
01
00
00
6 dB00 90k
10 dB 70k
SOUND_L26
SOUND_R26
D D
C C
B B
21
U21
6
PVDD
PVDD
VDD
NC
BYPASS
SHUTDOWN
GND
GND
GND
1
GND
TPA6017A2
D31
BAV99
Dummy
SOUND_L
AUD_AGND
4
21
3
TC10 100uF
TC11 100uF
Place it as close as AMP
18
ROUT+
14
ROUT-
4
LOUT+
8
LOUT-
7
RIN+
17
RIN-
9
LIN+
5
LIN-
2
GAIN0
3
GAIN1
thermal_pad
21
D32
BAV99
Dummy
21
cesdh5516V, +/-20%
*
21
cesdh5516V, +/-20%
*
AUD_AGND
SPKR_R+
SPKR_RSPKR_L+
SPKR_L-
RIN+
RIN-
LIN+
LIN-
GAIN0
GAIN1
3D3V_S0
21
3
SPKR_L+2
R447
R448
22K
22K
+/-1%
+/-1%
R0402
R0402
AUD_AGND
BC504 0.47uF
C0603 1 6V, Y5V, +80%/-20%
*
BC505 0.47uF
C0603 1 6V, Y5V, +80%/-20%
*
BYPASS
*
AUD_AGND
BC491
0.47uF
C0603
16V, Y5V, +80%/-20%
D33
BAV99
Dummy
SPKR_R+SPKR_L- SP KR_R-SPKR_L+
3
R439 22
R0402 +/-5%
R443 22
R0402 +/-5%
AUD_AGND
3
21
D34
BAV99
Dummy
SPKR_L_1 SPKR_L_2
SPKR_R_1SPKR_R+2
50V, X7R, +/-10%
*
AUD_AGND
SPKR_L+
SPKR_LSPKR_RSPKR_R+
BC508
680pF
C0402
50V, X7R, +/-10%
BC509
680pF
*
C0402
AUD_AGND
BC4941nF C0402 50V , X7 R , + / -10%
*
BC4951nF C0402 50V , X7 R , + / -10%
*
BC4961nF C0402 50V , X7 R , + / -10%
*
BC4981nF C0402 50V , X7 R , + / -10%
*
SPKR_L+
SPKR_LSPKR_RSPKR_R+
J4
1
2
3
4
HS82040
SPKR_R_2
6
5
AUD_AGND
5V_S0
MIC226
2
R424
0
R0805
+/-5%
AUD_REF
5V_OP_S0
BC492
4.7uF
*
10V, Y5V, +80%/-20%
C0805
AUD_AGND
R429
4.7K
+/-5%
R0402
R432
22K
+/-1%
R0402
R430
0 R0603
+/-5%
50V, X7R, +/-10%
1
Internal MIC
INT_MIC_R
16V, Y5V, +80%/-20%
BC617
0.1uF
*
C0402
J3
123
NC
NC
Header_1X2
4
MIC-In
AUD_AGND_S
EXT_MIC_IN
BC502
680pF
*
C0402
INT_MIC
50V, X7R, +/-10%
*
BC503
680pF
C0402
AUD_AGND AUD_AGND_SAUD_AGND AUD_AGND
MIC_JK1
5
4
3
6
2
1
MIC-IN
G
2N7002EPT
5V_OP_S0
Q17
AUD_AGND
R435
100K
+/-5%
R0402
DS
R436
100K
+/-5%
R0402
G
BC507
0.1uF
*
C0402
16V, Y5V, +80%/-20%
AUD_AGND AUD_AGND_S
SHORT6
1 2
AUD_AGND_S AUD_AGND
JUMPER1
2
SPKR_L_2
SPKR_R_2
Line-Out
Title
Document Number Rev
Date: Sheet
AUDIO_AMP
S06 MAINBOARD
LINEOUT_JK1
5
4
3
6
2
1
JACK_AUDX1 Reverse
TECHNOLOGY COPR.
1
A
of
27 45Thursday, December 16, 2004
AUD_REF
INT_MIC_R
R604 22
R0402 +/-5%
AUD_REF
A A
MIC_IN_A26
5
R528
4.7K
+/-5%
R0402
R529
22KR0402
+/-1%
AUD_AGND
AUD_AGND
BC618 1uF
C0603
10V, Y5V, +80%/-20%
R530
+/-5%
4.7KR0402
R531
+/-1%
22K R0402
*
FB7
21
FB L0603 300 Ohm
INT_MICINT_MIC_1
*
AUD_AGND
AUD_AGND
BC619
220pF
25V, NPO, +/-5%
C0402
EXT_MIC_IN
4
SHORT2
1 2
JUMPER1
SHORT3
1 2
JUMPER1
SHORT4
1 2
JUMPER1
SHORT5
1 2
JUMPER1
3
SHUTDOWNJ
Q16
2N7002EPT
DS
AUD_AGND
Page 28
5
hocnghetructuyen.vn
B_PCI_AD[31..0]15,21,24,43
4
3
2
1
D D
RF_KILL#29
C C
B B
3D3V_S0
BC483
0.1uF
*
C0402
Dummy
BC484
0.1uF
*
C0402
Dummy
*
BC485
0.1uF
C0402
Dummy
R419
10K
+/-5%
R0402
*
PCLK_MINI3
BC486
0.1uF
C0402
Dummy
*
BC487
0.1uF
*
C0402
Dummy
R420
33
+/-5%
R0402
Dummy
BC482
33pF
50V, NPO, +/-5%
C0603
Dummy
802.11_ACT13
3D3V_S0
PCI_REQ#115
B_PCI_C/BE#315,21,24,43
B_PCI_C/BE#215,21,24,43
B_PCI_IRDY#15,21,24,43
B_PM_CLKRUN#15,21, 24, 29, 30, 43
B_PCI_SERR#15,21,24
B_PCI_PERR#15,21,24
B_PCI_C/BE#115,21,24,43
5V_S0
BC488
0.1uF
*
C0402
Dummy
BC489
4.7uF
*
10V, Y5V, +80%/-20%
C0805
Dummy
INT_PIRQC#
1
TP83
B_PCI_AD31
B_PCI_AD29
B_PCI_AD27
B_PCI_AD23
B_PCI_AD21
B_PCI_AD17
B_PCI_C/BE#2 B_PCI_AD16
B_PM_CLKRUN#
B_PCI_C/BE#1
B_PCI_AD14
B_PCI_AD10
B_PCI_AD8
B_PCI_AD7
B_PCI_AD1
MINI1
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
1
3
5
7
9
128 127
125
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
Mini-PCI
PIN 3-16 : LAN RESERVE
B_PCI_AD30
B_PCI_AD28B_PCI_AD25
B_PCI_AD26
B_PCI_AD24B_PCI_C/BE#3
MOD_IDSEL
B_PCI_AD22
B_PCI_AD20B_PCI_AD19
B_PCI_AD18
B_PCI_AD15
B_PCI_AD13
B_PCI_AD11B_PCI_AD12
B_PCI_AD9
B_PCI_C/BE#0
B_PCI_AD6
B_PCI_AD4B_PCI_AD5
B_PCI_AD2
B_PCI_AD0B_PCI_AD3
R421 10
R0402 +/-5%
802.11_LINK 13
5V_S0
INT_PIRQC# 15,24
PCIRST1# 15,21,24,43
3D3V_S0
PCI_GNT#1 15
CBUS_PME# 21,22,43
B_PCI_AD21
B_PCI_PAR 15,21,24,43
B_PCI_FRAME# 15,21,24,43
B_PCI_T R D Y # 15,21,24,43
B_PCI_STOP# 15,21,24,43
B_PCI_DEVSEL# 15,21,24,43
B_PCI_C/BE#0 15 , 21, 24, 43
INT_SERIRQ 15,21,29,30,43
5V_S0
A A
BC490
4.7uF
*
10V, Y5V, +80%/-20%
C0805
Dummy
5
Title
TECHNOLOGY COPR.
MINI-PCI
Document Numbe r Rev
S06 MAINBOARD
of
4
3
2
Date: Sheet
28 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 29
5
hocnghetructuyen.vn
D D
INT_SERIRQ15,21,28,30,43
B_LPC_LFRAME#14,30
B_LPC_LAD014,30
B_LPC_LAD114,30
B_LPC_LAD214,30
B_LPC_LAD314,30
PCLK_KBC GPIO20
R457
33
+/-5%
R0402
BC516
Dummy
50V, NPO, +/-5%
33pF
*
C0603
Dummy
C C
3D3V_S5
5V_S0
B B
BAT_TH35
Pull-Down resistor required
to avoid leakage current
3D3V_AUX_S5
R463
10K
+/-5%
R0402
COVERUP
TP92
1
TP93
1
TP94
1
TP95
1
R0402
R473 1K
R475
15K
+/-5%
R0402
PCLK_KBC3
PLT_RST1#7,15,17,30,42
B_ICH_PME#15,22,24
R467
10K
+/-5%
R0402
BAT_TYPE
D35
CH501H-40
EX_BL_ON42
GMCH_BL_ON7
R462 47K
R0402 +/-5%
POWER-ON RESET
Example Only
R466
10K
+/-5%
R0402
+/-5%
BC518
0.1uF
*
16V, Y5V, +80%/-20%
C0402
R468
10K
+/-5%
R0402
21
R469
10K
+/-5%
R0402
ECRST#
R465
0
R0603
+/-5%
Dummy
PSCLK1
PSDAT1
PSCLK2
PSDAT2
BTSENSE35
R471 0
R0402 +/-5%
R472 0
R0402 +/-5%
User Programing Button
A A
BTN1
2
4
5
GND
Tactile Switch
1
3
5
KROW1
KCOL17
R458
10K
+/-5%
R0402
BC517
0.1uF
*
25V, Y5V, +80%/-20%
C0603
3D3V_AUX_S5
SMC_WAKE_SCI#_R15
@PM
@GM
CHARON#/OFF35
4
R464
10K
+/-5%
R0402
TP91
MXM_PGD42
RTC_SENSE#14
MDC_RINGJ20
4
BC513
0.1uF
16V, Y5V, +80%/-20%
C0402
B_PM_CLKRUN#15,21,24,28,30,43
PM_SUS_STAT#15
H_RCIN#14
H_A20GATE14
SMC_RUNTIME_SCI#15
1
AC_IN35
COVERUP13
EC_PWRBTN#41
TP96
IOUT35
KBC_MATRIX132
KBC_MATRIX032
1D5V_S5PGD37
S0_EN17,20,36,37,38,40,42
S3_EN38
PM_SLP_S3#_ICH15
PM_SLP_S4#_ICH15
S0_EN_D37
S5_EN18,37,41
RF_KILL#28
EC_BLON13
AC_BAT#42
AD_OFF40
KROW132
KROW232
KROW332
KROW432
KROW532
KROW632
KROW732
KROW832
KCOL132
KCOL232
KCOL332
KCOL432
KCOL532
KCOL632
KCOL732
KCOL832
KCOL932
KCOL1032
KCOL1132
KCOL1232
KCOL1332
KCOL1432
KCOL1532
KCOL1632
TP89
TP90
TCLK32
TDATA32
TP100
TP102
TP103
3D3V_AUX_S5
*
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8
KCOL17
1
KCOL18
1
BAT_IN2#
BAT_TYPE
BT_IN#
1
BL_ONF_NB_VGA
MP3PWR_ON#
1
MP3BT_ON#
1
AC_BAT_R
1
R476
10K
+/-5%
R0402
BL#2
U23
161
VCCBAT
17
GND
35
GND
46
GND
122
GND
137
GND
167
GND
159
BATGND
7
SERIRQ
9
LFRAME#
15
LAD0
14
LAD1
13
LAD2
10
LAD3
18
LCLK
25
CLKRUN#/GPIO0C
24
GPIO0B
165
LRST#/GPIO2C
6
KBRST#/GPIO03
5
GA20/GPIO02
31
ECSCI#
19
ECRST#
71
KSI0/GPIK0
72
KSI1/GPIK1
73
KSI2/GPIK2
74
KSI3/GPIK3
77
KSI4/GPIK4
78
KSI5/GPIK5
79
KSI6/GPIK6
80
KSI7/GPIK7
49
KSO0/GPOK0
50
KSO1/GPOK1
51
KSO2/GPOK2
52
KSO3/GPOK3
53
KSO4/GPOK4
56
KSO5/GPOK5
57
KSO6/GPOK6
58
KSO7/GPOK7
59
KSO8/GPOK8
60
KSO9/GPOK9
61
KSO10/GPOK10
64
KSO11/GPOK11
65
KSO12/GPOK12
66
KSO13/GPOK13
67
KSO14/GPOK14
68
KSO15/GPOK15
153
KSO16/GPOK16
154
KSO17/GPOK17
2
GPWU0
26
GPWU1
29
GPWU2
30
GPWU3
44
GPWU4
76
GPWU5
172
GPWU6/TIN1
176
GPWU7/TIN2/FANFB2
110
PSCLK1
111
PSDAT1
114
PSCLK2
115
PSDAT2
116
PSCLK3
117
PSDAT3
81
AD0/GPIAD0
82
AD1/GPIAD1
83
AD2/GPIAD2
84
AD3/GPIAD3
87
AD4/GPIAD4
88
AD5/GPIAD5
89
AD6/GPIAD6
90
AD7/GPIAD7
28
GPIO0E
27
GPIO0D
175
TOUT2/GPIO2F
8
GPIO04
11
GPIO05/FAN3PWM
12
GPIO06/FANFB3
20
GPIO07
21
GPIO08
22
GPIO09
48
GPIO10
62
GPIO13
63
GPIO14
69
GPIO15
70
GPIO16
75
GPIO17
109
GPIO24
118
GPIO25
119
GPIO26
148
GPIO27
149
GPIO28
155
GPIO29
156
GPIO2A
162
GPIO2B
168
GPIO2D
KB3910
3
Power
Power
XIO8CS#/GPIO18
XIO9CS#/GPIO19
XIOACS#/GPIO1A
XIOBCS#/GPIO1B
XIOCCS#/GPIO1C
XIODCS#/GPIO1D
XIOECS#/GPIO1E
XIOFCS#/GPIO1F
Expanded I/O
LPC Interface
X-BUS Interface
Internal KeyBoard
SMbus
GPW
PS2
GPIO
PWM0/GPOW0
PWM1/GPOW1
PWM2/GPOW2/FAN1PWM
PWM3/GPOW3
PWM4/GPOW4
PWM5/GPOW5
PWD
PWM6/GPOW6
PWM7/GPOW7/FAN2PWM
FANFB1/TOUT1/GPIO2E
CAPLOCK#/GPIO11
FNLOCK#/GPIO12
SCROLLLOCK#/GPIO0F
A to D
NUMLOCK#/GPIO0A
DA0/GPODA0
DA1/GPODA1
DA2/GPODA2
DA3/GPODA3
DA4/GPODA4
DA5/GPODA5
DA6/GPODA6
D to A
DA7/GPODA7
E51IT0/GPIO00
E51IT1/GPIO01
E51RXD/GPIO21/ISPCLK
Debug
E51TXD/GPIO22/ISPDAT
E51CS#/GPIO20/ISPEN_TP
Clock
3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
AGND
A20/GPIO23
RD#
WR#
IOCS#
MEMCS#
SCL1
SDA1
SCL2
SDA2
XCLKO
XCLKI
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
16
34
45
123
136
157
166
95
96
85
86
CHG_LED2#
91
EMAIL_LED#
92
PWR_LED#
93
BT_LED#
94
INTERNET_LED#
97
98
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
108
138
139
140
141
144
145
146
147
150
151
152
173
163
164
169
170
32
33
36
37
38
39
40
43
171
54
55
41
23
99
100
101
102
1
42
47
174
3
4
106
107
GPIO20
105
160
158
3D3V_AUX_S5
BC514
1uF
*
10V, Y5V, +80%/-20%
C0603
A0/ENV0
A1/ENV1
A2/BADDR0
A3/BADDR1
A4/TRIS
A5/SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7
KBCBIOS_FRD#
KBCBIOS_FWR#
KBCBIOS_MEMCS#
B_KBC_SCL1 18,42
B_KBC_DAT1 18,42
BAT_KBC_SCL1 35
BAT_KBC_DAT1 35
BRIGHTNESS_PWM 13
KBC_SPKR 26
R470
100K
+/-5%
R0402
CAPS# 13
NUM# 13
VSET 35
ISET 35
CELLS 35
1
1
1
X1_KBC
X2_KBC
BC519
10pF
C0402
50V, NPO, +/-5%
*
CHG_LED# 13
CHG_LED2# 13
1
TP85
PWR_LED# 13
1
TP86
1
TP87
KBCBIOS_IOCS#
TP98
For External Debug
TP99
TP101
4 1
*
BC515
0.1uF
10V, X7R, +/-10%
C0402
G9
1 2
Close-Power-Gap-3050
PWRBTN#_ICH 15
MUTE_EN 27
X6
XTAL-32.768kHz
23
2
L19
21
FB L0805 100 Ohm
*
1
TP88
BC520
*
10pF
C0402
50V, NPO, +/-5%
2
TC12
10uF
10V, Y5V, +80%/-20%
C0805
3D3V_AUX_S5
KBC_D3
KBC_D2
KBC_D1
KBC_D0
KBC_D7
KBC_D6
KBC_D5
KBC_D4
3D3V_AUX_S5
1
HW STRAP OPTION
R454
47K
+/-5%
R0402
A4/TRIS
A4 A5 GPIO20
S0_EN
R459
4.7K
+/-5%
R0402
R455
47K
+/-5%
R0402
A5/SHBM
S3_EN A1 /ENV1
R460
4.7K
+/-5%
R0402
R456
47K
+/-5%
R0402
R461
4.7K
+/-5%
R0402
GPIO05 GPIO06 A1
3D3V_AUX_S5
RN61 4.7K
1
2
*
3
4
5
6
7 8
Dummy
*
8P4R0603+/-5%
RN62 4.7K
1
2
*
3
4
5
6
7 8
8P4R0603+/-5%Dummy
C30
0.1uF
16V, Y5V, +80%/-20%
C0402
A0/ENV0
A1/ENV1
A2/BADDR0
A3/BADDR1 KBC_D4
A4/TRIS
A5/SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
KBCBIOS_MEMCS#
KBCBIOS_FRD#
A18
KBCBIOS_FWR#
Title
KBC_ENE3910
Document Number Rev
S06 MAINBOARD
Date: Sheet
512KB Flash
U25
32
VCC
12
A0
11
A1
10
A2
9
A3
8
A4
7
A5
6
A6
5
A7
27
A8
26
A9
23
A10
25
A11
4
A12
28
A13
29
A14
3
A15
2
A16
30
A17
22
CE
24
OE
1
VPP
31
PGM
16
GND
PLCC-32-SKT
O0
O1
O2
O3
O4
O5
O6
O7
KBC_D0
13
KBC_D1
14
KBC_D2
15
KBC_D3
17
18
KBC_D5
19
KBC_D6
20
KBC_D7
21
1
SST39VF040
U34
TECHNOLOGY COPR.
of
29 45Friday, Decemb er 17 , 2004
A
Page 30
5
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4
3
2
1
*
10
VCOREF
3D3V_S0
16V, Y5V, +80%/-20%
8
VDD224VDD2
LDRQ#/XOR_OUT
LPCPD#/GPIO21
CLKRUN#/GPIO22
VSS334VSS223VSS1
9
VDD1
BC521
0.1uF
C0402
@87381
35
LRESET#
LFRAME#
U24
LAD0
LAD1
LAD2
LAD3
LCLK
SERIRQ
CLKIN
GPIO0
GPIO01
GPIO2
GPIO3
GPIO4
GPIO20
GPIO24
GPIO23
PC87381
@87381
16V, Y5V, +80%/-20%
*
32
36
38
40
25
27
30
16
21
19
28
43
11
12
13
14
15
17
20
22
BC522
0.1uF
C0402
@87381
*
16V, Y5V, +80%/-20%
BC523
0.1uF
C0402
@87381
LPCPD#
SIO_14M
16V, Y5V, +80%/-20%
*
3D3V_S0
R477
100K
+/-5%
R0402
@87381
LPCPD#
B_LPC_LAD0 14,29
B_LPC_LAD1 14,29
B_LPC_LAD2 14,29
B_LPC_LAD3 14,29
PLT_RST1# 7,15,17,29,42
B_LPC_LFRAME# 14,29
LPC_LDRQ0# 14
B_PM_CLKRUN# 15,21,24,28,29,43
INT_SERIRQ 15,21,28,29,43
SIO_14M 3
R484
33
+/-5%
R0402
Dummy
BC528
*
33pF
50V, NPO, +/-5%
C0603
Dummy
R480
33
+/-5%
R0402
Dummy
BC525
*
33pF
50V, NPO, +/-5%
C0603
Dummy
PCLK_SIO 3
D D
BC524
0.1uF
C0402
@87381
DCD1J31
DSR1J31
SIN131
IRRX1
RTS1J31
SOUT131
CTS1J31
DTR1J31
RI1J31
IRRX2FIRSL0
R478 3.3
R0603 +/-5%
@87381
3D3V_S0
C C
IR1
TFDU6102
@87381
VCC2/IRED_ANODE
R479 3.3
R0603 +/-5%
@87381
IRED_CATHODE
TXD
RXD
VCC1
MODE
GND
3D3V_S0
BC526
10uF
*
C0805
@87381
R481
100K
+/-5%
+/-5%
R0402
@87381
10R0402
BC527
0.1uF
C0402
@87381
3D3V_FIR_S0
IRTX
R483
R482
10K
@87381
+/-5%
R0402
@87381
16V, Y5V, +80%/-20%
*
1
2
3
4
5
SD
6
7
8
44
DCD1#
45
DSR1#
46
SIN1
47
RTS1#
48
SOUT1
1
CTS1#
2
DTR1#_BOUT1
3
RI1#
4
NC
6
IRTX
5
IRRX1
7
IRRX2_IRSL0
29
NC
42
NC
41
NC
39
NC
37
NC
18
NC
33
NC
31
NC
26
NC
B B
A A
10V, Y5V, +80%/-20%
TECHNOLOGY COPR.
Title
SIO_FIR NS87381
Document Numbe r Rev
5
S06 MAINBOARD
of
4
3
2
Date: Sheet
30 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 31
5
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D D
4
3
2
1
SERIAL PORT1
3D3V_S0
BC529
C0603
1uF
10V, Y5V, +80%/-20%
*
@87381
16V, Y5V, +80%/-20%
*
BC530 0 . 1uF
C0402
DCD1J30
C C
@87381
BC531 1uF
C0603 10V, Y5V, +80%/-20%
BC532 1uF
C0603 10V, Y5V, +80%/-20%
@87381
DSR1J30
SIN130
RTS1J30
SOUT130
CTS1J30
DTR1J30
*
RI1J30
*
@87381
U14
11
VCC
19
R5OUT
26
R3OUT
22
R4OUT
7
T1IN
20
T3IN
5
R2OUT
6
T2IN
8
R1OUT
12
C1+
14
C1-
16
15
10
C2C2+
GND
SHDN/SHDN
@87381
R5IN
R3IN
R4IN
T1OUT
T3OUT
R2IN
T2OUT
R1IN
ADM560
T4IN
T4OUT
EN/EN
ADM560JRS
13
V+
18
27
23
2
1
4
3
9
21
28
25
24
17
V-
*
NDCDA
NDSRA
NSINA
NRTSA
NSOUTA
NCTSA
NDTRA
NRIA
ADM_SHDN
ADM_EN
BC533
1uF
C0603
10V, Y5V, +80%/-20%
@87381
3D3V_S0
@87381
@87381
@87381
@87381
C38 150pF
C31 150pF
*
C34 150pF
C32 150pF
C33 150pF
*
*
*
C37 150pF
C36 150pF
C35 150pF
*
*
*
*
@87381
@87381
@87381
@87381
11
10
1
6
2
7
3
8
4
9
5
CN9
RS232-9
@87381
R489
1K
+/-5%
ADM_SHDN
B B
A A
ADM_EN
R0402
@87381
R491
1K
+/-5%
R0402
Dummy
R490
1K
+/-5%
R0402
@87381
R492
1K
+/-5%
R0402
Dummy
ADM560 R489 R490 Reserved; R491 R492 Dummy
ADM561 R491 R492 Reserved; R489 R490 Dummy
TECHNOLOGY COPR.
Title
FWH&DEBUG&COM
Document Numbe r Rev
5
S06 MAINBOARD
of
4
3
2
Date: Sheet
31 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 32
5
hocnghetructuyen.vn
4
3
2
1
D D
Internal KeyBoard Connector
2930
KB1
KROW829
KROW729
TouchPad Strap
PIN Number
1
C C
6
PH/PL
NC
0
NC
0
NOTES
O Degree
Connector Downtoward
180 Degree
Connector Uptoward
For Two Buttons
For Four Buttons
TouchPad Connector
5V_S05V_S0
16V, Y5V, +80%/-20%
C27
1uF
*
C0603
LEFT
RIGHT
R602
0
+/-5%
R0402
10V, Y5V, +80%/-20%
FPC CONN_12P
12
11
10
9
8
7
SHIELD2
6
5
4
SHIELD1
3
2
1
TOUCHPAD_CONN2
TEMP
14
13
TDATA
TCLK
C26
0.1uF
C0402
*
R485
10K
R0402
TDATA29
TCLK29
B B
+/-5%
C28
33pF
50V, NPO, +/-5%
C0603
*
R486
10K
R0402
+/-5%
C29
33pF
*
50V, NPO, +/-5%
C0603
KROW629
KROW529
KROW429
KROW329
KROW229
KROW129
KCOL1629
KCOL1529
KCOL1429
KCOL1329
KCOL1229
KCOL1129
KCOL1029
KCOL929
KCOL829
KCOL729
KCOL629
KCOL529
KCOL429
KCOL329
KCOL229
KCOL129
KBC_MATRIX129
KBC_MATRIX029
Keyboard matrix ( from vendor )
KROW8
KROW7
KROW6
KROW5
KROW4
KROW3
KROW2
KROW1
KCOL16
KCOL15
KCOL14
KCOL13
KCOL12
KCOL11
KCOL10
KCOL9
KCOL8
KCOL7
KCOL6
KCOL5
KCOL4
KCOL3
KCOL2
KCOL1
KBC_MATRIX1
KBC_MATRIX0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FPC CONN_28P_R/A
3D3V_S0
R487 10K R0402 +/-5%
R488 10K R0402 +/-5%
TEMP
JapUS
KBC_MATRIX0
KBC_MATRIX1
OhterEur
RIGHT
SW_Right1
1
2
3
4
5
GND
Tactile Switch
A A
5
D40
BAV99
3
Dummy
LEFT
SW_Left1
1
2
3
4
5
GND
21
Tactile Switch
5VTP
4
D39
BAV99
3
Dummy
21
BC676
0.1uF
*
16V, Y5V, +80%/-20%
C0402
Dummy
MATRIXID1#
MATRIXID2#
3
1
1
001
1
00
TECHNOLOGY COPR.
Title
KBC CONN
Document Numbe r Rev
S06 MAINBOARD
of
2
Date: Sheet
32 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 33
5
hocnghetructuyen.vn
4
3
2
1
100 mil
D D
C C
5V_S0 USB2PWR
F3
*
F1813_0.75A
B_USB_PN715
B_USB_PP715
B_USB_PN7 USB_7-
B_USB_PP7
USB1PWR
BC537
10V, Y5V, +80%/-20%
4.7uF
*
*
C0805
4 3
1
Common Choke 90 Ohm 2L
BC538
16V, Y5V, +80%/-20%
0.1uF
C0402
R493 0
R0402 +/-5%
L20
Dummy
R495 0
R0402 +/-5%
100 mil
BC539
1nF
*
50V, X7R, +/-10%
C0402
2
*
TC14
150uF
6.3V, +/-20%
CTX
USB_7+
USB1PWR
USB3
5
VCC
1
USB-
2
3
USB+
GND
4
6
USB
B_USB_PN115
B_USB_PP115
B_USB_PN015
B_USB_PP015
100 mil
5V_S0
B_USB_PN1
B_USB_PP1
B_USB_PN0
B_USB_PP0
F2
*
F1210_1.1A
R494 0
R0402 +/-5%
L21
4 3
1
Common Choke 90 Ohm 2L
Dummy
R496 0
R0402 +/-5%
R498 0
R0402 +/-5%
L23
4 3
1
Common Choke 90 Ohm 2L
Dummy
R500 0
R0402 +/-5%
10V, Y5V, +80%/-20%
BC535
0.1uF
C0402
100 mil
16V, Y5V, +80%/-20%
50V, X7R, +/-10%
BC536
1nF
*
C0402
USB_1USB_1+
USB_0USB_0+
*
USB2PWR
USB2PWR
TC13
150uF
6.3V, +/-20%
CTX
USB1
5
VCC
1
USB-
2
3
USB+
GND
4
6
USB
USB2
5
VCC
1
USB-
2
3
USB+
GND
4
6
USB
BC534
4.7uF
*
*
C0805
2
2
B B
A A
TECHNOLOGY COPR.
Title
USB*2*2/POWERSWITCH
5
Document Number Rev
4
3
2
Date: Sheet
S06 MAINBOARD
1
33 45Thursday, December 16, 2004
A
of
Page 34
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4
3
2
1
H1
MHT23X29_B23X60
D D
C C
1
H2
MH31X39
1
H11
MH27X34
1
H15
MH32X80
1
H17
MH35X60
1
H10
MHT23X29_B23X60
1
H3
MH31X39
1
H12
MH27X34
1
H16
MH32X80
1
H18
MH35X60
1
H13
MH27X34
1
H19
MH35X60
H4
MH27X80
1
H14
MH27X34
1
H20
MH35X60
1
H5
MH27X80
1
1
H6
MH27X80
1
H7
MH27X80
1
H8
MH27X80
1
AUD_AGND_S
H9
MH27X80
1
B B
A A
TECHNOLOGY COPR.
Title
HOLE/UNUSED PARTS
Document Numbe r Rev
5
S06 MAINBOARD
of
4
3
2
Date: Sheet
34 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 35
A
hocnghetructuyen.vn
MBATA+
PC1
*
0.1uF
50V, Y5V, +80%/-20%
4 4
C0603
PR1 0
R0805 +/-5%
PR2 0
R0805 +/-5%
PC2
*
47pF
50V, NPO, +/-5%
C0402
could change it to FB
(FB L0805 30 Ohm, 4A)
*
PC3
1nF
50V, NPO, +/-5%
C0603
PR152
10K
+/-5%
R0402
Dummy
PR155
10K
+/-5%
R0402
Dummy
PR153
+/-5%
R0402
PR156
+/-5%
R0402
47K
10K
*
B
PR154
100K
+/-5%
R0402
BTSENSEBT+_BAT
PC117
0.1uF
16V, Y5V, +80%/-20%
C0402
BAT_TH29
BAT_KBC_DAT129
BAT_KBC_SCL129
BTSENSE 29
PR3 0 R0402 +/-5%
PR4 0 R0402 +/-5%
PR5 0 R0402 +/-5%
3
2 1
PD1
BAV99
Dummy
3D3V_S5
3D3V_S5 3D3V_S5 3D3V_S5
C
PR10
10K
+/-5%
R0402
3
2 1
PD2
BAV99
Dummy
PR147
10K
+/-5%
R0402
BATCN_MBATA+
BATCN_SMB_PRES#
BATCN_SMB_DAT
BATCN_SMB_CLK
3
2 1
PD3
BAV99
Dummy
D
PR146
10K
+/-5%
R0402
E
BAT1
7
6
5
4
3
2
1
BAT7P
REF3D3V
AGND_OZ8603D3V_S5 3D3V_S5
PR6
100K
+/-1%
R0603
Dummy
PR8
100K
+/-1%
R0603
Dummy
PR7
100K
+/-1%
R0603
Dummy
ISET
VSET
PR9
100K
+/-1%
R0603
Dummy
VINT
3 3
ADIN
ADIN
PR17
PC10
0.1uF
C0603
25V, Y5V, +80%/-20%
Dummy
22K
+/-5%
r0402h4
PR160 10K +/-5% R0402
PR22 10K
+/-5% R0402
*
0.1uF
PC119
A
*
2 2
CELLS29
IOUT
VSET
PR21
10K
+/-5%
R0402
1 1
AGND_OZ860 AGND_OZ860
PR12
33m
r2512h9
+/-1%
PR14
10
+/-5%
R0402
*
PC12
2.2uF
25V, Y5V, +80%/-20%
C0805
0.1uF
PC115
16V, Y5V, +80%/-20%
C0402
Dummy
16V, Y5V, +80%/-20%
C0402
*
PR15
+/-5%
R0402
ADIN
PD27
SSM54PT
1 2
PD4
SSM54PT
ADIN1
10
1 2
*
1uF
C0805
PC8
25V, Y5V, +80%/-20%
OZ860_IACM
OZ860_IACP
PR19 10K
+/-5% R0402
*
PC13 0 .22uF
C0603 16V, Y5V, +80%/-20%
REF3D3V
10V, Y5V, +80%/-20%
*
PC17
AGND_OZ860
OZ860_COMP1
PC14 10uF
PC15
2.2uF
C0603
AGND_OZ860 AGND_OZ860AGND_OZ860AGND_OZ860
VINT
*
4.7uF
C1206
25V, Y5V, +80%/-20%
PR23 150
*
*
B
ADIN2
PR11
10K
R0402
+/-5%
PQ2
SI4435BDY
1
2
3
4 5
10uF
C1210
PC120
*
C080510V, Y5V, +80%/-20%
PC118
R0402+/-5%
25V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
C0402
OZ860_CELLS
OZ860_IOUT
OZ860_VSET
OZ860_COMP
OZ860_LV
*
OZ860_HDR1
PC9
10uF
PR18
0
R0603
+/-5%
25V, Y5V, +80%/-20%
8
S
D
7
CHARGEBAT1
6
G
SSM54PT
PU1
1
CELLS
2
IOUT
3
VSET
4
COMP
5
GND
6
LV
7
REF
8
VAC
GNDP
17
C1210
AGND_OZ860
Will change this part before SMT(6.8uH)
PL1 3.3uH
*
1 2
PD5
1 2
ISET
IACP
IACM
VBATT
ICHP
ACAV
CHIGH
HDR
Dummy
25V, Y5V, +80%/-20%
OZ860_ISET0
16
OZ860_IACP
15
OZ860_IACM
14
MBATA+
13
OZ860_ICHP
12
OZ860_ACAV
11
OZ860_CHIGH
10
OZ860_HDR
9
PC5
10uF
C1210
*
OZ8604LN
*
PC16
0.47uF
25V, Y5V, +80%/-20%
C0805
C
*
PC6
10uF
25V, Y5V, +80%/-20%
C1210
AGND_OZ860
AGND_OZ860
CHARGEBAT2
OZ860_ICHP
MBATA+
PC114
*
0.1uF
16V, Y5V, +80%/-20%
C0402
PR24
10K
+/-5%
R0402
PJ1
1 2
JUMPER1
PR16 10
PC11
*
2.2uF
25V, Y5V, +80%/-20%
C0805
AC_IN 29
AD in use
+/-5%R0402
DS
AGND_OZ860
D
PR13
33m
r2512h9
+/-1%
PQ35
2N7002EPT
G
123
45
PQ1
S
G
SI4435BDY
D
678
PC7
0.1uF
*
25V, Y5V, +80%/-20%
C0603
PR20
10K
+/-5%
R0402
PR158
10K
+/-5%
R0402
AGND_OZ860
ISET 29
CHARON#/OFF 29
Title
Charger
Document Number Rev
S06 MAINBOARD
Date: Sheet
PC4
*
10uF
25V, Y5V, +80%/-20%
C1210
Note:
CELLS=Hi-Z for 2 cells
CELLS= Low for 3 cells
CELLS= High for 4 cells
All the decupling close to the
active pins an d ground: ref, lv,
vset, iset, comp and gnd
VINT
MBATA+
TECHNOLOGY COPR.
35 45Thursday, December 16, 2004
E
of
A
Page 36
PR32
hocnghetructuyen.vn
47K
+/-5%
R0402
MAX1999_SLP_VEST
PR33
47K
+/-5%
R0402
PWRPM_SLP_S3
S0_EN17,20 ,29,37,38,40,42
7A/3D3V
3D3V_S5
PSHORT2
*
PC29
0.1uF
C0402
16V, Y5V, +80%/-20%
5V_AUX_S5
MAX1999_SHUTDOWN_S5#
MAX985_SHDN#
SHUTDOWN_S518
50V, NPO, +/-5%
PR46
47K
+/-5%
R0402
2 1
CTX
PTC1
220uF
4V, +/-20%, D.F.=8%
100pF
PD26
CH501H-40
VCC3D3V
*
PC32
*
C0402
MAX1999AGND
*
PTC14
PR38
6.8K
+/-1%
R0402
PR42
10K
+/-1%
R0402
G
MAX1999AGND
TP0610K
S D
G
MAX1999AGND
CTX
220uF
Dummy
4V, +/-20%, D.F.=8%
PR47
0
R0402
+/-5%
DS
PQ9
2N7002EPT
PQ3
2 1
G
DS
PQ52N7002EPT
*
*
PL3
4.7uH
IHLP2525CZRZ4R7M01
Dummy
PR48
+/-5%
R0402
*
PC35
0.1uF
MAX1999AGND
M1999_CTLTON
PD6
CH501H-40
MAX1999_SKIP#
DCBATOUT
*
PC25
4.7uF
C1206
25V, Y5V, +80%/-20%
Will change this
part before SMT
(2.2UH,9A)
21
0
Will change this
part before SMT
(180K;+/-1%)
*
PC36
0.1uF
C0402
16V, Y5V, +80%/-20%
MAX1999AGND
BAIN
PR31
150K
+/-5%
R0402
PR142
100K
+/-5%
R0402
PR35
MAX1999AGND
0
+/-5%
R0805
*
M1999V+P3
678
DDD
D
123
D
GSS
4 5
PR51
100K
+/-1%
r0402h4
S
678
S
PR44
4.7K
+/-5%
R0603
PR49
18K
+/-1%
R0402
Dummy
GSS
4 5
DDD
123
MAX1999_VCCMAX1999_VCC
PQ6
Si4800BDY
DCBATOUT
MAX1999_ON3
MAX1999_ON5
PC26
0.1uF
C0603
25V, X7R, +/-10%
PQ7
PD10
SI4892DY
Dummy
SSM24PT
BAIN
C0402
16V, Y5V, +80%/-20%
MAX1999AGND MAX1999AGND
MAX1999_LDO5
DCBATOUT
PD9
2 1
PR34
4.7
+/-5%
R0805
*
PC24
4.7uF
C1206
25V, Y5V, +80%/-20%
PC27
0.1uF
*
C0603
25V, Y5V, +80%/-20%
PR144
4.7K
+/-5%
R0603
Dummy
Will change this
part before SMT
PR50
(180K;+/-1%)
18K
+/-1%
R0402
Dummy
MAX1999_ILIM3
MAX1999_ILIM5
PR52
100K
+/-1%
r0402h4
CH501H-40
PC23
PR36
0
R0402
+/-5%
2 1
DRV_BST3
0.1uF
C0603
25V, X7R, +/-10%
MAX1999_BST3
MAX1999_FB3
MAX1999_SHDN#
MAX1999_ON3
MAX1999_ON5
5V_AUX_S5
PD7
CH501H-40
MAX1999_LDO5
MAX1999_V+
MAX1999_DH3
MAX1999_LX 3
MAX1999_DL3
MAX1999_ILIM3
MAX1999_ILIM5
PR25
0
+/-5%
R0402
*
PC18
PU2
18
LDO5
20
V+
28
BST3
26
DH3
27
LX3
24
DL3
22
OUT3
7
FB3
6
SHDN
3
ON3
4
ON5
5
ILIM3
11
ILIM5
DCBATOUT
PR139
300K
+/-5%
R0402
2.2uF
C0603
PR140
100K
+/-5%
R0402
PR26
2 1
10V, Y5V, +80%/-20%
PD8
CH501H-40
12
*
MAX1999AGND
MAX1999_SKIP#
SKIP
13
TON
17
VCC
14
BST5
16
DH5
15
LX5
19
DL5
PR30
10
+/-5%
R0805
PC19
1uF
10V, Y5V, +80%/-20%
C0603
MAX1999_BST5
DRV_BST5
MAX1999_TON
MAX1999_VCC
PR37 0
MAX1999_DH5
MAX1999_LX 5
MAX1999_DL5
100K
R0402
+/-5%
Dummy
25V, Y5V, +80%/-20%
MAX1999
21
23
PR141
1M
R0402
+/-5%
GND
N.C.
LDO3
1
25
MAX1999_LDO3
*
OUT5
FB5
PGOOD
REF
PRO
PC34
10uF
C0805
10V, Y5V, +80%/-20%
5V_AUX_S5
MAX1999_FB5
9
MAX1999_PGOOD
2
M1999_VREF
8
10
MAX1999AGND
10V, X7R, +/-10%
PR40
0
+/-5%
3D3V_AUX_S5
R0402
MAX985_SHDN#
PC33
0.22uF
*
C0603
MAX1999AGND
MAX985_SHDN# 39
PU13
1
OUT
2
VCC
3
IN+
MAX985
Low4 Protect CKT
+/-5%
R0402
PC28
0.1uF
C0603
5V_AUX_S5
PR41
100K
+/-5%
R0402
VEE
IN-
DCBATOUT
PR27
0
+/-5%
R0402
PQ4
Si4800BDY
MAX1999AGND
M1999V+P5
678
DDD
D
GSS
S
123
4 5
*
*
10uF
PC20
C1210
25V, X5R, +/-10%
PR28
0
PR29
+/-5%
0
R0805
+/-5%
R0805
*
PC22
0.1uF
10uF
PC21
C1210
C0603
25V, X5R, +/-10%
25V, Y5V, +80%/-20%
7A/5V
5V_S5
PSHORT1
*
PL2
*
678
D
PQ8
SI4892DY
GSS
S
4 5
5
M1999_VREFMAX985_IN
4
5.6uH
DDD
21
PD11
SSM24PT
123
21
PD12
Dummy
SSM24PT
Dummy
PR39
15K
+/-1%
r0402h4
MAX1999AGND
Title
MAX1999+ 5V/3D3V
Document Number Rev
S06 MAINBOARD
Date: Sheet
1
2
*
PR43
9.76K
+/-1%
r0402h4
VCC5V
PTC3
150uF
6.3V, +/-20%
CTD
Dummy
PC31
100pF
*
C0402
50V, NPO, +/-5%
*
PTC2
150uF
6.3V, +/-20%
CTD
PJ2
JUMPER1
PC30
*
0.1uF
16V, Y5V, +80%/-20%
C0402
12
MAX1999AGND
TECHNOLOGY C OPR.
of
36 45Thursday, Decem be r 1 6, 2004
A
Page 37
5
hocnghetructuyen.vn
D D
3D3V_S0
*
OZ824AGND
*
OZ824AGNDOZ824AGND
VCC_PWRGD39
5V_S0
PR57
22
+/-5%
R0603
+/-5%
R0402
+/-5%
PR63
0
+/-5%
R0402
OZ824AGND
PC47
1nF
50V, X7R, +/-10%
PC50
1nF
50V, X7R, +/-10%
PC38 47nF
C0402
16V. Y5V, +80/-20%
OZ824_ON2
OZ824_VIN
OZ824_VREF
OZ824_VDDA
OZ824_ON1
PC46
*
1uF
C0603
C0402
PC49
47nF
16V. Y5V, +80/-20%
C0402
*
C0402
OZ824_VIN1
PR56
1K
+/-5%
R0603
S0_EN17,20,29,36,38,40,42
16V, Y5V, +80%/-20%
PR143 0
Dummy
PR61 0
R0402
S0_EN18,29,41
C0603
PR62
102K
+/-1%
R0402
OZ824_SET1
1
PR64
45K
+/-1%
r0402h4
2
OZ824_SET2
PR65
105K
+/-1%
r0402h4
5
C C
*
10nF
PC42
OZ824AGNDOZ824AGND
B B
A A
S0_EN_D29
*
PC45
0.22uF
C0603
50V, X7R, +/-10%
PR53
100K
+/-5%
R0402
OZ824_SLEW2
*
OZ824_SET2
PU3
1
ON2
2
NC
3
VIN
4
VREF
5
GNDA
6
VDDA
7
CE
8
ON1
OZ824_SET1
OZ824_SLEW1
3D3V_S0 3D3V_S0
4
PR68
100K
+/-5%
R0402
4
33
GNDA
PR54
10K
+/-5%
R0402
OZ824_SKIP2
28
26
29
31
32
SKIP2
VSET2
25
27
30
LX2
CS2P
CS2N
PGD2
HDR2
SLEW2
OZ824LN
VSET19SKIP110SLEW111CS1N12CS1P13PGD114HDR1
OZ824_SKIP1
PR69
10K
+/-5%
R0402
LX1
16
15
OZ824_CS1NF
3D3V_S0
OZ824_CS2NF
OZ824_CS2PF
OZ824_HDR2
OZ824_LX2
24
BST2
23
GNDP2
22
LDR2
21
VDDP2
20
VDDP1
19
LDR1
18
GNDP1
17
BST1
PC48
0.22uF
25V, X7R, +/-10%
C0805
OZ824_LX1
OZ824_CS1PF
PC39
0.22uF
25V, X7R, +/-10%
*
C0805
OZ824_LDR1
*
OZ824AGND
OZ824_LDR2
OZ824_BST2
5V_S5
*
OZ824_BST1
PJ3
1 2
JUMPER1
3
PD14
CH501H-40
C0603
CH501H-40
PC41 1uF
OZ824_HDR1
3
PC37
25V, Y5V, +80%/-20%
PD15
10uF
C1210
21
21
PQ12
SI4392DY
PQ13
Si4856DY
OZ824_VIN1
*
678
DDD
D
PQ10
GSS
S
Si4800BDY
123
4 5
678
DDD
D
PQ11
GSS
4 5
D
GSS
4 5
D
GSS
4 5
SI4892DY
S
123
678
DDD
S
123
678
DDD
S
123
25V, Y5V, +80%/-20%
21
21
Dummy
PC54
10uF
C1210
DCBATOUT
PG4
1 2
OPEN-POWER-GAP-3050
DCBATOUT
PD16
SSM24PT
1 2
Dummy
OZ824_VIN2
PD18
SSM24PT
*
PG3
1 2
OPEN-POWER-GAP-3050
OZ824_CS2PF
OZ824_CS2NF
PG5
PG6
1 2
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
OZ824_CS1PF
OZ824_CS1NF
PC121
10uF
*
25V, Y5V, +80%/-20%
C1210
2
PL4
2.2uH
*
PR59
120K
+/-1%
R0603
PC40 3.3nF
C0603
50V, X7R, +/-10%
PC43
*
22pF
50V, NPO, +/-5%
C0402
OZ824AGND OZ824AGND
PL9 1uH Dummy
*
PL5 0.68uH
*
PR70
52.3K
+/-1%
R0603
Dummy
PC51 3.3nF
C0603
50V, X7R, +/-10%
PC52
22pF
*
50V, NPO, +/-5%
C0402
OZ824AGND OZ824AGND
2
1
PSHORT4
PTC5
220uF
7A/1.05V
1D05V_S0
CTX
2.5V, +/-20%
PR58
15K
+/-5%
R0402
PR60
45.3K
+/-1%
R0603
PR55
51
+/-1%
R0603
Vin: 3S2P -- 10.8V/typ;
OZ824_1D05V_S0
21
*
PD13
Dummy
SSM24PT
PTC4
220uF
2.5V, +/-20%
CTX
*
*
14A/1.5V
1D5V_S0
PSHORT5
CTX
PR66
15K
+/-5%
R0402
2.5V, +/-20%
PTC13 330uF
1.0uH
PR71
267K
+/-1%
R0603
PC44
*
1nF
50V, X7R, + / - 10%
C0402
PR67
51
+/-1%
R0603
OZ824_1D5V_S0
21
PD17
Dummy
SSM24PT
PSHORT9
CTX
*
*
2.5V, +/-20%
PTC6 330uF
*
PC53
1nF
*
50V, X7R, + / - 10%
C0402
Title
OZ824
Document Number Rev
S06 MAINBOARD
Date: Sheet
TECHNOLOGY COPR.
37 45Thursday, December 16, 2004
1
of
A
Page 38
5
hocnghetructuyen.vn
SC486_1D8V
D D
PC58
*
10pF
C0402
DDR_VREF
50V, NPO, +/-5%
3mA
PG1
PG2
1 2
OPEN-POWER-GAP-3050
PR82
10
+/-5%
R0402
SC486_DDR
12
*
PC65
SC486AGND
0D9V_S0 3A
VTT_MEM
C C
1 2
OPEN-POWER-GAP-3050
*
B B
A A
5
1uF
PR75
10
R0402
+/-5%
1
PR80
2.26K
+/-1%
r0402h4
2
PR81
PR83
10K
+/-1%
R0402
C0402
10V, Y5V, +80%/-20%
*
PC68
0.1uF
C0603
25V, Y5V, +80%/-20%
10
R0402
+/-5%
12
*
1uF
PC59
10V, Y5V, +80%/-20%
12
*
PC62
*
10uF
PC69
PC70
C0805
6.3V, X5R, +/-10%
PR76
820K
+/-1%
r0402h4
C0402
*
C0603
25V, NPO, +/-5%
PC63 1nF
*
PC60
16V, Y5V, +80%/-20%
C0402
10V, Y5V, +80%/-20%
*
C0805
6.3V, X5R, +/-10%
0.1uF
C0402
10uF
PC71
C0805
0
1
01
1uF
10uF
0
0
11
4
SC486DCBATOUT
PR77
10
+/-5%
R0402
SC486_VTTEN
SC486_VDDQS
SC486_TON
SC486_FB
SC486_COMP
SC486_VTTS
SC486_VCCA
C0603
12
*
PC66
12
1uF
*
10V, Y5V, +80%/-20%
C0402
1uF
PC73
C0402
10V, Y5V, +80%/-20%
SC486AGND
PR84
*
10
+/-5%
R0402
PC64 68nF
16V, X7R, +/-10%
SC486_VTT
*
22uF
PC72
C1206
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
11
3
2
6
8
9
10
5
4
14
15
12
13
16
17
PR86
0
R0402
+/-5%
PU4
VTTEN
VDDQS
TON
FB
REF
COMP
VTTS
VCCA
VSSA
VTT_1
VTT_2
VDDP2_1
VDDP2_2
PGND2_1
PGND2_2
SC486IM
VREFVTT_MEMVTT_MEM/ENVDIMM/EN VDIMM
XXX
XXX
X1.8
0.9
1.8 0.9
4
0.9
25
3
THERMALPAD
3
PGD
EN/PSV
BST
ILIM
VDDP1
PGND1
DH
LX
DL
S0_EN17,20,29,36,37,40,42
S3_EN29
7
SC486_EN
1
SC486_BST
24
SC486_DH
23
SC486_ILIM
21
SC486_LX
22
SC486_DL
19
SC486_VDDP1
20
18
1
PR78
470K
+/-5%
R0402H4
2
PR162
0
R0402
+/-5%
1 2
PR85
15K
r0402h4
+/-1%
2 1
*
PR87
0
R0402
+/-5%
PR88
0
R0402
+/-5%
5V_S5
PD19
DRV_BST
PC61
SC486AGND
SC486AGND
PR74
0
R0402
+/-5%
CH501H-40
0.1uF
C0603
25V, Y5V, +80%/-20%
PC74
12
1uF
*
10V, Y5V, +80%/-20%
C0402
*
PC75 0.1uF
16V, Y5V, +80%/-20%
*
PC76 0.1uF
16V, Y5V, +80%/-20%
PR79
0
R0402
+/-5%
Dummy
C0402
C0402
2
PQ14
SI4892DY
PQ15
SC486_VTTEN
2
D
GSS
4 5
D
Si4856DY
GSS
4 5
SC486_EN
OPEN-POWER-GAP-3050
*
C1210
25V, Y5V, +80%/-20%
1
PG7
1 2
OPEN-POWER-GAP-3050
10uF
PC57
C1210
25V, Y5V, +80%/-20%
DCBATOUT
2A 2A
*
SC486_PGDSC486_PG
1
PC55
PTP1
*
10uF
0.1uF
PC56
25V, X7R, +/-10%
C0603
1D8V_S3 13A
678
DDD
S
PL8 1uH Dummy
123
*
1uH
PL6
0.68uH
*
Dummy
678
DDD
S
123
Title
Document Number Rev
Date: Sheet
SC486_1D8V
PC67
0.1uF
*
10V, X7R, +/-10%
C0402
*
SC486(1D8V-S3&0D9V-S0)
S06 MAINBOARD
PSHORT6
PTC7
330uF
2.5V, +/-20%
CTX
1
PG8
1 2
VDIMM
PTC8
330uF
*
2.5V, +/-20%
CTX
TECHNOLOGY COPR.
of
38 45Friday, December 17, 2004
A
Page 39
5
hocnghetructuyen.vn
4
3
2
1
3D3V_S0
PR89
30K
+/-5%
R0603
G
3D3V_S0
PR101
100K
+/-5%
R0402
*
VCORE_AGND
DS
3D3V_S0
3D3VPULL
G
PQ18
2N7002EPT
*
DS
MAX985_SHDN#36
PR106
100K
+/-5%
R0402
PC91
0.1uF
16V, Y5V, +80%/-20%
C0402
Dummy
D D
PM_DPRSLPVR15
PM_STPCPU#3,15
VCORE_AGND
C C
VRMPWRGD16
16V, Y5V, +80%/-20%
B B
PC90
0.1uF
C0402
Dummy
VTT_PWRGD#3
VCORE_AGND
SC451_CMPRF1 SC451_CMPRF
DS
PQ16
G
2N7002EPT
2N7002EPT
H_VID55
H_VID45
H_VID35
H_VID25
H_VID15
H_VID05
*
10V, Y5V, +80%/-20%
PD28
PC94
1nF
25V, NPO, +/-5%
C0603
PQ17
VCC_PWRGD37
SC451_PBOOT
PR90
82.5K
+/-1%
R0603
C0603
VCORE_AGND
PR95 0
PR96 0
PR97 0
PR99 0
PR100 0
PR102 0
2 1
CH501H-40
PM_DPRSLPVR
PR109
100K
+/-5%
R0402
VCORE_AGND
SC451_VDPR
*
PC84
1uF
+/-5%
R0402
+/-5%
R0402
+/-5%
R0402
+/-5%
R0402
+/-5%
R0402
+/-5%
R0402
PC95 1nF
25V, NPO, +/-5%
5V_S0
*
C0603
PR91
10
+/-5%
R0603
VCORE_AGND
SC451_VCCA
SC451_VID5
SC451_VID4
SC451_VID3
SC451_VID2
SC451_VID1
SC451_VID0
SC451_PBOOT
SC451_VDPR
SC451_HYS
PR110
36.5K
+/-1%
R0603
PR111
33.2K
+/-1%
R0603
PR115
54.9k
+/-1%
R0603
PC85
330pF
*
50V, NPO, +/-5%
C0603
21
10
11
12
13
14
16
25
15
SC451_SS
*
PC93
PR113
249K
+/-1%
R0603
VCC_CORE_S0
+/-5%
R0402
PU5
VCCA
9
VID5
VID4
VID3
VID2
VID1
VID0
PWRGD
6
PBOOT
ENPAD
5
VDPR
4
DPRSL
7
CLK_EN#
8
HYS
SS
SC451IT
15nF
C0603
25V, Y5V, +80%/-20%
PR92
300
5V_S0
VCOREDCBATOUT
PQ19
PQ21
SI4392DY
Si4856DY
PR107
1K
+/-1%
R0402
678
D
GSS
S
4 5
678
D
GSS
S
4 5
DDD
123
DDD
123
PD20
*
CH501H-40
2 1
BST1_VCORE
PR93
3.3
+/-5%
R0603
SC451_BST
SC451_CORE
3
28
17
V5
CORE
GND
19
BST
DRN
PGND
CMP
CLRF
CMPRF
DAC
SC451_DH
2
TG
SC451_LX
1
SC451_DL
27
BG
26
SC451_CL
24
CL
SC451_CMP VH_R1
23
SC451_CLRF
22
SC451_CMPRF
20
SC451_DAC
18
*
VCORE_AGND
*
C0805
PC77 4.7uF
10V, Y5V, +80%/-20%
*
PC86
1uF
25V, Y5V, +80%/-20%
PR103 681 R0603+/-1%
PR104 464 R0603+/-1%
PR105 681 R0603+/-1%
PC92
1nF
C0603
25V, NPO, +/-5%
C0805
PC78 0.1uF
25V, Y5V, +80%/-20%
PR108
1K
+/-1%
R0402
C0603
PQ20
PQ22
678
DDD
D
*
SI4392DY
GSS
S
123
4 5
678
DDD
D
Si4856DY
GSS
S
123
4 5
1 2
PC79
0.1uF
25V, Y5V, +80%/-20%
*
C0603
*
PC80
PL7
0.68uH
0.1uF
25V, Y5V, +80%/-20%
*
C0603
*
PC87
4.7uF
Dummy
C0805
10V, Y5V, +80%/-20%
SC451_LX1
PD21
Dummy
SSM54PT
0
PR98
+/-5%
Dummy
R0402
PC81
PR94
1m
+/-1%
R2612
10uF
*
C1210
25V, X5R, +/-10%
PPSHORT1
10uF
PC82
25V, X5R, +/-10%
PD22
SSM54PT
1 2
Dummy
DCBATOUT
*
C1210
*
PC88 0.1uF C0603
10uF
PC83
25V, X5R, +/-10%
VCC_CORE_S0
*
25V, X7R, +/-10%
C1210
*
PC89 0.1uF C0603
10uF
C1210
PC129
25V, X5R, +/-10%
VCC_CORE_S0
*
*
25V, X7R, +/-10%
2.5V, +/-20%
PTC10 330uF CTX
PTC9 330uF CTX
*
*
2.5V, +/-20%
2.5V, +/-20%
PTC12 330uF CTX
PTC11 330uF CTX
Dummy
2.5V, +/-20%
VCORE_AGND
SC451_CL
A A
VCORE_AGND
5
PR116
0
+/-5%
R0402
VCORE_AGNDVCORE_AGND
SC451_CMP SC451_CMPRF
PC97
*
220pF
C0402
25V, NPO, +/-5%
4
SC451_CLRF
PC98
*
180pF
C0603
50V, NPO, +/-5%
VCORE_AGND
ACTIVE DEEP DEEPER
0or1
2
1
Title
VCORE_SC451
Document Number Rev
S06 MAINBOARD
Date: Sheet
TECHNOLOGY C OPR.
1
A
of
39 45Thursday, Decem be r 1 6, 2004
00
3
PM_DPRSLPVR
PM_STPCPU#
1 0
PC99
220pF
25V, NPO, +/-5%
C0402
*
180pF
C0603
PC100
50V, NPO, +/-5%
*
Page 40
5
hocnghetructuyen.vn
4
3
2
1
Run Power
MOSVCC
D D
C C
S0_EN17,20,29,36,37,38,42
PDCIN1
B B
DC-IN
A A
5
1
3
2
PR117
330K
R0402
+/-5%
AD_OFF29
MOSVCC_VG
PSHORT8
PQ23
TP0610K
S D
G
PC101
0.1uF
*
50V
C0603
PR119
330K
+/-5%
R0402
S01N#
DS
PQ24
G
2N7002EPT
DS
PQ34
G
2N7002EPT
S02N#
PR118
330K
+/-5%
R0402
Adaptor in to generate DCBATOUT
PC102
0.1uF
*
50V, Y5V, +80%/-20%
C0603
13
AD_OFF#_JK
DS
PQ27
G
2N7002EPT
2
4
PQ26
DRVTOS0
3D3V_S0
PU8
Si4800BDY
G
4 5
S
3
S
2
S
1
1D8V_S0 VDIMM
AD+_1POWER_ADIN
PR121
100K
*
+/-5%
R0402
DTA124EUA
PC104
0.1uF
C0603
50V, Y5V, +80%/-20%
PU12
Si4800BDY
G
4 5
S
3
S
2
S
1
@PM
D
8
7
6
SI4435BDY
AD+_2
1
PR122
56K
+/-5%
r0402h4
2
PU7
3
S
G
D
D
6
D
7
D
8
D
D
6
D
7
D
8
1
2
3
45
PQ25
1
S
2
3
4 5
SI4435BDY
PC116 0.1uF
G
3D3V_S5
5V_S55V_S0
PR163
100K
+/-5%
R0402
C040216V, Y5V, +80%/-20%
*
Dummy
8
D
7
6
PC105
*
0.1uF
50V, Y5V, +80%/-20%
C0603
ADIN
10V, Y5V, +80%/-20%
*
PC103
0.1uF
50V, Y5V, +80%/-20%
C0603
3D3V_S0
2D5V_S0
PC111
1uF
C0603
*
PR164
10K
*
+/-5%
R0402
2D5V_PWRGD
PC123
2D5VVGA_S0
Io = 2.0A
Vo=2.52V
=0.8*(21.5+10)/10
2
168mA
2D5V_S0
*
22pF
C0402
I max = 300 mA
PU11
1
SHDN#
2
GND
3
IN
G913C
10uF
C0805
6.3V, Y5V, +80%/-20%
PC112
5
SET
4
OUT
*
1uF
C0603
PC113
5V_S03D3V_S0
PTC15
220uF
*
*
1uF
C0603
PC122
10V, Y5V, +80%/-20%
4
VPP
1
POK
2
VEN
3
VIN
2.5V, +/-20%
CTB
PU14
6
VO
2D5V_S0_FB
7
ADJ
5
NC
GND
GND
8
9
G966
*
50V, NPO, +/-5%
10V, Y5V, +80%/-20%
2D5V_S0
PC124
1uF
2D5V_S0_SET
10V, Y5V, +80%/-20%
PR137
10K
+/-1%
R0402
PR138
10K
+/-1%
R0402
C0603
PR165
10K
+/-1%
R0402
Dummy
PR166
10K
+/-1%
R0402
Will change this
part before SMT
TECHNOLOGY COPR.
Title
Other power
Document Number Rev
S06 MAINBOARD
Date: Sheet
1
of
40 45Friday, December 17, 2004
(21.5K;+/-1%)
A
Page 41
5
hocnghetructuyen.vn
4
3
PR123
2
1
ADIN_3
R
PU10
A C
LM431ACM3
1K
R0603
+/-5%
ADIN_SET
PR128
2.2K
+/-1%
R0603
Dummy
PR129
1K
+/-1%
R0603
Dummy
R0603
Dummy
PR126
+/-5%
MOSVCC
0
21
PD29
MMSZ2V4T1
Dummy
Will change this
part before SMT
(MMSE8V2T1G)
PC106
1uF
*
25V, Y5V, +80%/-20%
C0805
Adapter
D D
19V DC, 3.42A, 65W
Battery
ADIN
MBATA+
3S2P 10.8V
PR124 0
R0402 +/-5%
ADIN_1
12
PD23
BAT54CPT
3
PR125 330
R0603 +/-5%
Dummy
Vref= 2.5V
P=1/4 W
Dummy
Vout=Vref*(1+R1/R2)
ADIN_2
C C
1D5V_S5
3D3V_S5
PR167
10K
*
+/-5%
R0402
1D5V_S5PGD
PC127
10uF
C0805
6.3V, Y5V, +80%/ -20%
1D5V_S5
B B
A A
Io = 270mA
1D5V_S5PGD
Vo=1.5V
=0.8*(21+24)/24
29
5
C0603
10V, Y5V, +80%/-20%
4
1
2
3
1uF
5V_S5
*
PC125
VPP
POK
VEN
VIN
*
PU15
VO
ADJ
NC
GND
GND
8
9
2
4
5
Tactile Switch
G966
PSW1
GND
PC126
6
7
5
10uF
1D5V_S5
C0805
6.3V, Y5V, +80%/ -20%
1D5V_S5_FB
*
1
3
1uF
PC128
10V, Y5V, +80%/-20%
MBATA_D2
PR168
21K
+/-1%
R0402
PR169
10K
+/-1%
R0402
C0603
Dummy
Will change this
part before SMT
(24K;+/-1%)
*
100pF
PC110
PR134
10K
+/-5%
R0402
PQ33
PMBT3906
B
C0402
Dummy
50V, NPO, +/-5%
4
ADIN
MBATA+
EC
PR136
100K
R0402
+/-5%
C0603
50V, Y5V, +80%/-20%
0.1uF
MBATA_D3
*
*
PC108
PR145
R0402
+/-5%
Dummy
DC Working Peak Reserve 20V
PC107
0.1uF
50V, Y5V, +80%/-20%
C0603
PQ28
PMBT3906
E C
PR130
0
100K
R0402
+/-5%
DTC144EUA
2
2
PQ32
MBATA_D1
B
PQ29
DTC144EUA
1 3
3D3V_AUX_S5
PR135
100K
R0402
+/-5%
1 3
PD24
CH501H-40
MBATA1
*
50V, NPO, +/-5%
21
PD25
CH501H-40
MBATA_D4
PC109
100pF
C0402
3
21
EC_PWRBTN# 29
BAIN
existence existence
PR131
10K
+/-5%
R0402
BAINPSW1BatteryAdapter
inexistenceexistence
ON
OFF
existenceinexistence
ON
OFF
OPEN
ON
OFF
VINT
PR133
100K
R0402
+/-5%
S5_EN18,29, 37
2
PQ30
1
S
D
2
3
G
4 5
SI4435BDY
PQ31
DTC144EUA
1 3
8
7
6
H
H
H
H
H
VINT_D
PR132
0
R0402
+/-5%
Dummy
EC_PWRBTN#
L
H
L
H
H
L
DCBATOUT
TECHNOLOGY COPR.
Title
Save Power circuit
Document Numbe r Rev
S06 MAINBOARD
of
2
Date: Sheet
41 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 42
5V_S0 2D5V_S0
hocnghetructuyen.vn
BC542
0.1uF
*
16V, Y5V, +80%/-20%
C0402
Dummy
3D3V_S0
BC544
0.1uF
*
16V, Y5V, +80%/-20%
C0402
Dummy
DCBATOUT
BC546
0.1uF
*
25V, Y5V, +80%/-20%
C0603
PEG_RXP[15..0]7
PEG_RXN[15..0]7
PEG_TXP[15..0]7
PEG_TXN[15..0]7
BC543
0.1uF
*
16V, Y5V, +80%/-20%
C0402
Dummy
BC545
0.1uF
*
16V, Y5V, +80%/-20%
C0402
Dummy
BC547
0.1uF
*
25V, Y5V, +80%/-20%
C0603
1D8V_S0
BC688
0.1uF
*
16V, Y5V, +80%/-20%
C0402
Dummy
GMODULE_RST#15
EX_DDCDATA12
GF1
@PM
231
1
2
3
DCBATOUT
PEG_RXN15
PEG_RXP15
PEG_RXN14
PEG_RXP14
PEG_RXN13
PEG_RXP13
PEG_RXN12
PEG_RXP12
PEG_RXN11
PEG_RXP11
PEG_RXN10
PEG_RXP10
PEG_RXN9
PEG_RXP9
PEG_RXN8
PEG_RXP8
PEG_RXN7
PEG_RXP7
PEG_RXN6
PEG_RXP6
PEG_RXN5
PEG_RXP5
PEG_RXN4
PEG_RXP4
PEG_RXN3
PEG_RXP3
PEG_RXN2
PEG_RXP2
PEG_RXN1
PEG_RXP1
PEG_RXN0
PEG_RXP0
CLK_PCIE_PEG#3
CLK_PCIE_PEG3
PLT_RST1#7,15,17,29,30
B_KBC_DAT118,29
B_KBC_SCL118,29
EX_HSYNC12
EX_VSYNC12
EX_DDCCLK12
AC_BAT#29
S0_EN17,20,29,36,37,38,40
R634 0 R0402 +/-5%
R539 0
R0402 +/-5%
AC_BAT
TP104
TP105
1D5V_S0
Dummy
R628 0
R0402 +/-5%
THERM_ALERT#_GPIO8
1
THRM_ALERT#
1
Reserved
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
MXM230P
1D8V_S0
PEG_TXN15
PEG_TXP15
PEG_TXN14
PEG_TXP14
PEG_TXN13
PEG_TXP13
PEG_TXN12
PEG_TXP12
PEG_TXN11
PEG_TXP11
PEG_TXN10
PEG_TXP10
PEG_TXN9
PEG_TXP9
PEG_TXN8
PEG_TXP8
PEG_TXN7
PEG_TXP7
PEG_TXN6
PEG_TXP6
PEG_TXN5
PEG_TXP5
PEG_TXN4
PEG_TXP4
PEG_TXN3
PEG_TXP3
PEG_TXN2
PEG_TXP2
PEG_TXN1
PEG_TXP1
PEG_TXN0
PEG_TXP0
EX_TXACLKEX_TXACLK+
EX_TXAOUT2EX_TXAOUT2+
EX_TXAOUT1EX_TXAOUT1+
EX_TXAOUT0EX_TXAOUT0+
5V_S0
EX_TV_CRMA 12
EX_TV_LUMA 12
EX_TV_COPM 12
EX_RED 12
EX_GREEN 12
EX_BLUE 12
Dummy
R629 0
R0402 +/-5%
R633 0
R0402 +/-5%
LDDC_CLK 7,13
LDDC_DATA 7,13
EX_LCDVDD_ON 13
EX_BRIGHTNESS 13
EX_BL_ON 29
2D5V_S0
3D3V_S0
MXM_PGD
MXM_PGD 29
VGA_PWROK 18
RN63 0 8P4R0603+/-5%
1
TXACLKTXACLK+
TXAOUT2TXAOUT2+
TXAOUT1TXAOUT1+
TXAOUT0TXAOUT0+
*
3
5
7 8
@PM
RN64 0 8P4R0603+/-5%
1
*
3
5
7 8
@PM
RN65 0 8P4R0603+/-5%
1
*
3
5
7 8
@GM
RN66 0 8P4R0603+/-5%
1
*
3
5
7 8
@GM
TXAOUT2+13
TXAOUT2-13
TXACLK+13
TXACLK-13
TXAOUT0+13
TXAOUT0-13
TXAOUT1+13
TXAOUT1-13
TXAOUT2- EX_TXAOUT2TXACLK+ EX_TXACLK+
TXACLK- EX_TXACLK-
TXAOUT0+
TXAOUT0TXAOUT1+
TXAOUT1- EX_TXAOUT1-
2
4
6
2
4
6
2
4
6
2
4
6
EX_TXAOUT2+TXAOUT2+
EX_TXAOUT0+
EX_TXAOUT0EX_TXAOUT1+
GMCH_TXACLK- 7
GMCH_TXACLK+ 7
GMCH_TXAOUT2- 7
GMCH_TXAOUT2+ 7
GMCH_TXAOUT1- 7
GMCH_TXAOUT1+ 7
GMCH_TXAOUT0- 7
GMCH_TXAOUT0+ 7
TECHNOLOGY COPR.
Title
External Graphic Conn.
Document Number Rev
S06 MAINBOARD
Date: Sheet
42 45Thursday, December 16, 2004
A
of
Page 43
8
hocnghetructuyen.vn
hocnghetructuyen.vn
7
6
NOTE:
THIS PAGE SHOWS THE OZ601T CONFIGURED WITH
EXTERNAL IDSEL AND WITHOUT 12V VPP SUPPORT.
5
4
3
2
1
D D
3D3V_S0
3D3V_S0
BC681
10uF
*
C0805
@OZ601T
BC685
10uF
*
C0805
@OZ601T
BC682
*
C0402
@OZ601T
*
@OZ601T
NOTE: IDSEL SELECTION!
THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME.
C C
IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE
PCI AD LINES OR EXTERNAL IDSEL SIGNAL.
22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE
REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO
SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS.
THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS.
CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS
FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY
CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST
BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC.
VCC5# VPP_PGM IDSEL SELECT
(124) (123)
DOWN DOWN AD18
DOWN UP AD20
UP DOWN AD25
B B
UP UP PIN 127
A A
22K TO 47K PULL-UPS MUST BE PLACED
ON INTA#, PME#, SERIRQ# & CLKRUN#.
0.1uF
BC686
0.1uF
C0402
BC683
0.1uF
*
C0402
@OZ601T
BC687
0.1uF
*
C0402
@OZ601T
B_PCI_AD[31..0]15,21,24,28
B_PCI_C/BE#315,21,24,28
B_PCI_C/BE#215,21,24,28
B_PCI_C/BE#115,21,24,28
B_PCI_C/BE#015,21,24,28
B_PCI_DEVSEL#15,21,24,28
B_PCI_FRAME#15,21,24,28
B_PCI_IRDY#15,21,24,28
B_PCI_TRDY#15,21,24,28
B_PCI_STOP#1 5,21,24,28
B_PM_CLKRUN#15,21, 24, 28, 29, 30
PCLK_PCM3,21
B_PCI_PAR15,21, 24, 28
CBUS_PME#21,22,28
INT_PIRQE#15,21
INT_SERIRQ15,21,28,29,30
*
@OZ601T
PCI_SPKR21,26
PCI_REQ#015,21
PCI_GNT#015,21
PCIRST1#15,21,24,28
BC684
0.1uF
C0402
R616 33 R 0402 +/-5%
3D3V_S0
B_PCI_AD31
B_PCI_AD30
B_PCI_AD29
B_PCI_AD28
B_PCI_AD27
B_PCI_AD26
B_PCI_AD25
B_PCI_AD24
B_PCI_AD23
B_PCI_AD22
B_PCI_AD21
B_PCI_AD20
B_PCI_AD19
B_PCI_AD18
B_PCI_AD17
B_PCI_AD16
B_PCI_AD15
B_PCI_AD14
B_PCI_AD13
B_PCI_AD12
B_PCI_AD11
B_PCI_AD10
B_PCI_AD9
B_PCI_AD8
B_PCI_AD7
B_PCI_AD6
B_PCI_AD5
B_PCI_AD4
B_PCI_AD3
B_PCI_AD2
B_PCI_AD1
B_PCI_AD0
@OZ601T
@OZ601T
R617 0
R0402 +/-5%
3D3V_S0
IDSEL SELECT POWER-ON-STRAPPING
U46
64
CORE_VCC
77
CORE_VCC
97
CORE_VCC
115
CORE_VCC
1
PCI_VCC
20
PCI_VCC
33
PCI_VCC
4
AD31
5
AD30
6
AD29
7
AD28
8
AD27
9
AD26
10
AD25
13
AD24
14
AD23
15
AD22
16
AD21
17
AD20
18
AD19
19
AD18
21
AD17
22
AD16
28
AD15
29
AD14
30
AD13
31
AD12
34
AD11
35
AD10
36
AD9
37
AD8
38
AD7
39
AD6
40
AD5
41
AD4
42
AD3
43
AD2
44
AD1
46
AD0
11
C/BE3#
12
C/BE2#
49
C/BE1#
50
C/BE0#
26
PCI_CLK
27
DEVSEL#
23
FRAME#
24
IRDY#
25
TRDY#
47
STOP#
48
PAR
51
PERR#/SPKR_OUT
2
REQ#
3
GNT#
126
RST#
120
PME#/RI_OUT#
52
MF0
53
MF3
54
MF4
55
MF6
VCC5#/VCCD0#/SDATA
VCC3#/VCCD1#/SCLK
VPP_PGM/VPPD0/SLATCH
VPP_VCC/VPPD1/IDSEL
GND32GND45GND65GND96GND
(SEE NOTE & TABLE FOR
OPTIONS)
124
125
123
127
103
CAD31
102
CAD30
101
CAD29
100
CAD28
99
CAD27
110
CAD26
109
CAD25
108
CAD24
106
CAD23
105
CAD22
104
CAD21
118
CAD20
95
CAD19
94
CAD18
93
CAD17
75
CAD16
73
CAD15
74
CAD14
71
CAD13
72
CAD12
70
CAD11
69
CAD10
68
CAD9
85
CAD8
84
CAD7
82
CAD6
83
CAD5
80
CAD4
81
CAD3
78
CAD2
79
CAD1
76
CAD0
107
CCLK
114
CFRAME#
117
CIRDY#
116
CTRDY#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD1#
CCD2#
CAUDIO
CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#
OZ601@OZ601T
113
61
58
60
91
89
62
88
59
87
119
98
86
63
57
121
56
122
92
90
111
112
66
67
CDEVSEL#
CCLKRUN#
CSTSCHG
128
VCC5# VPP_PGM PULL HIGH IN PAGE 21
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
VCC5_OZ2211
VCC3_OZ2211
R0402+/-5%
100
CCLK_1
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD1#
CCD2#
CAUDIO
CSTSCHG
CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#
R622
@OZ601T
VCC5_OZ2211 21
VCC3_OZ2211 21
ODR_VCC3# 21,23
CAD[31:0] 21
CCLKRUN# 21
B_PCI_AD25
CCLK_1 21
CFRAME# 21
CIRDY# 21
CTRDY# 21
CDEVSEL# 21
CSTOP# 21
CPAR 21
CPERR# 21
CSERR# 21
CREQ# 21
CGNT# 21
CINT# 21
CBLOCK# 21
CRST# 21
R2_D2 21
R2_D14 21
R2_A18 21
CVS1 21
CVS2 21
CCD1# 21
CCD2# 21
CAUDIO 21
CSTSCHG 21
CC/BE3# 21
CC/BE2# 21
CC/BE1# 21
CC/BE0# 21
TECHNOLOGY COPR.
Title
OZ601T(DUAL LAYOUT)
Document Numbe r Rev
8
S06 MAINBOARD
of
7
6
5
4
3
Date: Sheet
2
43 45Thursday, Dec e mbe r 1 6, 2004
1
A
Page 44
5
0
hocnghetructuyen.vn
4
11_25
BC403 Change to 10u, del BC407,C25,BC411,R614,R615,DUMMY BC434,BC435,BC438,BC439,R389,R391,R392,R346,Q9
3
2
1
CHANGE BC417,BC418,BC428,BC429 TO Y5V 0603,CHANGE C23 TO 0402 Y5V,C24 TO 4.7U 0805 Y5V
11_09.MOVE VRMPGD BUFFER FROM PAGE 39(VCORE) TO PAGE 16(ICH 3 OF 4)
11_10.Modify T/P Connector Circuit for Material Change
11_10.Modify Parts to Combine BOM
R241 R0402 +/-1% TO R0402 +/-5%
R48 R0603 +/- 1% TO R0402 +/-5%
D D
R47,R57,R84,R85,R86,R113,R114,R115,R178,R179,R180,R197,R200,R203 TO R0402 +/-5%
DEL BC458,BC459,R434,R440,R444,R404,BC461,R434,R538,CHANGE BC530 TO Y5V,R489,R490,R491,R492,BC450 TO 0402
DUMMY U29,U28,R537,R538,BC621,RN61,RN62,R387,R413,R414,R405,BC478,BC479,BC480,BC481
ADD BC689,BC690,BC691,R618,R619,R620,R621,R622,R542,MOVE ISET,VSET TO DA4,DA5 CHANGE R326 TO 20K 0402
CHANGE BC403 TO TOLERANCE 10%,BC404 TO Y5V,
BC3,BC27,PC69,PC70,PC71,BC283,BC322,BC323,BC339,BC355,BC620,BC472,TC12 TO +80%/-20%, Y5V, 10V, SMD0805 CC0805ZRY5V6BB106
BC450,BC462,BC477,BC478,BC479,BC480,BC481,C19,BC499,BC500,BC501,BC529,BC531,BC532,BC533,BC618,BC622,BC623,BC636,BC514 TO CC0603ZRY5V6BB105 CAP, 1uF, +80%/-20%, Y5V, 10V, SMD0603
BC619,BC637 FROM CAP, 220pF, +/-5%, NPO, 50V, SMD0603 TO CAP, 220pF, +/-5%, NPO, 25V, SMD0402
Q1,Q2,Q4,Q5,PQ5,Q6,Q7,Q18,Q19,Q20,Q21,Q9 FROM MOS N, 2N7002, 7.5 Ohm@Vgs=10V, SOT-23-3P, SMD TO MOS N, 2N7002, 5.3 Ohm@Vgs=4.5V, SOT-23-3P, SMD
BC1,BC534,BC537 FROM CAP, 4.7uF, +/-10%, X5R, 10V, SMD0805 TO CAP, 4.7uF, +80%/-20%, Y5V, 10V, SMD0805
Change CarBus Controler From CB810 to OZ711MP1
11_10. change Q10 TO P-CHANNEL MOS
add R630 R631, DUMMY R95,R96,R613 DEL R474,R539,R14712_07
11_11. Change MDC Suspend Power from 3D3V_Lan_s5 to 3D3v_S5
11_11. Add R604,L13,L14 use TDK
11_11. chang MOS 2N7002 TO VENDOR CHEMKO
change USB to use 0,1,6,7 four Ports
11_12. Modify Parts to combine BOM
change BC12,PC13,C24,C25,C26,BC373,BC374,BC375 from CAP, 0.1uF, +80%/-20%, Y5V, 16V, SMD0603 CC0603ZRY5V7BB104 TO CAP, 0.1uF, +80%/-20%, Y5V, 16V, SMD0402 CC0402ZRY5V7BB104
BC76 FROM CAP, 1 u F , +80%/-20%, Y5V, 6.3V, SMD0402 CC0402ZRY5V5BB105 TO CAP, 1uF, +80%/-20%, Y5V, 10V, SMD040 CC0402ZRY5V6BB105
BC581,BC583,BC587,BC589,BC593,BC595,BC597,BC599,BC601,BC603,BC605,BC607,BC609,BC611,BC613,BC615 FROM CAP, 2.2uF, +80%/-20%, Y5V, 16V, SMD0805 CC0805ZRY5V7BB225 TO CAP, 2.2uF, +80%/-20%, Y5V, 1
BC409,BC307 FROM CAP, 22uF, +80%/-20%, Y5V, 10V, SMD1206 CC1206ZRY5V6BB226 TO CAP, 22uF, +/-10%, X5R, 6.3V, SMD1206 CC1206KRX5R5BB226
C C
BC378,BC380,BC381,BC382,BC385,BC389,BC395 FROM CAP, 4.7uF, +/-10%, X5R, 6.3V, SMD0805 CC0805KRX5R5BB475 TO CAP, 4.7uF, +80%/-20%, Y5V, 10V, SMD0805 CC0805ZRY5V6BB475
11_12. Modefy CR1 S_VCC Pin CONNECT to SD/MS/XD_DATA1
11_13. Page21, add CarBus PME# signal connection to ICH6
11_13. Page 20 change R345 Dummy
11_13. Change U4A,U4B,U4C to 74HCT1G125GW U36,U37,U38
11_13.Change R352,R353,R354,R355 R493,R494,R495,R496,R497,R498,R499,R500 TO 0402 0 ohm
11_14.Page 7 Modefy the Level Shift circuit,change R507,R508 Reserved,Q18,Q19,R506 @GM
11_14. Replace LAN FB with 0 Ohm,include FB3,4,5,6,7
11_14.Change R352,353,354,355 to 1% tolerence
11_15.Change R34,R40 Reserved
11_15.change R133,R140 to R0805
11_15 add R612,R613
11_15 chang Page 25 Lan Transformer H5062@Giga and H1285@8100c
11_15. Add BC679,BC680
12_2
DEL SMBUS OF LAN,DEL R518,R542,ADD R627,R628,BC692,CHANGE R518 TO 22ohm, CHANGE D37,CORRECT AC'97 BIT CLOCK
CHANGE BC622,BC623 TO 0.47U,BC499 TO 10U, BC500 TO 0.1U,TC1,TC2 TO C2016M0100SD
ADD R629,R630,R631,DEL R540
12_3
DEL EC's 168 pin, DEL SMI# OF EC, ADD THERMAL ALERT TO EXT_GRAHPIC
11_16 Change R260 Dummy,R539 Reserved
11_18 Change L13,L14 to TDK ACM2012-900-2P-T000
11_18 page 7 Del some CFG pins and TestPoints to meet Layout needs
B B
11_22. change R368 Reserved
11_23. Updated connector accroding ME's request Audio Jack, RTC header, Battery CONN changed
11_24. UPDATED EXTERNAL GRAPHIC CARD, DEL GID SIGNALS
11_26
ADD R623,R624,NET RTC SENSE, CHANGE OZ601T REMARK TO @OZ601T
MOVE R622 FOR IDSEL, MODIFIED IT TO 100OHM,ADD R623,R625,R626,
DUMMY R18,R26,CHANGE TC1,TC2,TC13,TC14,TC9,TC15,R447,R448
Change BC444 Reserved,R185,R186 @GM
12_15
1.change PR56 to 0603 1K (RC0603JR-071K)
12_4
2.PR18 change to 0603 0ohm (RC0603JR-070R)
3.OZ8604LN pin7 name change to REF3D3V
4.VSET ISET need pull low with 10K
5.ADD PD27 (SSM54PT)
6.ADD PR152-PR156 (RC0402JR-0710K)
7.ADD PR159 (RC0402JR-0733K)
8.ADD PC117,PC118 (CC0402ZRY5V7BB104)
9.CHANGE PC16 TO 0.47uF (CC0805ZRY5V8BB474)
10.CHANGE PR59,PR70 TO 120K (RC0603FR-07120K)
11.CHANGE PR60,PR71 TO 45.3K (RC0603FR-0745K3)
1.PC1,PC3 CHANGE TO REQUEST
2.PC17 CHANGE TO 4.7uF
3.OZ860 Pin17:AGND
4.OZ824 PGD2 PULL HIGH 3D3V_S5
5.OZ824 SKIP2 CONNECT TO 3D3V_S5
6.OZ824 Pin6,7 VDDA,CE CONNECT TO 5V_S5
7.PC14,PC34 CHANGE TO REQUEST
8.PC39,PC48 PC33 PC42 PC67 CHANGE TO REQUEST
9.PQ24,PQ5,PQ9,PQ27 CHANGE TO 2N7002EPT
10.PQ3 CHANGE TO TP0610K
A A
11.PD10,PD11,PD12 CHANGE TO SSM24PT
12.PD19 CHANGE TO CH501H-40
13.PTC1 CHANGE TO 4TPE220MIC
14.ADD ONE PU10:Si4800BDY
15.PR22 CHANGE TO REQUEST
16.ADD NETNAME
5
2004 11 13年月日
1.PC13(CC0603ZRY5V7BB104) CHANGE TO CC0603ZRY5V8BB104
2.PC15(CC0603ZRY5V5BB225) CHANGE TO CC0603ZRY5V6BB225
3.PC99(CC0402JRNPO9BN221) CHANGE TO CC0402JRNPO8BN221
2004 11 17年月日
1.PR115 (RC0603FR-0754K9) CHANGE TO RC0402FR-0754K9
2.PC27,PC28 (CC0603KRX7R8BB104) CHANGE TO CC0603ZRY5V8BB104
3.ADD TWO BY PASS CAP PC114,PC115 (CC0402ZRY5V7BB104) TO OZ860 PIN3&PIN16
4.MAX1999 ADD LOW4 PROTECT CKT
5.CHANGE PD13 (DUMMT) TO DUMMY
6.PC13 (CC0603ZRY5V8BB104) CHANGE TO CC0402ZRY5V7BB104
4
3
2004 11 19年月日
1.ADD PQ34 2N7002EPT
2.CHANGE PU7 TO SI4435BDY
3.ADD PR143 RC0402JR-07100K
4.ADD PC116 CC0402ZRY5V7BB104
2004 11 24年月日
1.ADD PR145 DUMMY RCO4O2（） JR-070R
2.ADD PR144 DUMMY RCO6O3J（） R-074K7
3.CHANGE PR139 TO RCO4O2JR-07300K
4.CHANGE PR140 TO RCO4O2JR-07100K
2004 11 25年月日
1.CHANGE PR12 PR13 TO 33m (WSL2512R0330FEK)
2.CHANGE PTC2 PTC3 TO (TLPSLV0J157M(18)12RE)
2
2004 11 29年月日
1.CHANGE PR56 TO 1K (RC0402JR-071K)
2.CHANGE PR64 TO 45K (RC0402FR-0745K)
3.CHANGE PR65 TO 105K (RC0402FR-07105K)
4.CHANGE PL5 TO 3.3uH (IHLP2525CZRZ3R3M01)
5.CHANGE PR17 TO (RC0402JR-0722K)
2004121年月日
1.CHANGE PU1 TO OZ8604LN
2.P35:ADD FUNCTION:CHARON#/OFF,AND BTSENSE
3.ADD PR148,PR149,PR150,PD27,PQ35
4.CHANGE PR 62 (RC0402FR-07100K)
Title
HISTORY
Document Numbe r Rev
S06 MAINBOARD
Date: Sheet
TECHNOLOGY COPR.
44 45Thursday, Dec e mbe r 1 6, 2004
1
of
A
Page 45
5
hocnghetructuyen.vn
D D
Device
Rails
CPU GMCH ICH6-M ENE3910
4
DDRII
Audio HDD ODD LCD INV USB2.0 LAN SIO
3
2
OZ711
CLK
GEN
EXT
VGA
1
3D3V_AUX_S5
5V_AUX_S5
3D3V_S5
5V_S5
C C
VDIMM
(1D8V_S3)
VTT_MEM
(0D9V_S0)
3D3V_S0
5V_S0
2D5V_S0
1D5V_S0
1D5V_S5
B B
1D05V_S0
VCC_CORE_S0
1D8V_S0
DCBATOUT
A A
TECHNOLOGY COPR.
45 45Thursday, Dec e mbe r 1 6, 2004
1
of
A
5
Title
POWER PLANE
Document Numbe r Rev
S06 MAINBOARD
4
3
2
Date: Sheet
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