LDV5010
DVC Read Channel
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1. LDV5010 FEATURE OVERVIEW
The LDV5010 Channel is tailored to run on the 41.85MHz Digital Video Camera
(DVC) platform. The main function is to read the signal from the media
(presented by the preamp), extracting the data and the data clock for the
controller. The secondary function is to detect the Automatic Tracking
Frequencies of 465KHz and 697.5KHz. In the DVC system, the LDV5010 interfaces
to the Preamp, MicroProcessor and Controller. Channel performance information
is available through LDV5010’s Quality Engine, which can be used as a metric
to help optimize the channel’s bit-error-rate.
The LDV5010 utilizes a 0.18 micron CMOS process technology for low power
consumption and a small die area. The part requires two power supplies: 3.3V
+/-10% and 1.8V +/-10% or one power supply of 3.3V +/-10% (with internal 1.8V
voltage regulator enabled). The part is available in a 64-pin TQFP package.
2. CHIP FEATURES
2.1. General Features
• Fully integrated 41.85 MHz Read Channel Device
• Supports constant density recording of 41.85Mbps with no external component
changes
• Fabricated in .18 micron CMOS technology
• Operating supply voltages: 3.3 ± 10% and 1.8 +/-10% volts or one 3.3 ± 10%
(with internal 1.8V voltage regulator enabled).
• Available in a 64-pin TQFP package.
2.2. Read Data Conditioning
• Full-Differential Analog Front-End
• PR4 Automatic Sampled-time Gain Control Loop Algorithm
¾ 4-Banded Variable Gain Amplifier to accommodate input signal ranges
of 30-300mVppd
¾ normalize the incoming data within 100-300 samples
¾ Optional VGA initial gain shadow registers for each head/field
combination
¾ Locks to random or 6T acquisition fields
• 7
th
-order Bessel Continuous Time Filter
¾ Programmable Filter Supports Cut-offs from 6 to 30 MHz
¾ Filter boost programmable from 0 to 10dB
¾ Flat Group Delay +/- 5% up to 1.5* Fc, without boost
• 6-bit Analog-To-Digital Converter
¾ Automatic Offset Correction
• PR4 Sampled-time Timing Recovery Loop to frequency and phase acquire
¾ acquires to the incoming data within 100 to 300 samples on a 6T
acquisition field
¾ Locks to random data or a 6T acquisition field
• Digital Full-LMS Adaptive Equalizer
¾ Correlation Detector detects highly correlated fields (2T, 4T, 6T or
12T) and stops adaptation
LDV5010
DVC Read Channel
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• PR4 Viterbi for Data Detection
• Programmable Drop-Out detection
2.3. User programmable fields for system optimization
• Programmable Head Recovery Delay
• Programmable IDLE times after drop-out, excess zeros and gaps
• Programmable Length of LowZ after readgate (RG Pin) assertion
• Programmable acquisition field lengths for gain and timing recovery loops
2.4. Head and Field Sensitive Features
• When applicable, unique user defined parameters are provided for audio, and
non-audio fields for head0 or head1 combinations in order to optimize for
each head/field combination.
2.5. ATF Detector
• The LDV5010 includes a Digital Heterodyne Tuner to detect the servo
automatic tracking frequencies (ATF)
• Servo tone amplitude difference is provided on the STDIF output pin.
2.6. Trick Mode Support
• Due to the programmable registers, the user is able to configure the part
to work properly in various modes of operation, such as NTSC LP Forward and
LP Reverse.
• Dropouts are automatically detected via the Dropout detector block
2.7. Channel Optimization Vehicles
• Quality Metrics for use in Channel Optimization
• 8-bit Digital Test Bus for Testability and Channel Optimization
2.8. Test Modes
• Built-In-Test logic to minimize test vectors and allow fault testing in the
field
• Analog Test Inputs and Outputs are provided for control and observation of
internal analog blocks
• An 8-bit Digital Test Bus is provided for Digital and some Analog
Testability
2.9. User Interface
• Three-bit Serial Interface Port for access of internal configuration
registers
¾ to load and verify register contents
¾ to monitor status
¾ to collect chip feedback
2.10. Powerdown Modes
• Register controlled powerdown of analog blocks
• During non-read mode, the clock to the digital logic is shut-off to
conserve power
LDV5010
DVC Read Channel
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• An internal Power-On-Circuit (POR) monitors the voltage level. When the
voltage is too small, the chip is placed in powerdown mode, until the
voltage assumes a working level.
• External Power-down pin
3. ABSOLUTE MAXIMUM RATINGS
Input Voltages:
CMOS Digital Pins........... .................. ......... -0.3 V +3.6 V
Analog Pins................. .................. ......... -0.3 V +3.6 V
Storage Temperature, T
stg
.... .................. ......... -65oC to 150oC
Junction Temperature, T
J
.... .................. ......... 0 oC to 110oC
Thermal Impedance, Θ
JA
:
Still Air................... .................. ......... 51
o
C/W
200 fpm air flow............ .................. ......... 38
o
C/W
600 fpm air flow............ .................. ......... 27
o
C/W
Maximum power consumption:
Power supply maximum drawn current (with internal 1.8V
regulator enabled @V
CC
= 3.3V).................. ....... 70mA
4. LDV5010 CHIP I/O
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42
41
40
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61 53
63
62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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45
44
43
42
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1
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LDV5000
VSC
RCT
VDC
ENREG
VDG
RAB
VSG
DIP
DIN
VSB
RFIL
VDB
ATO1N
VSE
ATO1P
VDE
VSA
ATIP
VDA
ATIN
VDT
CTR
VST
FREF
VSD4
RCK
VDD4
RD
VDI2
RSTB
VSI2
PD
VSD1
ATO2P
VDD1
ATO2N
VDF
STDIF
VSD2
TB0
VDD2
TB1
VDI1
TB2
VSI1
TB3
VSF
DIFREF
SM
SSADET
RG
ADPHL
D
VDD3
DO
VSD3
SD
SEN
SCK
TB7
TB6
TB5
TB4
HDSEL
LOCK
64
LDV5010
Pin assignments for LDV5010 in a 64-pin TQFP package.
LDV5010
DVC Read Channel
LDIC 4 LDIC Confidential
L
DV501
0 Blo
ck
Diagram
VG
A
DI
P
DIN
VG
X
VG
Y
CTF
VG
X
VG
Y
CTX
CTY
A
F
adrd afrd
cdcd
DD
afrd ddrd
AD
C
CTX
CTY
adrd
afrd
adrd
slrd
trsl
adafrd
TRD
pherr adafrd
slrd
phadj
TR
A
pherr
phadj
trck
fref
adrd
afrd
adafrd
gcsl
slrd
GCD
gcnewus
slrd
adafrd
gcerr
gcdac
padDIP
padDIN
slgcrd
ddrd
sltrrd
ddrd
padrd
CK
rsck
trckfref
padFREF
CC
DO
padRG
QE
afrd
tb
adrd
gcerr
gcnewus
trerr
adrg
afrg
lowz
updo
UP
reg_sel
padSEN
padSD
padSCK
updi
updo
up
w
upr
padSEN
padSD
padSCK
reg_selects
updi
updo
up
w
upr
adrd
afrd
adrg
afrg
lowz
trerr
gcerr
gcnewus
padTB
PG
pgrd
pgrg
pgrg pgrd
test
data
S
A
updord
padRG
gcnewus
gcnewus
gcerr
gcdac
padXZ
updo
IO_TL
padATOAC
padATIX
padATIY
padATODC
padATIX
padATIY
padATOACx/y
padATODCx/y
POR
porb
V
D
V
D
porb
padRG
CD
cdcdslrd
cdcd
cdcd
Note: Grey shading indicates an analog block
XZ
ccgctrk
cctrtrk
ccgcrg
cctrrg
lowz
cciacq
GCDA
C
TD
XZ
iorg
gcnewus
DO
padDO
LDV5010 Data Path Block Diagram
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