Ordering number : EN*5237
D3095HA (OT) No. 5237-1/16
Overview
The LC8905V is for use in IEC 958 and EIAJ CP-1201
format data transmission between digital audio equipment.
This LSI is used on the receiving side, and handles
synchronization with the input signal and demodulation of
that signal to a normal format signal.
Features
• On-chip PLL circuit synchronizes with the transmitted
IEC 958 and EIAJ CP-1201 format signal.
• Provides 128fs, bit, and L/R clock outputs.
• System clock can be selected to be either 384fs or 512fs.
• Microprocessor interface code settings for different
output types
— Input pin, emphasis output, input bi-phase data
output, and validity flag output settings
— Audio data output format setting
— Channel status output (32-bit output for consumer
products)
— Subcode Q output with CRC flags (80 bits)
• Start ID and shortening ID detection for DAT (Digital
Audio Tape recorder) that use subcodes
• CMOS, single-voltage power supply
• Miniature package: SSOP-24
Package Dimensions
unit: mm
3175A-SSOP24
Preliminary
SANYO: SSOP24
[LC8905V]
LC8905V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Digital Audio Interface Receiver
CMOS LSI
Pin Assignment
Pin Functions
No. 5237-2/16
LC8905V
Pin No. Symbol I/O Description
1 DIN1 I Data input with built-in amplifier (for coaxial or optical module input)
2 DIN2 I Data input (for optical module input)
3 E/DOUT O Emphasis, input bi-phase, and validity flag output
4 V
DD
Power supply
5 R I VCO gain control input
6 VIN I VCO free-running setting input
7 VCO O PLL low-pass filter setting
8 GND Ground
9 CKSEL I System clock selection input (384fs or 512fs)
10 XMODE I Reset input
11 AVOCK I PLL error lock avoidance clock input
12 TST1 I Test input (Must be connected to ground in normal operation)
13 TST2 I Test input (Must be connected to ground in normal operation)
14 SCLK/CL I Microprocessor interface clock input
15 XLAT/CE I Microprocessor interface latch/chip enable input
16 SWDT/DI I Microprocessor interface write data input
17 SRDT/DO O Microprocessor interface read data output
18 DQSY/LD O Microprocessor interface subcode Q and ID synchronization output
19 CKOUT O VCO clock output (free running, 384fs, or 512fs)
20 FS128 O 128fs clock output
21 BCK O Bit clock output
22 LRCK O L/R clock output (left channel = high, right channel = low)
23 DATAOUT O Audio data output
24 ERROR O PLL lock error mute output
Block Diagram
No. 5237-3/16
LC8905V
Specifications
Absolute Maximum Ratings at Ta = 25°C
Allowable Operating Ranges
Electrical Characteristics
DC Characteristics at Ta = –30 to +75°C, VDD= 4.5 to 5.5 V, VSS= 0 V
AC Characteristics at Ta = –30 to +75°C, VDD= 4.5 to 5.5 V
No. 5237-4/16
LC8905V
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
DD
max –0.3 to +7.0 V
Maximum I/O voltages V
IVO
max –0.3 to VDD+ 0.3 V
Operating temperature Topr –30 to +75 °C
Storage temperature Tstg –55 to +125 °C
Parameter Symbol Conditions min typ max Unit
Supply voltage V
DD
4.5 5.0 5.5 V
Parameter Symbol Conditions min typ max Unit
Input high-level voltage V
IH
1 Applies to the DIN2 pin. TTL levels 2.2 VDD+ 0.3 V
Input low-level voltage V
IL
1 Applies to the DIN2 pin. TTL levels –0.3 +0.8 V
Input high-level voltage V
IH
2
Applies to the CKSEL, AVOCK, TST1, and TST2 pins.
0.7 V
DD
VDD+ 0.3 V
CMOS levels
Input low-level voltage VIL2
Applies to the CKSEL, AVOCK, TST1, and TST2 pins.
–0.3 0.3 V
DD
V
CMOS levels
Input high-level voltage VIH3
Applies to the XMODE, SCLK/CL, XLAT/CE,
0.8 V
DD
VDD+ 0.3 V
SWDT/DI pins. CMOS Schmitt inputs
Input low-level voltage VIL3
Applies to the XMODE, SCLK/CL, XLAT/CE,
–0.3 0.2 V
DD
V
SWDT/DI pins. CMOS Schmitt inputs
Input high-level voltage V
OHIOH
= –1 µA VDD– 0.05 V
Input low-level voltage V
OL
IOL= 1 µA VDD+ 0.05 V
Current drain I
DD
VDD= 5.0 V, Ta = 25°C, input data fs = 48 kHz 10 15 mA
Input amplitude Vpp Measured before the DIN1 pin input capacitor. 0.4 V
DD
+ 0.3 V
Parameter Symbol Conditions min typ max Unit
Input pulse width t
WBI
10 µs
Output pulse width t
WBO
fs = 48 kHz 160 ns
Output data setup time t
DSO
80 ns
Output data hold time t
DHO
80 ns
Output delay t
BD
–10 0 +10 ns
No. 5237-5/16
LC8905V
Microprocessor Interface Block AC Characteristics
at Ta = –30 to +75°C, VDD= 4.5 to 5.5 V (when CKSEL is low)
Input mode
Output mode
No. 5237-6/16
LC8905V
Parameter Symbol Conditions min typ max Unit
CL low pulse width t
WL
100 ns
CL high pulse width t
WH
100 ns
Data setup time t
DS
50 ns
Data hold time t
DH
50 ns
CE delay time t
D3
1.0 µs
CL delay time t
D4
50 ns
CE delay time t
D5
100 ns
LD pulse width t
W
fs = 44.1 kHz 136 µs
Data delay time t
D1
CL = 30 pF 75 ns
Data delay time t
D2
CL = 30 pF 75 ns
Microprocessor Interface Block AC Characteristics
at Ta = –30 to +75°C, VDD= 4.5 to 5.5 V (when CKSEL is high)
Input mode
Output mode
No. 5237-7/16
LC8905V
Parameter Symbol Conditions min typ max Unit
CL low pulse width t
WL
100 ns
CL high pulse width t
WH
100 ns
Data setup time t
DS
50 ns
Data hold time t
DH
50 ns
CE delay time t
D
100 µs
LD pulse width t
W
fs = 44.1 kHz 136 µs
Data delay time t
D1
CL = 30 pF 75 ns
Data delay time t
D2
CL = 30 pF 75 ns
Functions
1. Data Input and Output (DIN1, DIN2, E/DOUT)
The DIN1 pin has a built-in amplifier, and can receive signals with an amplitude of about 400 mVp-p (coaxial input).
The DIN2 pin is only for use with optical modules.
Note that although the data input pins are controlled by the microprocessor, DIN1 can be selected when a
microprocessor is not used. The microprocessor interface pins must be tied low in such applications.
The E/DOUT normally outputs channel status information. However, it can be set to output either the input bi-phase
data or the validity flag by command codes from the microprocessor.
2. PLL (R, VIN, VCO, AVOCK)
This circuit includes a built-in VCO and supports sampling frequencies of 32, 44.1, and 48 kHz.
The resistor connected to R functions as both the VCO gain control and as temperature compensation. The VIN pin
sets the VCO free-running frequency.
The PLL circuit can be reset within a fixed period when it operates incorrectly, for example, if a lock pull-in failure
occurs, by inputting an asynchronous, continuously operating clock signal to the AVOCK pin.
3. Clock Settings and Output (FS128, BCK, LRCK, DATAOUT, CKSEL, CKOUT)
A 128fs clock signal is output from the FS128 pin. Figure 1 shows the output timing for the BCK, LRCK, and
DATAOUT pins.
The CKOUT clock output is set by the CKSEL pin as listed in the table below.
The microprocessor interface format is also set by CKSEL as listed in the table below.
No. 5237-8/16
LC8905V
CKSEL CKOUT
L 384fs clock output
H 512fs clock output
CKSEL Microprocessor interface
L Figure 2
H Figure 3
Figure 1 Data Output Timing
No. 5237-9/16
LC8905V
Figure 2 Microprocessor Interface Timing 1
No. 5237-10/16
LC8905V
Figure 3 Microprocessor Interface Timing 2
No. 5237-11/16
LC8905V
Microprocessor Interface (SCLK/CL, XLAT/CE, SWDT/DI, SRDT/DO, DQSY/LD)
1. Data input and output addresses are allocated as follows:
2. The input command codes control the following settings:
• System stop
• Data input pin settings
• Input bi-phase data output selection
• Validity flag output selection
• Audio data output format setting
DI1: Stops VCO operation and thus stops the system.
DI2: Selects which input data to demodulate.
DI3 and DI4: Select the E/DOUT pin output.
DI5 and DI6: Set the audio data output format.
All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used.
No. 5237-12/16
LC8905V
Data input or output
Figure 2: Microprocessor Interface Timing 1 Figure 3: Microprocessor Interface Timing 2
B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3
Data input F7 1 1 1 0 1 1 1 1 EA 0 1 0 1 0 1 1 1
C bit output F8 0 0 0 1 1 1 1 1 E9 1 0 0 1 0 1 1 1
Subcode Q, ID output F9 1 0 0 1 1 1 1 1 E8 0 0 0 1 0 1 1 1
DI1 L H
System Operating Stopped
DI2 L H
Data demodulation input DIN1 DIN2
DI3 L H
DI4 L H L H
E/DOUT
Emphasis Validity DIN1 input DIN2 input
data output flag output data output data output
DI5 L H
DI6 L H L H
16-bit right- 20-bit right- 20-bit right- 20-bit left-
DATAOUT justified justified justified justified
MSB first LSB first MSB first MSB first
3. The following output settings can be controlled:
• Channel status (C bit) output
• Subcode Q data output
• Status ID and shortening ID detection for DAT that use subcodes
C bit output
• This function presumes that this IC will be used in consumer mode and thus only handles the first 32 bits.
• The flag is fixed at the high level (although there is no flag in the type 1 microprocessor interface timing), and the
data format is LSB first.
• Error and update checking is not applied to the data.
• The internal shift register is reset if a PLL lock error occurs.
• An interval of at least 6 msec must be provided between consecutive data readout operations.
Subcode Q output
• Subcode Q can be read out after the fall of the DQSY/LD signal. Also note that the data is updated every time this
signal falls. However, this signal will not be output (fall) unless 96 bits of subcode Q data (include the CRC check
bits) is input.
• The flag outputs a high when the CRC check passes, and low if the CRC check fails.
• The bit order is LSB first within each byte of the 80 bits of subcode Q data.
ID detection
• The start ID and shortening ID are only detected when the DAT category code (1100000L) is received.
• These IDs are detected as follows:
— A low pulse is output from DQSY/LD if a start ID (R0) or a shortening ID (L1) is detected following a sync
signal (L0).
— After this signal, data can be read out from SRDT/DO by inputting the same address value as that used for
subcode Q data to SWDT/DI.
Figure 4 User Data for DAT that Use Subcodes
• The table below shows the relationship between the sync signal (L0), the start ID (R0), the shortening ID (L1), and
the data output.
• Output pins
The output scheme used for SRDT/DO differs depending on the microprocessor interface format selected by
CKSEL.
No. 5237-13/16
LC8905V
(L0): SYNC H H
(R
0
): Start ID H L
(L
1
): Shortening ID L H
Flags + 80 data bits all H all L
Detected ID Start ID Shortening ID
CKSEL Format SRDT/DO
L Figure 2 Open-drain output
H Figure 3 Three-state output
Error (ERROR)
The ERROR pin goes high if there is an error in the input data or if the PLL is unlocked. It holds the high level for about
200 to 300 msec after data demodulation returns to normal and then goes low. The table below lists the data processing
when an error has occurred.
System Reset (XMODE)
Normal system operation is started by setting XMODE high after the power supply has risen above at least 4.5 V. If
XMODE is set low, the VCO free-running oscillator clock is output from CKOUT.
Setting XMODE low once again after power on resets the system.
No. 5237-14/16
LC8905V
Type of error DATAOUT C bit Sub Q ID E/DOUT
Up to 8 consecutive parity errors Previous data value Output Output Output Output
Over 8 consecutive parity errors L Output Output Output Output
PLL lock error L L L L L
Sample Application Circuit
No. 5237-15/16
LC8905V
No. 5237-16/16
LC8905V
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
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