Ordering number : ENN*6843
LC876694B/78B/62B
8-Bit Single-Chip Microcontroller
Preliminary
Overview
The LC876694B/LC876678B/LC876662B are 8 bit single chip microcontrollers with the following on-chip functional
blocks :
- CPU: operable at a minimum bus cycle time of 100ns
- On-chip ROM Maximum Capacity : LC876694B 96K bytes
LC876678B 80K bytes
LC876662B 64K bytes
- On-chip RAM: 2048 bytes
- VFD automatic display controller / driver
- 16 bit timer / counter (can be divided into two 8 bit timers)
- 16 bit timer / PWM (can be divided into two 8 bit timers)
- timer for use as date / time clock
- High speed clock counter
- System clock divider function
- synchronous serial I/O port (with automatic block transmit / receive function)
- asynchronous / synchronous serial I/O port
- 12-channel × 8-bit AD converter
- Weak signal detector
- 15-sour ce 10-vec tored in terrupt syst em
All of the above functions are fabricated on a single chip.
Features
(1) Read-Only Memory (ROM): LC876694B 98304 × 8 bits
LC876678B 81920 × 8 bits
LC876662B 65536
(2) Random Access Memory (RAM): LC876694B/78B/62B 2048 × 9 bits
(3) Minimum Bus Cycle Time: 100ns (10MHz)
Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time: 300ns (10MHz)
8 bits
×
CMOS IC
Ver.1.01
51000
11901 RM (IM) SK No.6843-1/23
LC876694B/78B/62B
(5) Ports
- Input/output ports
Data direction programmable for each bit individually : 20 (P1n, P70 to P73, P8n)
- 15V withstand input/output ports
Data direction programmable in nibble units : 8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
Data direction programmable for each bit individually : 8 (P3n)
- Input ports : 2 (XT1,XT2)
- VFD output ports
Large current outputs for digits : 9 (S0 / T0 to S8 / T8)
Large current outputs for digits / segments : 7 (S9 / T9 to S15 / T15)
digit / segment outputs : 8 (S16 to S23)
segment outputs : 28 (S24 to S51)
Other functions
Input/output ports : 12(PFn, PG0 to 3)
Input ports : 24 (PCn, PDn, PEn)
- Oscillator pins : 2 (CF1,CF2)
- Reset pin : 1 (RES#)
- Power supply : 6 (VSS1 to 2, VDD1 to4)
- VFD power supply : 1 (VP)
(6) VFD automatic display controller
- Programmable segment/digit output pattern
Output can be switched between digit/segment waveform output (pins 9 to 24 can be used for output of digit
waveforms).
parallel-drive available for large current VFD.
- 16-step dimmer function available
(7) Weak signal detection (MIC signals etc)
- Counts pulses with width greater than a preset value
- 2 bit counter
(8) Timers
- Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
Counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
- Timer 1: PWM / 16 bit timer toggle output
Mode 0: 2 channel 8 bit timer (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer (with toggle output) Toggle output also possible using lower order 8 bits.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output.
- Base Timer
1) The clock signal can be selected from any of the following :
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts can be selected to occur at one of five different times.
(9) High speed clock counter
1) Capable of counting maximum : 20MHz clock (Using main clock 10MHz)
2) Real time output
No.6843-2/23
LC876694B/78B/62B
(10) Serial-interface
- SIO 0: 8 bit synchronous serial Interface
1) LSB first / MSB first function availa ble
2) Internal 8 bit baud-rate generator (maximum transmit clock period 4 / 3 Tcyc)
3) Continuous automatic data communication (1-256 bits)
- SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 Tcyc)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048Tcyc)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 Tcyc)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
(11) AD converter
-8 bits × 12 channels
(12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
-Noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 Tcyc)
(13) Watchdog timer
- The watching timer period is set using an external RC.
- Watchdog timer can produce interrupt, system reset
(14) Interrupts: 15-source, 10-vectored interrupts
1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower priority interrupt request is refused.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
(15) Subroutine stack levels: 1024 levels max. Stack is located in RAM.
(16) Multiplication and division
- 16 bit × 8 bit (executed in 5 cycles)
- 24 bit × 16 bit (12 cycles)
- 16 bit ÷ 8 bit (8 cycles)
- 24 bit ÷ 16 bit (12 cycles)
(17) Oscillation circuits
- On-chip RC oscillation circuit for system clock use.
- On-chip CF oscillation circuit for system clock use. (R
- On-chip Crystal oscillation circuit low speed system clock use. (Rd, R
built in)
f
external)
f
(18) System clock divider function
- Able to reduce current consumption
Available minimum instruction cycle time: 300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs.
(Using 10MHz main clock)
No.6843-3/23
LC876694B/78B/62B
(19) Standby function
- HALT mode
HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still
operate but VFD display and some serial transfer operations stop.
1) Oscillation circuits are not stopped automatically.
2) Release occurs on system reset or by interrupt.
-HOLD mode
HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are
stopped.
1)CF, RCand crystal oscillation circuits stop automatically.
2) Release occurs on any of the following conditions.
(1) input to the reset pin goes low
(2) a specified level is input at least one of INT0, INT1, INT2
(3) an interrupt condition arises at port 0
-X’tal HOLD made
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF and RC oscillation circuits stop automatically.
2) Crystal oscillator is maintained in its state at HOLD mode inception.
3) Release occurs on any an any of the following conditions
(1) input to the reset pin goes low
(2) a specified level is input to at least one of INT0, INT1, INT2
(3) an interrupt condition arises at port 0
(4) an interrupt condition arises at the base-timer
(20) Factory shipment
-delivery form QIP100E
(21) Development tools
- Evaluation chip: LC876095
- Emulator: EVA62S + ECB876600 (Evaluation chip board) + SUB876500 + POD100QFP
- Flash ROM version: LC87F66C8A
No.6843-4/23
Pin Assignment
Z
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
LC876694B/78B/62B
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
VDD4
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
8079787776757473727170696867666564636261605958575655545352
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9
P30
P31
P32
P33
P16/T1PWML
P17/T1PWMH/BU
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P34
P35
P36
P37
RES
CF1
CF2
VSS1
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
XT1/AN10
XT2/AN11
P86/AN6
S24/PD0
25
P87/AN7/MICIN
S23/PC7
26
P70/INT0/T0LCP/AN8
S22/PC6
27
P71/INT1/T0HCP/AN9
S21/PC5
28
P72/INT2/T0IN/NKIN
S20/PC4
29
P73/INT3/T0IN
VP
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
S0/T0
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VDD3
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
SANYO: QIP100E
No.6843-5/23
System Bl ock Diagram
Interrupt Control
LC876694B/78B/62B
IR PLA
SIO0
SIO1
Timer 0
(High speed clock
Timer 1
counter)
Stand-by C ontr ol
CF
RC
X’tal
Clock
Generator
Bus Interface
Port 0
Port 1
Port 3
Port 7
ROM
PC
ACC
B Register
C Register
ALU
Base Timer
VFD Controller
INT0-3
Noise Rejection Filter
Port 8
ADC
Weak Signa Detector
PSW
RAR
RAM
Stack Pointer
Watch Do g Timer
No.6843-6/23
LC876694B/78B/62B
Pin Assignment
Pin name I/O Function Option
VSS1
VSS2
VDD1
VDD2
VDD3
VDD4
VP - • Power supply (-) No
PORT0
P00 to P07
PORT1
P10 to P17
PORT3
P30 to P33
PORT7
P70 to P73
- • Power supply (-) No
- • Power supply (+) No
I/O • 8bit input/output port
• data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
• 15V withstand at N-channel open drain output
I/O • 8bit input/output port
• data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit
• Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
I/O • 8bit Input/output port
• Data direction can b e specified for each bit
• Use of pull-up resistor can be specified for each bit
• 15V withstand at N-channel open drain output
• 4bit Input/output port
I/O
• Data direction can b e specified for each bit
• Use of pull-up resistor can be specified for each bit
• Other func tions
P70: INT0 input/HOLD release input/Timer0L capture Input/output for watc h dog timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/High
speed clock counter input
P73: INT3 input(noise rejection filter attached input)/timer 0 event input/Timer 0H
capture input
AD input port: AN8(P70), AN9(P71)
The following types of interrupt detection are possible:
Yes
Yes
Yes
No
INT0
INT1
INT2
INT3
Rising Falling Rising/
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
falling
No
No
Yes
Yes
H level L level
Yes
Yes
No
No
Yes
Yes
No
No
No.6843-7/23
LC876694B/78B/62B
Pin name I/O Function description Option
PORT8
P80 to P87
S0/T0 to
S6/T6
S7/T7 to
S8/T8
S9/T9 to
S15/T15
S16 to S23 I/O • Output for VFD display controller segment/digit
S24 to S31 I/O • Output for VFD display controller segment
S32 to S39
S40 to S47
S48 to S51
RES
XT1 I • Input for 32.768kHz crystal oscillation
XT2 I/O • Output for 32.768kHz crystal oscillation
CF1 I Input terminal for ceramic oscillator No
CF2 O Output terminal for ceramic oscillator No
I/O • 8bit Input/output port
• Input/out put can be specified in a bit unit
• Other func tions:
AD input port: AN0 to AN7
Weak signal detector input port: MICIN(P87)
O • Large current output for VFD display controller digit (can be used for segment) Yes
O • Large current output for VFD display control ler digit (can be used for segment) No
O • Large current output for VFD display controller segment/digit No
• Other functions:
High voltage input port: PC0 to PC7
• Other func tions:
High voltage input port: PD0 to PD7
I/O • Output for VFD display controller segment
• Other func tions
High voltage input port: PE0 to PE7
I/O • Output for VFD display controller segment
• Other func tions:
High voltage input/output port: PF0 to PF7
I/O • Output for VFD display controller segment
• Other func tions:
High voltage input/output port: PG0 to PG3
I Reset terminal No
• Other func tions:
General purpose input port
When not in use, connect to VDD1.
AD input port: AN10
• Other func tions:
General purpose input port
When not in use, set to oscillation mode and leave open circuit.
AD input port: AN11
No
No
No
Yes
Yes
No
No
No
No.6843-8/23
LC876694B/78B/62B
Port Output Configuration
Output configuration and pull-up/pull-down resistor options are shown in the following table.
Input /output is possible even when port is set to output mode.
Terminal Option applies to: Options Output Format Pull-up resistor
1 CMOS Programmable
(Note 1)
2 15 voltage Nch-open drain None 1 CMOS Programmable - P10 to P17 each bit
2 Nch-open drain Programmable 1 CMOS Programmable - P30 to P37 each bit
2 15V Nch-open drain None P70 - None Nch-open drain Programmable P71 to P73 - None CMOS Programmable P80 to P87 - None Nch-open drain None -
1 High voltage Pch-open drain - Fixed S0/T0 to S6/T6 each bit
2 High voltage Pch-open drain - None
Pull-down
resistor
- P00 to P07 1 bit units
S7/T7 to S15/T15
S16 to S31
S48 to S51 - None High voltage Pch-open drain - None
XT1 - None Input only None XT2 - None Output for 32.768kHz crystal
- None High voltage Pch-open drain - fixed
1 High voltage Pch-open drain - Fixed S32 to S47 each bit
2 High voltage Pch-open drain - None
None -
oscillation
Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07).
* Note 1: Connect as follows to reduce noise on VDD and increase the back-up time.
VSS1, and VSS2 must be connected together and grounded.
*Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the
VDD2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore,
when the VDD2 is not b acked up and the po rt latc h is “H” level, the port l evel is unstable in the HO LD mode, a nd
the back up time becomes shorter because the through current runs from VDD to GND in the input buffer.
If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD
mode so that the port level becomes “L” level and unnecessary current consumption is prevented.
Power
Supply
Back-up capacitors *2
LSI
VDD1
VDD2
VDD3
VDD4
VFD
Powers
VSS2 VSS1
No.6843-9/23
LC876694B/78B/62B
1. Absolute Maximum Ratings at Ta=25°C and VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Supply voltage VDDMAX VDD1,VDD2,
VDD3,VDD4
Input voltage
VI(1)
XT1,XT2,CF1,
RES
VDD1=VDD2=
VDD3=VDD4
-0.3 VDD+0.3
VI(2) VP VDD-45 VDD+0.3
Output voltage VO(1) S0/T0 to S15/T15 VDD-45 VDD+0.3
Input/Output
voltage
VIO(1) •Port 0: CMOS output
option
-0.3 VDD+0.3
•Port 1
•Port 3: CMOS output
option
•Port 7
•Port 8
VIO(2) •Port 0 open drain
-0.3 15
•Port 3 open drain
VIO(3) S16 to S51 VDD-45 VDD+0.3
High
level
output
current
Peak
output
current
IOPH(1) Port 0, 1, 3 •CMOS output
selected
•Current at each pin
IOPH(2) Port71,72,73 Current at each pin -3
IOPH(3) S0/T0 to S15/T15 Current at each pin -30
IOPH(4) S16 to S51 Current at each pin -15
Total
output
current
Low
level
output
Peak
output
current
current
Total
output
current
Maximum power
IOAH(1)
Σ
IOAH(2)
Σ
IOAH(3)
Σ
IOAH(4)
Σ
IOAH(5)
Σ
IOAH(6)
Σ
IOAH(7)
Σ
IOPL(1) Port 02,03 For each pin 30
IOPL(2) •Port 00,01,04 to 07
IOPL(3) Port 7, 8 For each pin 5
IOAL(1)
Σ
IOAL(2)
Σ
IOAL(3)
Σ
Pdmax QIP100E
Port 0 Total of all pins -30
Port 1,3 Total of all pins -30
Port 7 Total of all pins -5
S0/T0 to S15/T15 Total of all pins -65
S16 to S27 Total of all pins -60
S28 to S39 Total of all pins -60
S40 to S51 Total of all pins -60
For each pin 20
•Port 1,3
Port 00,01,02,03 For each pin 60
•Port 04,05,06,07
For each pin 50
•Port 1,3
Ports 7,8 For each pin 20
Ta = -30 to+70°C
dissipation
Operating
Topr -30 70
temperature
range
Storage
Tstg -55 125
temperature
range
Ratings
[V]
VDD
min. typ. max.
-0.3 +7.0
-10
mW
unit
V
mA
C
°
No.6843-10/23
LC876694B/78B/62B
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Operating
supply voltage
VDD(1) VDD1=VDD2=VDD3
=VDD4
0.294µs ≤ Tcyc
200µs
≤
range
Hold voltage VHD VDD1 RAM and the
register data are
kept in HOLD
mode.
Pull-down
VP VP 4.5 to 6.0 -35 VDD
voltage
Input high
voltage
VIH(1) •Port 0,3: CMOS output
option
•Port 8
VIH(2) Port 0,3: N-ch open drain
Output disable 4.5 to 6.0 0.3VDD
Output disable 4.5 to 6.0 0.3VDD
output
VIH(3) •Port 1
•Port71,72,73
Output disable 4.5 to 6.0 0.3VDD
•P70 port input/interrupt
VIH(4) S16 to S51 Output P-channel
Tr. OFF
VIH(5) P70 Weak signal input Output disable 4.5 to 6.0 0.75VDD VDD
VIH(6) Port 70
Output disable 4.5 to 6.0 0.9VDD VDD
Watchdog timer
Input low
voltage
VIH(7)
XT1, XT2, CF1,
RES
VIL(1) •Port 0,3: CMOS output
option
4.5 to 6.0 0.75VDD VDD
Output disable 4.5 to 6.0 VSS 0.15VDD
•Port 8
VIL(2) Port 0,3: N-ch open drain
Output disable 4.5 to 6.0 VSS 0.15VDD
output
VIL(3) •Port 1
Output disable 4.5 to 6.0 VSS 0.1VDD
•Port 71,72, 73
•P70 port input/interrupt
VIL(4) S16 to S51 Output P-channel
Tr. OFF
VIL(5) Port 87 weak signal input Output disabled 4.5 to 6.0 VSS 0.25VDD
VIL(6) Port 70
Output disabled 4.5 to 6.0 VSS 0.8VDD
Watchdog timer
Operation
VIL(7)
CYC
t
XT1,XT2,CF1,
4.5 to 6.0 0.294 200
RES
4.5 to 6.0 VSS 0.25VDD
cycle time
External system
clock
frequency
fEXCF(1) CF1
•CF2 open circuit
•system clock
divider set to 1/1
•external clock
DUTY = 50±50%
•CF2 open circuit
•system clock
divider set to 1/2
Ratings
[V]
VDD
4.5 6.0
2.0 6.0
4.5 to 6.0 0.3VDD
4.5 to 6.0 -35 0.2VDD
4.5 to 6.0 0.1 10
4.5 to 6.0 0.2 20
Continued
min. typ. max.
VDD
+0.7
13.5
+0.7
VDD
+0.7
VDD
+1.0
+0.4
+0.4
+0.4
-1.0
unit
V
s
µ
MHz
No.6843-11/23
LC876694B/78B/62B
Parameter Symbol Pins Conditions
Oscillation
stabilizing
time period
(Note 1)
FmCF(1) CF1, CF2 10MHz ceramic resonator
FmCF(2) CF1, CF2 4MHz ceramic resonator
FmRC
FsX’tal XT1, XT2 32.768kHz crystal resonator
RC oscillation 4.5 to 6.0 0.3 1.0 2.0
oscillation
Refer to figure 1
oscillation
Refer to figure 1
oscillation
Refer to figure 2
(Note 1) The oscillation constant is shown in table 1 and table 2.
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 10
4.5 to 6.0 4
4.5 to 6.0 32.768
unit
No.6843-12/23
LC876694B/78B/62B
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Input high
current
Input low
current
Output high
voltage
Output low
voltage
Pull-up
resistor
IIH(1) Ports 0,3: N-ch open
IIH(2) Port 0,1,3,7,8 •Output disabled
IIH(3) S16 to S51 without
IIH(4)
IIH(5) XT1,XT2 When configured as an input
IIH(6) CF1 VIN=VDD 4.5 to 6.0 15
IIH(7) P87/AN7/MICIN
IIL(1) Port 0,1,3,7,8 •Output disabled
IIL(2)
IIL(3) XT1,XT2 When configured as an input
IIL(4) CF1 VIN=VSS 4.5 to 6.0 -15
IIL(5) P87/AN7/MICIN
VOH(1) IOH=-1.0mA 4.5 to 6.0 VDD-1
VOH(2)
VOH(3) Port 7 IOH=-0.4mA 4.5 to 6.0 VDD-1
VOH(4) IOH=-20.0mA 4.5 to 6.0 VDD-1.8
VOH(5)
VOH(6) IOH=-5.0mA 4.5 to 6.0 VDD-1.8
VOH(7)
VOL(1) Port 02, 03 IOL=30mA 4.5 to 6.0 1.5
VOL(2) IOL=10mA 4.5 to 6.0 1.5
VOL(3)
Rpu Port 0,1,3,7 VOH=0.9VDD 4.5 to 6.0 15 40 70
drain output
pull-down resister
(Por t C,D,E ,F,G)
RES
weak signal input
RES
weak signal input
Port 0,1,3: CMOS
output option
S0/T0–S15/T15
S2+ to S51
Port 0,1,3
•Output disabled
•VIN=13.5V
(including OFF state leak
current of the output Tr.)
•Pull-up resister OFF.
•VIN=VDD
(including OFF state leak
current of the output Tr.)
When configured as an input
port
VIN=VDD
VIN=VDD 4.5 to 6.0 1
port
VIN=VDD
VIN=VBIS+0.5V
(VBIS : Bias voltage)
•VIN=VSS
(including OFF state leak
current of the output Tr.)
VIN=VSS 4.5 to 6.0 -1
port
VIN=VSS
VIN=VBIS-0.5V
(VBIS : Bias voltage)
IOH=-0.1mA 4.5 to 6.0 VDD-0.5
IOH=-1.0mA
IOH at any single pin is not
over 1mA.
IOH=-1.0mA
IOH at any single pin is not
over 1mA.
IOL=1.6mA 4.5 to 6.0 0.4
Continued
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 5
4.5 to 6.0 1
4.5 to 6.0 60
4.5 to 6.0 1
4.5 to 6.0 4.2 8.5 15
4.5 to 6.0 -1
4.5 to 6.0 -1
4.5 to 6.0 -15 - 8.5 -4.2
4.5 to 6.0 VDD-1
4.5 to 6.0 VDD-1
unit
A
µ
V
kΩ
No.6843-13/23
LC876694B/78B/62B
Parameter Symbol Pins Conditions
leak current
Resistance of
the low level
hold Tr.
High voltage
pull-down
resistor
Hysteresis
voltage
Pin
capacitance
Input
sensitivity
IOFF(1) •Output P-ch Tr. OFF
IOFF(2)
Rinpd S16 to S51 •Output P-ch Tr. OFF
Rpd S0/T0 to S15/T15,
VHIS(1) •Port 1,7
VHIS(2) Port 87 weak signal
CP All pins •All other terminals
Vsen Port 87 weak signal
S0/T0 to S15/T15,
S16 to S51 without
pull-down resistor
S16 to S51 with
pull-down resistor
•
RES
input
input
•VOUT=VSS
•Output P-ch Tr. OFF
•VOUT=VDD-40V
•Output P-ch Tr. OFF
•VOUT=3V
•Vp=-30V
4.5 to 6.0 0.1VDD
4.5 to 6.0 0.1VDD
connected to VSS.
•f=1MHz
•Ta=25°C
4.5 to 6.0 0.12VDD Vpp
Ratings
VDD[V] min. typ. Max.
4.5 to 6.0 -1 Output off-
4.5 to 6.0 -30
4.5 to 6.0 200
5.0 60 100 200
4.5 to 6.0 10 pF
unit
µ
kΩ
V
A
No.6843-14/23
LC876694B/78B/62B
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Cycle Time tSCK(1) 4/3
SCK0(P12) Refer to figure 6 4.5 to 6.0
Ratings
VDD[V] min. typ. max.
unit
CYC
t
pulse width
pulse width
Input clock
Cycle Time tSCK(2)
Low Level
pulse width
High Level
pulse width
Cycle Time tSCK(3)
Serial clock
pulse width
pulse width
Output clock
Cycle Time tSCK(4)
Low Level
pulse width
High Level
pulse width
Data set-up time
Data hold time t
Serial input
Output delay
time
Serial output
tSCKL(1)
tSCKLA(1)
tSCKH(1)
tSCKHA(1)
tSCKL(2)
tSCKH(2)
tSCKL(3)
tSCKLA(2)
tSCKH(3)
tSCKHA(2)
tSCKL(4)
tSCKH(4)
sDI
t
0.03
hDI
tdDO SO0(P12),
SCK1(P15) Refer to figure 6 4.5 to 6.0
SCK0(P12) •CMOS output option
SCK1(P15) •CMOS output option
SI0(P10),
SI1(P13),
SB0(P11),
SB1(P14)
SO1(P15),
SB0(011),
SB1(P14)
•Refer to figure 6
•Refer to figure 6
•Measured with resp ect
to SI0CLK leading
edge.
•Refer to figure 6
•Measured with resp ect
to SI0CLK trailing
edge.
•When port is open
drain: Time delay
from SI0CLK trailing
edge to the SO data
change.
•Refer to figure 6
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0 1/3
2/3 Low Level
2/3
2/3 High Level
3
2
1
1
4/3
1/2 Low Level
3/4
1/2 High Level
2
2 tCYC
1/2
1/2
0.03
tSCK
tSCK
µ
tCYC
+0.05
s
No.6843-15/23
LC876694B/78B/62B
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIH(5)
tPIL(5)
tPIH(6)
tPIL(6)
tPIL(7)
INT0(P70),
INT1(P71),
INT2(P72)
INT3(P73)
(Noise rejection ratio set
to 1/1.)
INT3(P73)
(Noise rejection ratio set
to 1/32.)
INT3(P73)
(Noise rejection ratio set
to 1/128.)
MICIN(P87) •Weak signal detection
NKIN(P72) •High speed clock
RES
•Interrupt accept able
•Events to timer 0 can
be input.
•Interrupt accept able
•Events to timer 0 can
be input.
•Interrupt accept able
•Events to timer 0 can
be input.
•Interrupt accept able
•Events to timer 0 can
be input.
counter enabl ed
counter countable
•Reset possible 4.5 to 6.0 200
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 1
4.5 to 6.0 2
4.5 to 6.0 64
4.5 to 6.0 256
4.5 to 6.0 1
4.5 to 6.0 1/12
unit
CYC
t
µ
High/low level
s
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Resolution N 4.5 to 6.0 8 bit
Absolute precisi on ET (Note2) 4.5 to 6.0
Conversion time TCAD
Analog input
voltage range
Analog port input
current
VAIN 4.5 to 6.0 VSS VDD V
IAINH VAIN=VDD 4.5 to 6.0 1
IAINL
AN0(P80) to
AN7(P87)
AN8(P70),
AN9(P71)
AN10(XT1),
AN11(XT2)
AD conversion time
= 32 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time
= 64 × tCYC
(ADCR2=1)
(Note 3)
VAIN=VSS 4.5 to 6.0 -1
Ratings
VDD[V] min. typ. max.
4.5 to 6.0
15.62
(tCYC=
0.488µs)
18.82
(tCYC=
0.294µs)
±
97.92
(tCYC=
3.06µs)
97.92
(tCYC=
1.53µs)
1.5
unit
LSB
s
µ
A
µ
(Note 2) A bsolute precision not including quanti zin g error (±1/2 LSB).
(Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register.
No.6843-16/23
LC876694B/78B/62B
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 4)
IDDOP(1) •FmCF=10MHz for
IDDOP(2) •CF1=20MHz for
IDDOP(3) •FmCF=4MHz Ceramic
IDDOP(4) •FmCF=0Hz (No
VDD1=
VDD2=
VDD3=
VDD4
Ceramic resonator
oscillation
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock: CF
oscillation
•Internal RC oscillation
stopped.
•Divider set to 1/1
external clock
•FsX’tal=32.768kHz f or
crystal oscillation
vSystem clock: CF
oscillation
•Internal RC oscillation
stopped.
•Divider set to 1/2
resonator oscillation
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock: CF
oscillation
•Internal RC oscillation
stopped.
•Divider set to 1/1
oscillation)
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock: RC
oscillation
•Divider set to 1/2
Ratings
VDD[V] min. typ. max
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
unit
mA
IDDOP(5)
•FmCF=0Hz (No
oscillation)
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock:
32.768kHz
•Internal RC oscillation
stopped.
•Divider set to 1/2
Continued
4.5 to 6.0
A
µ
No.6843-17/23
LC876694B/78B/62B
=
=
=
Parameter Symbol Pins Conditions
Current dissipation
HALT mode
(Note 4)
IDDHALT(1) HALT mode
IDDHALT(2) HALT mode
VDD1
VDD2
VDD3
VDD4
•FmCF=10MHz for
Ceramic resonator
oscillation
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock :
CF oscillation
•Internal RC oscillation
stopped.
•Divider: 1/1
•CF1=20MHz for extern al
clock
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock :
CF oscillation
•Internal RC oscillation
stopped.
•Divider 1/2
Ratings
VDD[V] min. typ. max.
4.5 to 6.0
4.5 to 6.0
unit
mA
IDDHALT(3)
IDDHALT(4) HALT mode
IDDHALT(5) HALT mode
HALT mode
•FmCF=4M Hz for Ceramic
resonator
oscillation
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock :
CF oscillation
•Internal RC oscillation
stopped.
•Divider: 1/2
•FmCF=0Hz
(When oscillation stops.)
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock :
RC oscillation
•Divider: 1/2
•FmCF=0Hz
(When oscillation stops.)
•FsX’tal=32.768kHz f or
crystal oscillation
•System clock : 32.768kHz
•Internal RC oscillation
stopped.
•Divider: 1/2
Continued
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
A
µ
No.6843-18/23
LC876694B/78B/62B
Parameter Symbol Pins Conditions
Current dissipation
HOLD mode
Current dissipation
Date/time clock
HOLD mode
IDDHOLD(1) VDD1 HOLD mode
•CF1=VDD or open
circuit (when using
external clock)
IDDHOLD(2) VDD1 Date/time clock HOLD
mode
•CF1=VDD or open
circuit (when using
external clock)
•FmX’tal=32.768kHz
for crystal oscillation
Ratings
VDD[V] min. typ. max.
4.5 to 6.0
4.5 to 6.0
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
A
µ
No.6843-19/23
LC876694B/78B/62B
Main system clock osci llation circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has pro vided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer
Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Frequency Manufacturer Oscillator
10MHz
4MHz
Circuit parameters
C1 C2 Rd1
Operating
supply
voltage
range
Oscillation
stabilizing time
typ max
Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum
operating voltage. (Refer to Figure4)
Subsystem clock osci lla tion circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has pro vided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer
Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Frequency Manufacturer Oscillator
32.768kHz
Circuit parameters
C3 C4 Rf Rd2
Operating
supply voltage
range
Oscillation
stabilizing time
typ max
Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the
sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4)
(Notes) • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close tothe
oscillation pins as possible with the shortest possible pattern length.
CF2 CF1
Rd1
Rf
XT2 XT1
Rd2
C1
CF
C2
C3
X’tal
C4
Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit
No.6843-20/23
LC876694B/78B/62B
,
,
0.5VDD
Figure 3 AC timing measurement poi n t
Power Supply
RES
Reset time
Internal RC
Resonator oscillation
CF1
CF2
XT1
XT2
tmsCF
tmsXtal
Operation mode
Unfixed
Rese t Instruction execution mode
Reset time and oscillation stable time
HOLD release signal
Without HOLD
Release signal
HOLD release signal VALID
Internal RC
Resonator oscillation
tmsCF
CF1,CF2
tmsXtal
XT1,XT2
Operation mode
HOLD HALT
HOLD release signal and oscillation stable time
Figure 4 Oscillation stablization time
VDD
VDD limit
0V
No.6843-21/23
SIOCLK
DATAIN
DATAOUT
SIOCLK
DATAIN
DATAOUT
SIOCLK
DATAIN
DATAOUT
LC876694B/78B/62B
VDD
RES
R
RES
RES
, R
values such that reset
RES
(Note) Set C
time exceeds 200µs.
RES
C
Figure 5 Reset circuit
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
Data RAM
transmission period
(only SIO0)
tSCK
tSCKL tSCKH
tsDI thDI
tdDO
Data RAM
transmission period
(only SIO0)
tSCKLA tSCKHA
tsDI thDI
tdDO
Figure 6 Serial input / output test condition
No.6843-22/23
memo :
LC876694B/78B/62B
tPIL tPIH
Figure 7 Pulse input timing condition
PS
No.6843-23/23
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