Ordering number : ENN*6838
LC86P7248
8-Bit Single-Chip Microcontroller
with the One-Time Programmable PROM Built in
Preliminary
Overview
The LC86P7248 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC867200 series. This
microcontroller has the function and the pin description of the LC867200 series mask ROM version, and 48K-byte
EPROM.
QIP package are available for shipping as well as LC867200 series. It is suitable to set up first release, prototyping,
developing and testing of set.
Features
(1) Option switching by PROM data
The option function of the LC867200 series can be specified by the PROM data.
LC86P7248 can be checked the functions of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity : 49408 bytes
(3) Internal RAM capacity : 1152 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P7248.
Mask ROM version EPROM capacity RAM capacity
LC867248 49152 bytes 1152 bytes
LC867240 40960 bytes 1152 bytes
LC867232 32768 bytes 1152 bytes
LC867224 24576 bytes 1152 bytes
Programming service
We offers various services at nominal charges. These include ROM writing, ROM reading and package stamping and
screening. Contact local our representative for further information.
CMOS IC
Ver.1.02
72396
D2700 RM (IM) SK No.6838-1/20
LC86P7248
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 1µs to 366µs
(6) Operating temperature : -30°C to +70°C
(7) The pin compatible with the LC867200 series mask ROM devices
(8) Applicable mask ROM version : LC867248/LC867240/LC867232/LC867224
(9) Factory shipment : QIP100E
Notice for use
LC86P7248 is provided for the first release and small shipping of the LC867200 series.
At using, take notice of the followings.
(1) A point of difference LC86P7248 and LC867200 series
Item LC86P7248 LC867248/40/32/24
Operation after reset
releasing
Operating supply
voltage range (VDD)
Power dissipa tion Refer to ‘electrical characteristics’ on the semiconduct or news.
The option is specified until 3ms after
going to a ‘H’ level to the reset
terminal by degrees. The program is
executed from 00H of the program
counter.
4.5V to 6.0V 2.5V to 6.0V
LC86P7248 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data
area. This option configuration can execute all options which LC867200 series have.
• A kind of the option of the LC86P7248
A kind of option Pins, Circuits Contents of the option
Input/output form of
input/output ports
Pull-up MOS Tr. of
input port
Port 0
Port 1
*1
Port 3
*1
Ports 70, 71, 72, 73
*1
1. N-channel open drain output
2. CMOS output *1
1. Pull-up MOS Tr.
2. No Pull-up MOS Tr. *2
1. Input : Programmable pull-up MOS Tr.
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. Input : No Programmable pull-up MOS Tr.
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. No Pull-up MOS Tr.
2. Pull-up MOS Tr.
*1) Specified in a bit.
*2) Specified in nibble unit. Pull-up MOS Tr. is not provided in N-channel open drain output port.
The program is executed from 00H of
the program counter i mmediately after
going to a ‘H’ level to the reset
terminal.
Output : N-channel open drain
Output : N-channel open drain
No.6838-2/20
LC86P7248
(1) Option
The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the
program area by linkage loader “L86K.EXE” .
(2) ROM space
LC86P7248 and LC8672 00 series use 256 bytes that is addresse d on 0FF00H to 0 FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Option
data area
Program area
48K bytes
LC867248 LC867240
Program area
40K bytes
Option
data area
Program area
32K bytes
LC867232
Option
data area
Program area
24K bytes
LC867224
(3) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
No.6838-3/20
LC86P7248
How to use
(1) Specification of option
Programming data for PROM of the LC86P7248 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P7248.
(2) How to program for the PROM
The LC86P7 248 can be prog rammed by PROM programmer with attac hment ; W86EP7248Q
• Recommended EPROM programmer
Productor EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0 to 0FFFFH” and a
jumper (DASEC) must b e set to ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the PROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then PROM programmer displays the error. The error means normally activity of the data security.
It is not a trouble of the PROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK=>PROGRAM=>VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
Data security
W86EP7248Q
Not data security
No.6838-4/20
Pin Assignment
V3/PL6
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
LC86P7248
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
VSS2
VDD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
V2/PL5
V1/PL4
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30
P31
VSS3
VDD3
P32
P33
P34
P35
P00
P01
P02
P03
P04
P05
8079787776757473727170696867666564636261605958575655545352
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
123456789
P06
P07
P10/SO0
P13/SO1
P12/SCK0
P11/SI0/SB0
101112131415161718192021222324252627282930
P16/BUZ
P15/SCK1
P17/PWM0
P70/INT0
P14/SI1/SB1
RES
VSS1
XT1/P74
XT2/P75
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
S0/PA0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
Notes
• The QIP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
• After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E
No.6838-5/20
System Bl ock Diagram
LC86P7248
Interrupt Control
Stand-by C ontr ol
CF
RC
X’tal
Base Timer Bus Interface
SIO0
SIO1
Timer 0
Clock
Generator
Port 1
Port 7
Port 8
IR PLA
EPROM
Control
EPROM (48KB)
PC
ACC
B Register
C Register
ALU
A15-A0
D7-D0
TA
CE
OE
DASEC
Timer 1
Real Time Service
RAM 128 bytes
LCD Display
Controller
SO0 to S7 (PA)
S8 to S13 (PB)
S16 to S23 (PC)
S24 to S31 (PD)
S32 to S39 (PE)
S40 to S47 (PF)
COM0 to -COM3(PL)
Port 3
ADC
INT0 to 3 Noise
Rejection Filter
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog T i mer
No.6838-6/20
LC86P7248
Pin Description
Pin name I/O Function description Option PROM mode
VSS1, 2, 3
*1
VDD1, 2, 3
*1
PORT0
P00 to P07
PORT1
P10 to P17
PORT3
P30 to P35
PORT7
P70
P71 to P73
P74
, P75
Port8
P80 to P87
- Power pin (–) - -
- Power pin (+) - -
I/O • 8-bit input/output port
Input/output in nibble units
• Input for port 0 interrupt
• Input for HOLD release
I/O • 8-bit input/output port
Input/output can be specified in bit unit
• Other pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus input/output
P12 : SIO0 clock input/output
P13 : SIO1 data output
P14 : SIO1 data input/bus input/output
P15 : SIO1 clock input/output
P16 : Buzzer output
P17 : Timer1 output (PWM output)
I/O • 6-bit input/output port
• Input/output can be specified in bit unit
• 6-bit input port
• Other pin functions
I/O
P70 : INT0 input/HOLD release input/
N-ch Tr. output for watchdog timer
I
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
• Interrupt recei ved form, vector address
rising falling rising
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
I
P74
: XT1 terminal for crystal oscillation
P75 : XT2 terminal for crystal oscillation
I • 8-bit input port
• Other func tion
AD input port (8 port pins)
falling
&
high
level
• Pull-up resistor :
Provided/Not provided
(specified in nibble units)
• Output form (P00 – P07) :
CMOS/N-channel open drain
(specified in a bit)
• Output form :
CMOS/N-channel open drain
(specified in a bit)
• Output form :
CMOS/N-channel open drain
(specified in a bit)
Pull-up resistor :
Provided/Not provided
(specified in a bit)
(P70, P71, P72, P73)
*
, P75 don’t have the pull-up
P74
resistor option.
low
vector
level
- -
-
Data line
D0 to D7
-
Power for
programming
PROM control
signals
DASEC (*2)
(*3)
OE
(*4)
CE
No.6838-7/20
LC86P7248
Pin name I/O Function description Option PROM mode
Port A
(S0/PA0 to
S7/PA7)
Port B
(S8/PB0 to
S15/PB7)
Port C
(S16/PC0 to
S23/PC7)
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
- Address input
A0 to A7
- Address input
A8 to A13
- PROM control
signal input
• TA (*5)
Address input
• A14, A15
Port D
(S24/PD0 to
S31/PD7)
Port E
(S32/PE0 to
S39/PE7)
Port F
(S40/PF0 to
S47/PF7)
Port L
(COM0/PL0 to
COM3/PL3)
V1/PL4 –
V3/PL6
RES
P74
XT1/
I/O • Segment output terminal for LCD display
- -
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
- -
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
- -
• Can be used as a general input/output
port
I/O • Common output terminal for LCD display
- -
• Can be used as a general input port
I • Bias power terminal for LCD drive
- -
• Can be used as a general input port
I Reset pin - I • Input pin for 32.768kHz crystal
oscillation
- -
In case of non use, connect to VDD.
• Other func tion
A general input port
XT2/P75 O
• Output pin for 32.768kHz crystal
oscillation
In case of non use, should be left
unconnected
• Other func tion
(I)
P74
- -
A general input port P75
CF1 I Input pin for ceramic resonator
- -
oscillation
CF2 O Output pin for ceramic resonator
- -
oscillation
* All of port options can be specified in bit unit except the pull-up resistor of port 0.
[Notes] • The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other.
• The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other.
*1 Connect like the following figure to reduce noise into a VDD terminals.
*2 Memory select input for data security
*3 Output enable input
*4 Chip enable input
*5 TA ! PROM control signal input
Power
Supply
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.6838-8/20
LC86P7248
V
1. Absolute Maximum Ratings at Ta=25°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Supply voltage VDDMAX VDD1, VDD2
LCD display
voltage
Input voltage VI •Ports 71, 72, 73
Input/output
voltage
High
level
output
current
Low
level
output
current
Maximum
power
dissipation
Operating
temperature
range
Storage
temperature
range
output
current
Total
output
current
Peak
output
current
Total
output
current
VLCD V1/PL6, V2/PL5
VIO •Port 0, 1, 3
IOPH(1) Ports 0, 1, 3 -4 Peak
IOPH(2) Ports A,B,C,D,E,F
IOAH(1)
Σ
IOAH(2)
Σ
IOAH(3)
Σ
vIOAH(4) Ports S26 to S47 Total all pins -25
IOPL(1) Ports 0, 1, 3 At each pins 20
IOPL(2) Ports A,B,C,D,E,F At each pins 20
IOPL(3) Port 70 At each pins 15
IOAL(1)
Σ
IOAL(2)
Σ
IOAL(3)
Σ
IOAL(4)
Σ
IOAL(5)
Σ
Pdmax QIP100E
Topr -30 +70
Tstg -55 +125
VDD3
V3/PL4
•Ports
74 , 75
•Port 8, Port L
RES
•
•Port 70
•Ports A,B,C,D,E,F
Ports 0, 1, 32, 33,
34, 35
Ports 30, 31 Total all pins -4
Ports S0 to S25 Total all pins -25
Ports 0, 1, 32, 33,
34, 35
Ports 30, 31 Total all pins 20
Ports S0 to S25 Total all pins 39
Ports S26 to S47 Total all pins 33
Port 70 Total all pins 10
VDD1=VDD2=
VDD3
VDD1=VDD2=
VDD3
-0.3 VDD+0.3
-0.3 VDD+0.3
•CMOS output
•At each pins
Total all pins -38
Total all pins 50
Ta=-30 to +70°C
Ratings
[V]
DD
min. typ. max.
-0.3 +7.0
-0.3 VDD
-4
515 mW
unit
V
mA
C
°
Notes
• The QIP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
• After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6838-9/20
LC86P7248
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Operating
supply voltage
range
Hold voltage VHD VDD1=VDD2=
VDD(1)
VDD(2)
VDD1=VDD2=
VDD3
VDD3
0.98µs ≤ t
≤
3.9µs ≤ t
≤
CYC
400µs
CYC
400µs
RAMs and the
registers hold vo ltage
at HOLD mode.
Input high
VIH(1) Port 0 Output disable 4.5 to 6.0 0.4VDD
voltage
VIH(2) •Ports 1, 3
Output disable 4.5 to 6.0 0.75VDD VDD
•Ports A,B,C,D,E,F,L
•Ports 72, 73
VIH(3) •Port 70
Port input/interrupt
Output N-channel
Tr. OFF
•Port 71
RES
•
Input low
voltage
VIH(4) Port 70
Watchdog timer
VIH(5) •Port 8
•Port
74
,75
VIL(1) Port 0 Output disable 4.5 to 6.0 VSS 0.2VDD
VIL(2) •Ports 1, 3
Output N-channel
Tr. OFF
Using as port 4.5-6.0 0.75VDD VDD
Output disable 4.5 to 6.0 VSS 0.25VDD
•Ports A,B,C,D,E,F,L
•Ports 72, 73
VIL(3) •Port 70
Port input/interrupt
Output N-channel
Tr. OFF
•Port 71
•
RES
Operation
VIL(4) Port 70
Watchdog timer
VIL(5) •Port 8
74
•Port
CYC
t
4.5 to 6.0 0.98 400
,75
Output N-channel
Tr. OFF
Using as port 4.5 to 6.0 V SS 0.25VDD
cycle time
Oscillation
frequency
range
(Note 1)
FmCF(1) CF1, CF2 •6MHz (ceramic
resonator oscillation)
•Refer to figure 1
FmCF(2) CF1, CF2 •3MHz (ceramic
resonator oscillation)
•Refer to figure 1
FmRC RC oscillation 4.5 to 6.0 0.4 0.8 3.0
FsXtal XT1, XT2 •32.768kHz (cry stal
oscillation)
•Refer to figure 2
Oscillation
stabilizing
time period
(Note 1)
tmsCF(1) CF1, CF2 •6M H z (ceramic
resonator oscillation)
•Refer to figure 3
tmsCF(2) CF1, CF2 •3M H z (ceramic
resonator oscillation)
•Refer to figure 3
tssXtal XT1, XT2 •32.768kH z (c rystal
oscillation)
•Refer to figure 3
Ratings
VDD[V] min. typ. max.
4.5 6.0
2.5 6.0
2.0 6.0
VDD
+0.9
4.5 to 6.0 0.75VDD VDD
4.5 to 6.0 0.9VDD VDD
4.5 to 6.0 V SS 0.25VDD
4.5 to 6.0 VSS 0.8VDD
4.5 to 6.0 6
4.5 to 6.0 3
4.5 to 6.0 32.768 kHz
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0 s
(Note 1) The oscillation constant is shown on table 1 and table 2.
-1.0
unit
V
s
µ
MHz
ms
No.6838-10/20
LC86P7248
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Input high
current
Input low
current
voltage
Output low
voltage
IIH(1) •Port 1
IIH(2) •Port 7 without
IIH(3) Port 3 VIN=VDD 4.5 to 6.0 1
IIH(4) Ports
IIH(5)
IIH(6)
IIL(1) •Port 1
IIL(2) •Port 7 without
IIL(3) Port 3 VIN=VSS 4.5 to 6.0 -1
IIL(4) Ports
IIL(5)
IIL(6)
VOH(1) Ports 0,1 of
VOH(2) •Port 3 of CMOS
VOL(1) IOL=10mA 4.5 to 6.0 1.5
VOL(2)
VOL(3) Port 70 IOL=1mA 4.5 to 6.0 0.4
VOL(4) IOL=10mA 4.5 to 6.0 1.5
VOL(5)
VOL(6) IOL=8mA 4.5 to 6.0 1.5
VOL(7)
•Port 0 without
pull-up MOS Tr.
pull-up MOS Tr.
•Port 8
A,B,C,D,E,F,L
RES
74
Ports
•Port 0 without
pull-up MOS Tr.
pull-up MOS Tr.
•Port 8
A,B,C,D,E,F,L
RES
Ports
CMOS output
output
•Ports A,B,C,D,E,F
of CMOS output
Ports 0, 1
Port 3
Ports A,B,C,D,E,F
Of CMOS output
,75
74
,75
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VDD
(including the off leak current of the
output Tr.)
VIN=VDD 4.5 to 6.0 1
VIN=VDD 4.5 to 6.0 1
VIN=VDD 4.5 to 6.0 1
Using as port
VIN=VDD
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VSS
(including the off leak current of the
output Tr.)
VIN=VSS 4.5 to 6.0 -1
VIN=VSS 4.5 to 6.0 -1
VIN=VSS 4.5 to 6.0 -1
Using as port
VIN=VSS
IOH=-1.0mA 4.5 to 6.0 VDD-1 Output high
IOH=-1.0mA 4.5 to 6.0 VDD-1
IOL=1.6mA 4.5 to 6.0 0.4
IOL=1.6mA 4.5 to 6.0 0.4
IOL=1.6mA 4.5 to 6.0 0.4
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 1
4.5 to 6.0 1
4.5 to 6.0 -1
4.5 to 6.0 -1
Continue.
unit
A
µ
V
No.6838-11/20
LC86P7248
Parameter Symbol Pins Conditions
LCD output
regulation
VODLS S0 to S47 •Deference voltage
to ideal value
•VLCD, 2/3VLCD,
1/3VLCD
VODLC COM0 to COM3 •Deference voltage
to ideal value
•VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
RLCD(1) Resistance at a
resistor
ladder resisto r
RLCD(2) •Resistance at a
ladder resistor
•1/2R mode
Pull-up MOS
Tr. resistor
Rpu •Ports 0, 1, 3
•Ports A,B,C,D,E,F
VOH=0.9VDD 4.5 to 6.0 15 40 70
•Ports 70, 71, 72, 73
Hysteresis
voltage
Pin
capacitance
VHIS •Port 1
Output disable 4.5 to 6.0 0.1VDD V
•Ports 70, 71, 72, 73
RES
•
CP All pins •f=1MHz
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 0
4.5 to 6.0 0
4.5 to 6.0 60 LCD ladder
4.5 to 6.0 30
4.5 to 6.0 10 pF
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Cycle t
Low Level
CKCY
CKL
t
SCK0,
(1) 2
SCK1
(1) 1
Refer to figure 5. 4.5 to 6.0
pulse width
High Level
Input clock
pulse width
Cycle t
Low Level
Serial clock
pulse width
High Level
Output clock
pulse width
Data set up ti me
Data hold time
Serial input
Output delay time
(Serial clock is
external clock)
Output delay time
Serial output
(Serial clock is
internal clock)
CKH
t
(1)
CKCY
CKL
t
SCK0,
(2) 2
SCK1
(2) 1/2
•Use pull-up
resistor (1kΩ)
when open drain
CKH
t
(2)
output.
•Refer to figure 5.
t
ICK
•SI0,SI1
4.5 to 6.0 0.1
•SB0,SB1
•Data set-up to
SCK0, 1
•Data hold from
CKI
t
CKO(1)
t
•SO0, SO1
4.5 to 6.0
•SB0, SB1
SCK0, 1
•Refer to figure 5.
•Use pull-up
resistor (1kΩ)
when open drain
output.
CKO(2)
t
•Data hold from
SCK0, 1
•Refer to figure 5.
Ratings
VDD[V] min. typ. max.
1
4.5 to 6.0
CKCY
t
1/2
CKCY
t
4.5 to 6.0 0.1
7/12tCYC
4.5 to 6.0
0.2
±
0.2
±
+0.2
1/3tCYC
+0.2
unit
CYC
t
µ
unit
V
kΩ
s
No.6838-12/20
LC86P7248
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
INT3/T0IN
(The noise re je c t i on
clock is selected to
1/16.)
INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
RES
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
Reset acceptable 4.5 to 6.0 2 00
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 1
4.5 to 6.0 2
4.5 to 6.0 32
4.5 to 6.0 128
unit
CYC
t
µ
High/low level
s
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Resolution NAD 4.5 to 6.0 8 bit
Absolute precision
(Note 2)
Conversion time tCAD
Analog input
voltage range
input current
ETAD 4.5 to 6.0
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
VAIN 4.5 to 6.0 VSS VDD V
IAINH VAIN=VDD 4.5 to 6.0 1 Analog port
IAINL
AN0 - AN7
VAIN=VSS 4.5 to 6.0 -1
Ratings
VDD[V] min. typ. max. unit
LSB
1.5
±
4.5 to 6.0
15.68
(tCYC=
0.98µs)
31.36
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
130.56
(tCYC=
4.08µs)
s
µ
A
µ
(Note 2) Absolute precision excepts quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6838-13/20
LC86P7248
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 4)
IDDOP(1) •FmCF=6MHz
IDDOP(2) •FmCF=3MHz
IDDOP(3) •FmCF=0Hz
IDDOP(4)
VDD1=
VDD2=
VDD3
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 15 30
4.5 to 6.0 6 15
4.5 to 6.0 4 13
4.5 to 6.0 4 9
Continue.
unit
mA
No.6838-14/20
LC86P7248
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 4)
Current dissipation
in HOLD mode
(Note 4)
IDDHALT(1) •HALT mode
IDDHALT(2) •HALT mode
IDDHALT(3) •HALT mode
IDDHALT(4)
IDDHALT(5)
IDDHOLD(1) VDD1=
VDD1=
VDD2=
VDD3
VDD2=
VDD3
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•HALT mode
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
HOLD mode
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 6 11
4.5 to 6.0 2.2 9
4.5 to 6.0 500 1700
4.5 to 6.0 25 100
4.5 to 6.0 0.05 30
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
mA
A
µ
No.6838-15/20
LC86P7248
Table 1. Ceramic resonator oscillation guaranteed constant (main clock)
Oscillation type Maker Oscillator C1 C2
6MHz ceramic resonator
oscillation
3MHz ceramic resonator
oscillation
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type Maker Oscillator C3 C4 Rd
32.768kHz crystal oscillation
(Notes) • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
• If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1 CF2
CF
C2C1
XT1 XT2
X'tal
Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit
Rd
C4C3
No.6838-16/20
LC86P7248
y
Power suppl
RES
Reset time
VDD
VDD limit
0V
tmsCF
Internal RC
resonator oscillation
CF1, CF2
XT1, XT2
tssXtal
Instruction
Operation mode
Unfixed Reset Instruction execution mode
execution mode
OCR6=1
< Reset time and oscillation stable time >
HOLD release signal
Valid
Internal RC
resonator oscillation
CF1, CF2
XT1, XT2
tmsCF
tssXtal
Operation mode
HOLD Instruction execution mode
< HOLD release signal and oscillation stable time >
Figure 3 Oscillation stable time
No.6838-17/20
VDD
V
CKO
C
C
CKC
RES
R
LC86P7248
RES
(Note) Fix the value of C
RES
C
sure to reset until 200µs, after Power
supply has be en over inferior limit of
RES
, R
RES
that is
supply voltage.
Figure 4 Reset circuit
0.5VDD
< AC timing point >
Y
SCK0
SCK1
SI0
SI1
S00, S01
SB0, SB1
t
KH tCKL
t
t
KI tICK
t
DD
1kΩ
50pF
< Timing > < Test lo ad >
Figure 5 Serial input / output test condition
tPIL tPIH
Figure 6 Pulse input timing condition
No.6838-18/20
LC86P7248
Notice for use
The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for Sanyo to
•
completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown
in the following figure should always be followed.
It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be guaranteed.
•
• Keeping the dry packing
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
After openi ng the packing
•
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the
substrate. Note that the QIP package should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This
baking is called pre-baking). After pre-baking, a controlled environment must be maintained until soldering. The
environment must be held at a temperature of 30°C or less and a humidity level o f 70% or less. Please sold er within 24
hours.
a. Shipping with a blank PROM b. Shipping with a programmed PROM
(Programming the data by yourself) (Programming the data by Sanyo)
QIP
Writing data for program/Verifying
Recommended process of screening
Heat-soak
Baking
Mounting
+1
-0
150±5°C, 24 Hr
Reading ascertain of program
VDD=5±0.5V
Baking before mounting
125°C, 12 hours
QIP
Baking before mounting
125°C, 12 hours
Baking
Mounting
No.6838-19/20
memo :
LC86P7248
No.6838-20/20
PS
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