Page 1
Ordering number : ENN*6692
CMOS IC
LC86P7148
8-Bit Single Chip Microcontroller
with One-Time Programmable PROM
Preliminary
Overview
The LC86P7148 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC867100 series. This
microcontroller has the function and the pin description of the LC867100 series mask ROM version, and 48K-byte PROM.
QFP package are available for shipping as well as LC867100 series. It is suitable to set up first release, prototyping,
developing and testing of set.
Features
(1) Option switching by PROM data
The option function of the LC867100 series can be specified by the PROM data.
LC86P7148 can be checked the functions of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity : 49152 bytes
(3) Internal RAM capacity : 1152 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P7148.
Mask ROM version PROM capacity RAM capacity
LC867148 49152 bytes 1152 bytes
LC867140 40960 bytes 1152 bytes
LC867132 32768 bytes 768 bytes
LC867128 28672 bytes 768 bytes
LC867124 24576 bytes 768 bytes
LC867120 20480 bytes 640 bytes
LC867116 16384 bytes 640 bytes
LC867112 12288 bytes 512 bytes
LC867108 8192 bytes 512 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping
and the screening. Contact our representative for further information.
Ver.1.00
D2994
91400 RM (IM) HK No.6692-1/21
Page 2
LC86P7148
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 1µs to 366µs
(6) Operating temperature : -30°C to +70°C
(7) The pin compatible with the LC867100 series mask ROM devices
(8) Applicable mask ROM version : LC867148/LC867140/LC867132/LC8671 28/LC867124/LC867120
/LC867116/LC867112/LC867108
(9) Factory shipment : QFP80E
Notice for use
LC86P7148 is provided for the first release and small shipping of the LC867100 series.
At using, take notice of the followings.
(1) A point of difference LC86P7148 and LC867100 series
Item LC86P7148 LC867148/40/32/28/24/20/16/12/08
Operation after reset
releasing
Operating supply
voltage range (VDD)
Total output current
[∑IOAL(2)]
[∑IOAL(3)]
Power dessipation
LC86P7148 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data
area. T his option configuration can execute all options which LC867100 series have. Next tables show the options that
correspond and not correspond to LC86P7148.
• A kind of the option corresponding of the LC86P7148
A kind of option Pins, Circuits Contents of the option
Input/output form of
input/output ports
Pull-up MOS Tr. of
input port
*1) Specified in a bit.
*2) Specified in nibble unit. Pull-up MOS Tr. is not provided in N-channel open drain output port.
The option is specified until 3ms after going
to a ‘H’ level to the reset terminal by
degrees. The program is executed from 00H
of the program counter.
4.5V to 6.0V 2.5V to 6.0V
Refer to ‘electrical characteristics’ on the semiconductor news.
Port 0
(specified in a bit)
Port 1
(specified in a bit)
*1
Port 7
(specified in a bit) *1
Each of P74 and P75 has no
option
1. Input : No Pull-up MOS Tr .
Output : N-channel open drain *1
2. Input : Pull-up MOS Tr.
Output : CMOS *2
1. Input : Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. No Pull-up MOS Tr.
2. Pull-up MOS Tr.
The program is executed from 00H of the
program counter immediately after going to
a ‘H’ level to the reset terminal.
No.6692-2/21
Page 3
LC86P7148
(2) Option
The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the
program area by linkage loader “L86K.EXE” .
(3) ROM space
LC86P7148 and LC8671 00 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Program area
48K bytes
LC867148 LC867140
Option
Data Area
Program area
40K bytes
Option
Data Area
Program area
32K bytes
LC867132
Option
Data Area
Program area
28K bytes
LC867128
Option
Data Area
Program area
24K bytes
LC867124
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Program area
20K bytes
LC867120 LC867116
Option
Data Area
Program area
16K bytes
Option
Data Area
Program area
12K bytes
LC867112
Option
Data Area
Program area
8K bytes
LC867108
(4) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
No.6692-3/21
Page 4
LC86P7148
How to use
(1) Specification of option
The LC86P7148 must be programmed after specifying option data. The option is specified by “SU86K.EXE”. The
specified option file and the file created by our macro assembler “M86K.EXE” are linked by our linkage loader
“L86K.EXE” which creates .HEX file, then the option code is put in the option specified area (0FF00H to 0FFFFH) of
its .HEX file.
(2) How to program for the EPROM
The LC86P7148 can be programmed by EPROM programmer with attachment ; W86EP7148Q
• Recommended EPROM programmer
Productor EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0 to 0FFFFH” and a
jumper (DASEC) must b e set to ‘OFF’ at progr amming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK=>PROGRAM=>VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
Data security
Not data security
W86EP7148Q
No.6692-4/21
Page 5
LC86P7148
Pin Assignment
COM0/PL0
V1/PL4
V2/PL5
V3/PL6
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S13/PB5
S12/PB4
VSS3
VDD3
COM1/PL1
COM2/PL2
COM3/PL3
VSS2
VDD2
P00
P01
P02
P03
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
64
63
62
61
60
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9
59
58
57
56
55
10
54
11
53
12
52
13
51
14
50
15
49
16
48
17
47
18
46
19
45
20
44
21
43
22
42
23
41
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
S0/PA0
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P93/DA3/AN11
CF1
P13/SO1
P15/SCK1
P14/SI1/SB1
RES
P16/BUZ
XT1/P74
P70/INT0
P17/PWM0
CF2
VSS1
XT2/P75
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P90/DA0/AN8
P91/DA1/AN9
P92/DA2/AN10
Package Dimension
(unit : mm)
3174
SANYO : QIP-80E
Notes •The QFP packages should be heat-soaked for 12 hours at 1 25°C immediately prior to mounting (This baking is called
pre-baking).
•After pre-baking a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6692-5/21
Page 6
System Bl ock Diagram
y
SIO0
SIO1
Timer 0
Timer 1
Real Time Service
RAM
128 b
LCD
Controller
S0 – S7 (PA)
S8 – S13 (PB)
S16 – S23 (PC)
S24 – S31 (PD)
COM0 – COM3(PL)
tes
Interrupt Control
Stand-by C ontr ol
X’tal
CF
RC
Clock
Generator
Bus Interface Base Timer
Port 1
Port 7
Port 8
Port 9
ADC
INT0 - 3
Nose Filter
DAC
LC86P7148
IR
PROM
Control
PROM(48KB)
PC
ACC
B Register
C Register
ALU
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog T i mer
PLA
A15-A0
D7-D0
TA
CE
OE
DASEC
No.6692-6/21
Page 7
LC86P7148
l
Pin Description
Pin name I/O Function description Option PROM mode
VSS1 *1 - Power pin (–) -
VSS2 *1 - Power pin (–) -
VSS3 *1 - Power pin (–) -
VDD1 *1 - Power pin (+) -
VDD2 *1 - Power pin (+) -
VDD3 *1 - Power pin (+) -
PORT0
P00 - P07
I/O • 8-bit input/output port
Input/output in nibble units
• Input for port 0 interrupt
• Input for HOLD release
• Pull-up resistor :
Provided/Not provided
(specified in nibble units)
• Output form (P00 – P07) :
CMOS/N-channel open drain
(specified in a bit)
PORT1
P10 - P17
I/O • 8-bit input/output port
Input/output can be specified in bit unit
• Other pin functions
• Output form :
CMOS/N-channel open drain
(specified in a bit)
Data line
D0 to D7
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer1 output (PWM output)
PORT7
P70
P71 - P73
P74
- P75
• 6-bit input port
• Other pin functions
I/O
P70 : INT0 input/HOLD release input/
N-channel Tr. output for watchdog
I
timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
• Interrupt received form, vector address
I
rising falling rising
&
high
level
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
P74
: XT1 terminal for crystal oscillation
Pull-up resistor :
Provided/Not provided
(specified in a bit)
(P70, P71, P72 , P73)
P74
, P75 don’t have the
*
pull-up resistor option.
low
vector
level
Power for
programming
PROM contro
signals
DASEC(*2)
(*3)
OE
(*4)
CE
P75 : XT2 terminal for crystal oscillation
Port8
P80 – P87
I • 8-bit input port
• Other function
-
AD input port (8 port pins)
PORT9
P90 - P93
I/O • 4-bit input/output port
• Other function
-
DA output port (4 port pins)
AD input port (4 port pins)
No.6692-7/21
Page 8
LC86P7148
Pin name I/O Function description Option PROM mode
PORT A
(S0/PA0 –
S7/PA7)
PORT B
(S8/PB0 –
S13/PB5)
PORT C
(S16/PC0 –
S23/PC7)
I/O • Segment output term inal for LCD display
• Can be used as a general input/output port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
- Address
input
A0 to A7
- Address
input
A8 to A13
- PROM
control
signal input
•TA(*5)
Address input
•A14,A15
PORT D
(S24/PD0 –
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
-
S31/PD7)
PORT L
(COM0/PL0 –
I/O • Common output terminal for LCD display
• Can be used as a general input port
-
COM3/PL3)
V1/PL4 –
V3/PL6
RES
P74
XT1/
I • Bias power terminal for LCD drive
-
• Can be used as a general input port
I Reset pin -
I • Input pin for 32.768kHz crystal oscillation
-
In case of non use, connect to VDD.
• Other function
A general input port
XT2/P75 O
• Output pin for 32.768kHz crystal oscillation
In case of non use, should be left unconnected
( I )
• Other function
P74
-
A general input port P75
CF1 I Input pin for ceramic resonator oscillation -
CF2 O Output pin for ceramic resonator oscillation -
* All of port options can be specified in bit unit except the pull-up resistor of port 0.
[Notes] • The VDD1 , VDD2 and VDD3 terminals must be shorted electrically each other.
• The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other.
*1 Connect like the following figure to reduce noise into a VDD terminals.
LSI
VDD1
Power
Supply
VDD2
VDD3
VSS1 VSS2
VSS3
*2 Memory select input for data security
*3 Output enable input
*4 Chip enable input
*5 TA ! PROM contro l signal input
No.6692-8/21
Page 9
LC86P7148
V
1. Absolute Maximum Ratings at Ta=25°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Supply voltage VDDMAX VDD1, VDD2
VDD3
LCD display
voltage
VLCD V1/PL6, V2/PL5
V3/PL4
Input voltage VI •Ports 71, 72, 73
•Ports
74
, 75
VDD1=VDD2=
VDD3
VDD1=VDD2=
VDD3
-0.3 VDD+0.3
Ratings
DD[V] min. typ. max.
-0.3 +7.0
-0.3 VDD
unit
V
•Port 8, Port L
RES
•
Input/output
voltage
VIO •Ports 0, 1
•Port 9
-0.3 VDD+0.3
•Ports A, B, C, D
High
level
output
current
Peak
output
current
Total
output
current
Low
level
output
Peak
output
current
current
Total
output
current
Maximum power
IOPH(1) P orts 0, 1 -4
IOPH(2) Ports A, B, C, D -4
IOPH(3) Port 9
IOAH(1)
Σ
ΣIOAH(2)
IOAH(3)
Σ
ΣIOAH(4)
Ports 0, 1 Total all pins -30
Ports A, B Total all pins -20
Ports C, D Total all pins -20
Port 9 Total all pins -20
•CMOS output
•At each pins
-4
mA
IOPL(1) Ports 0, 1 At each pins 20
IOPL(2) Ports A, B, C, D At each pins 20
IOPL(3) Port 9 At each pins 20
IOPL(4) Port 70 At each pins 15
IOAL(1)
Σ
ΣIOAL(2)
IOAL(3)
Σ
ΣIOAL(4)
IOAL(5)
Σ
Ports 0, 1 Total all pins 40
Ports A, B Total all pins 24
Ports C, D Total all pins 24
Port 9 Total all pins 15
Port 70 Total all pins 10
Pdmax QFP80E Ta=-30 to+70°C 515 mW
dissipation
Operating
Topr -30 +70
C
°
temperature
range
Storage
Tstg -65 +150
temperature
range
Notes •The QFP packages should be heat-soaked for 12 hours at 1 25°C immediately prior to mounting (This baking is called
pre-baking).
•After pre-baking a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6692-9/21
Page 10
LC86P7148
2. Recommended Operating Range at Ta=- 30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
supply voltage
range
VDD(1)
VDD(2)
VDD1,VDD2,VDD3
0.98µs ≤ tCYC
≤ 400µs
3.9µs ≤ tCYC
Ratings
VDD[V] min. typ. max.
4.5 6.0 Operating
2.5 6.0
≤ 400µs
Hold voltage VH D VDD1,VDD2,VDD3 RAMs and the
2.0 6.0
registers hold
voltage at HOLD
mode.
Input high
voltage
VIH(1) Port 0 Output disable 4.5-6.0 0.4VDD
+0.9
VIH(2) •Ports 1, 9
Output disable 4.5-6.0 0.75VDD VDD
•Ports A, B, C, D
•Ports 72, 73 (Schmitt)
VIH(3) •Port 70
Port input/interrupt
Output N-channel
Tr. OFF
4.5-6.0 0.75VDD VDD
•Port 71
RES
Input low
voltage
•
(Schmitt)
VIH(4) Port 70
Watchdog timer
VIH(5) •Port 8
•Ports
74
, 75
VIL(1) Port 0 Output disable 4.5-6.0 VSS 0.2VDD
VIL(2) •Ports 1, 9
Output N-channel
4.5-6.0 0.9VDD VDD
Tr. OFF
Using as port 4.5-6.0 0.75VDD VDD
Output disable 4.5-6.0 VSS 0.25VDD
•Ports A, B, C, D
•Ports 72, 73 (Schmitt)
VIL(3) •Port 70
Port input/interrupt
Output N-channel
Tr. OFF
4.5-6.0 VSS 0.25VDD
•Port 71
RES
•
(Schmitt)
VIL(4) Port 70
Watchdog timer
VIL(5) •Port 8
Output N-channel
4.5-6.0 VSS 0.8VDD
Tr. OFF
Using as port 4.5-6.0 VSS 0.25VDD
•Ports 74, 75
Operation
tCYC 4.5-6.0 0.98 400
cycle time
unit
VDD
-1.0
µ
V
s
No.6692-10/21
Page 11
LC86P7148
Parameter Symbol Pins Conditions
Oscillation
frequency
range
(Note 1)
FmCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
FmCF(2) CF1, CF2 •3MHz
(ceramic resonator
oscillation)
•Refer to figure 1
FmRC RC oscillation 4.5-6.0 0.4 0.8 3.0
FsXtal XT1, XT2 •32.768kHz
(crystal oscillation)
•Refer to figure 2
Oscillation
stabilizing
time period
(Note 1)
tmsCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tmsCF(2) CF1, CF2 •3MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tssXtal XT1, XT2 •32.768kHz
(crystal oscillation)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
Ratings
VDD[V] min. typ. max.
4.5-6.0 5.88 6 6.12
unit
MHz
4.5-6.0 2.94 3 3.06
4.5-6.0 32.768 kHz
4.5-6.0 0.05 0.5
ms
4.5-6.0 0.10 1.00
4.5-6.0 s
No.6692-11/21
Page 12
LC86P7148
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Input high
current
IIH(1) •Port 1
•Port 0 without
pull-up MOS Tr.
•Out put dis a ble
•Pull-up MOS Tr.
OFF. VIN=VDD
Ratings
VDD[V] min. typ. max.
4.5-6.0 1
(including the off leak current of the
output Tr.)
IIH(2) •Port 7 without
VIN=VDD 4.5-6.0 1
pull-up MOS Tr.
•Port 8
IIH(3) Port 9 VIN=VDD 4.5-6.0 1
IIH(4) Ports A, B, C, D, L VIN=VDD 4.5-6.0 1
IIH(5)
IIH(6)
RES
Ports
74
,75
VIN=VDD 4.5-6.0 1
Using as port
4.5-6.0 1
VIN=VDD
Input low
current
IIL(1) •Port 1
•Port 0 without
pull-up MOS Tr.
•Out put dis a ble
•Pull-up MOS Tr.
OFF. VIN=VSS
4.5-6.0 -1
(including the off-
leak current of the
output Tr.)
IIL(2) •Port 7 without
VIN=VSS 4.5-6.0 -1
pull-up MOS Tr.
•Port 8
IIL(3) Port 9 VIN=VSS 4.5-6.0 -1
IIL(4) Ports A, B, C, D, L VIN=VSS 4.5-6.0 -1
IIL(5)
IIL(6)
RES
Ports
74
,75
VIN=VSS 4.5-6.0 -1
Using as port
4.5-6.0 -1
VIN=VSS
voltage
VOH(1) Ports 0,1 of
CMOS output
VOH(2) •Port 9 of CMOS
IOH=-1.0mA 4.5-6.0 VDD-1 Output high
IOH=-1.0mA 4.5-6.0 VDD-1
output
•Ports A, B, C, D
of CMOS output
Output low
voltage
VOL(1) IOL=10mA 4.5-6.0 1.5
VOL(2)
Ports 0, 1
IOL=1.6mA 4.5-6.0 0.4
VOL(3) Port 70 IOL=1mA 4.5-6.0 0.4
VOL(4) IOL=6mA 4.5-6.0 1.5
VOL(5)
VOL(6) IOL=8mA 4.5-6.0 1.5
VOL(7)
Port 9
Ports A, B, C, D
of CMOS output
IOL=1.2mA 4.5-6.0 0.4
IOL=1.6mA 4.5-6.0 0.4
Continue.
unit
µA
V
No.6692-12/21
Page 13
LC86P7148
7
Parameter Symbol Pins Conditions
regulation
VODLS S0 to S13,
S16 to S31
•Deference voltage
to ideal value
•VLC D, 2/3VLCD ,
1/3VLCD
VODLC COM0 to COM3 •Deference voltage
to ideal value
•VLC D, 2/3VLCD ,
1/2VLCD, 1/3VLCD
RLCD(1) Resistance at a
resistor
ladder resistor
RLCD(2) •Resistance at a
ladder resistor
•1/2R mode
Pull-up MOS
Tr. resistor
Rpu •Ports 0, 1
•Ports A, B, C, D
VOH=0.9VDD 4.5-6.0 15 40 70
•Ports 70, 71, 72, 73
Hysteresis
voltage
VHIS •Ports 0, 1
•Ports 70, 71, 72, 73
RES
•
Output disable 4.5-6.0 0.1VDD V
Pin capacitance CP All pins •f=1MHz
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
Ratings
VDD[V] min. typ. max.
4.5-6.0 0 ±0.2 LCD output
unit
V
4.5-6.0 0 ±0.2
4.5-6.0 60 LCD ladder
kΩ
4.5-6.0 30
4.5-6.0 10 pF
4. Serial Input/Output Cha racteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Cycle tCKCY(1) 4.5-6.0 2
Low Level
tCKL(1) 4.5-6.0 1
SCK0,
SCK1
Refer to figure 5.
Ratings
VDD[V] min. typ. max.
unit
tCYC
pulse width
High Level
Input clock
pulse width
Cycle tCKCY(2) 4.5-6.0 2
Serial clock
Low Level
pulse width
High Level
Output clock
pulse width
Data set up time
Data hold time
Serial input
Output delay time
(Serial clock is
external clock)
Output delay time
Serial output
(Serial clock is
internal clock)
tCKH(1)
SCK0,
tCKL(2) 4.5-6.0 1/2
SCK1
•Use pull-up
resistor (1kΩ)
when open drain
tCKH(2)
output.
•Refer to figure 5.
tICK 4.5-6.0 0.1
•SI0,SI1
•SB0,SB1
•Data set-up to
SCK0, 1
4.5-6.0 1
tCKCY
4.5-6.0 1/2
tCKCY
s
µ
•Data hold from
tCKI
SCK0, 1
4.5-6.0 0.1
•Refer to figure 5.
tCKO(1) 4.5-6.0
•SO0, SO1
•SB0, SB1
•Use pull-up
resistor (1kΩ)
/12tCYC
+0.2
when open drain
output.
tCKO(2)
•Data hold from
SCK0, 1
4.5-6.0 1/3tCYC
+0.2
•Refer to figure 5.
No.6692-13/21
Page 14
LC86P7148
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
High/low level
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
Ratings
VDD[V] min. typ. max.
4.5-6.0 1
4.5-6.0 2
unit
tCYC
clock is selected to
1/1.)
tPIH(3)
tPIL(3)
INT3/T0IN
(The noise rejection
•Interrupt acceptable
•Timer0-countable
4.5-6.0 32
clock is selected to
1/16.)
tPIH(4)
tPIL(4)
INT3/T0IN
(The noise rejection
•Interrupt acceptable
•Timer0-countable
4.5-6.0 128
clock is selected to
1/64.)
tPIL(5)
RES
Reset acceptable 4.5-6.0 200
s
µ
6. AD Converter Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Ratings
VDD[V] min. typ. max.
unit
Resolution NAD 4.5-6.0 8 bit
Absolute precision
ETAD 4.5-6.0 ±1.5 LSB
(Note 2)
Conversion time tCAD
AD conversion time =
16 × tCYC
(ADCR2=0)
4.5-6.0
68
15.
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
s
µ
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
(Note 3)
Analog input
VAIN 4.5-6.0 VSS VDD V
AN0 - AN11
voltage range
input current
IAINH VAIN=VDD 4.5-6.0 1 Analog port
IAINL
VAIN=VSS 4.5-6.0 -1
µA
(Note 2) Absolute precision excepts quantizing error (±1/2 LSB).
(Note 3) T he conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6692-14/21
Page 15
LC86P7148
7. DA Converter Charact er istics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Resolution NDA 4.5-6.0 8 bit
Total error
Settling time tSAD (Note 4) 4.5-6.0 0.5
Analog output
voltage range
Output resistor RODA (Note 5) 4.5-6.0 4
VAOUT DA0 to DA3
8 bit mode 1.0
9 bit mode 0.8
9.5 bit mode
8 bit mode VSS VDD
9 bit mode (1) VSS 1/2VDD
9 bit mode (2) 1/2VDD VDD
9.5 bit mode
Ratings
VDD[V] min. typ. max.
4.5-6.0
0.7
4.5-6.0
1/3VDD 2/3VDD
unit
%
µ
V
kΩ
s
(Note 4) Settling time means the time from executing the DA conversion instruction to generating the analog voltage output
corresponding to the digital data on the specific port.
(Note 5) DA data = 80H
8. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 6)
IDDOP(1) •FmCF=6MHz
IDDOP(2) •FmCF=3MHz
IDDOP(3) •FmCF=0Hz
IDDOP(4)
VDD1=
VDD2=
VDD3
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
(when oscillation stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Ratings
VDD[V] min. typ. max.
4.5-6.0 15 30
4.5-6.0 6 15
4.5-6.0 4 13
4.5-6.0 4 9
unit
mA
Continue.
No.6692-15/21
Page 16
LC86P7148
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 6)
Current dissipation
in HOLD mode
(Note 6)
IDDHALT(1) •HALT mode
IDDHALT(2) •HALT mode
IDDHALT(3) •HALT mode
IDDHALT(4)
IDDHALT(5)
IDDHOLD(1) VDD1=
VDD1=
VDD2=
VDD3
VDD2=
VDD3
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•Syste m clock :
RC oscillation
•1/2 divided
•HALT mode
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
HOLD mode
Ratings
VDD[V] min. typ. max.
4.5-6.0 6 11
4.5-6.0 2.2 9
4.5-6.0 500 1700
4.5-6.0 25 100
4.5-6.0 0.05 30
(Note 6) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
mA
A
µ
No.6692-16/21
Page 17
LC86P7148
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type Maker Oscillator C1 C2
6MHz ceramic resonator
oscillation
Kyocera
CSA6.00MG 33pF 33pF Murata
CST6.00MGW on chip
KBR-6.0MSA 33pF 33pF
PBRC6.00A(chip
33pF 33pF
type)
KBR-6.0MKS
on chip
PBRC6.00B(chip
type)
3MHz ceramic resonator
oscillation
CSA3.00MG 33pF 33pF Murata
CST3.00MGW on chip
Kyocera KBR-3.0MS 47pF 47pF
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub clock)
Oscillation type Maker Oscillator C3 C4
32.768kHz crystal
oscillation
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation
pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1 CF2 XT1 XT2
CF
C2 C1
X’tal
C4 C3
Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit
No.6692-17/21
Page 18
LC86P7148
Power supply
VDD
VDD limit
0V
RES
Reset time
Internal RC
resonator oscillation
tmsCF
CF1, CF2
XT1, XT2
tssXtal
Instruction
Operation mode
Unfixed Instruction execution mode Reset
execution mode
OCR6=1
<Reset time and oscillation stable time>
HOLD release signal
Valid
Internal RC
resonator oscillation
tmsCF
CF1, CF2
XT1, XT2
tssXtal
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3 Oscillation stable time
No.6692-18/21
Page 19
LC86P7148
tCKO
tC
tICK tC
tC
tCKC
g p
V
VDD
RES
RES
R
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has be en over inferior limit of
RES
C
supply voltage.
Figure 4 Reset circuit
<AC timin
0.5VDD
oint>
Y
DD
SCK0
SCK1
KL
SI0
SI1
SO0, SO1
SB0, SB1
<Timing>
KI
KH
1k
50pF
<Test load>
Figure 5 Serial input / output test condition
tPIH tPIL
Figure 6 Pulse input timing condition
No.6692-19/21
Page 20
LC86P7148
Notice for use
• The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for SANYO
to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown
in the following figure should always be followed.
• It is not possible to perform a writing test on the blank PROM.. 100% yield, therefore, cannot be guaranteed.
• Keeping the dry packing
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
• After opening the packing
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the
substrate. Note that the QFP package should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This
baking is called pre-baking). After pre-baking, a controlled environment must be maintained until soldering. The environment
must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
a. Shipping with a blank PROM b. Shipping with a programmed PROM
(Programming the data by yourself) (Programming the data by Sanyo)
QFP
QFP
Writing data for program/Verifying
Recommended process of screening
Baking before mounting
125°C, 12 hours
Baking
Heat-soak
150±5°C, 24 Hr
+1
-0
Mounting
Reading ascertain of program
VDD=5±0.5V
Baking before mounting
125°C, 12 hours
Baking
Mounting
No.6692-20/21
Page 21
LC86P7148
No.6692-21/21
PS
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